NV3029datasheet V1.9

New Vision Microelectronics Inc.
NV3029 Data sheet
240RGB x 320dot, 262,144-color

TFT Controller Driver with Internal RAM
Preliminary Version 1.9

October 14, 2010
NV3029—240RGB x320dot, 262,144-color TFT Controller Driver ©2010
Index
Introduction ......................................................................................................................................5
Features ............................................................................................................................................6
Block Diagram .................................................................................................................................7
Pin Function .....................................................................................................................................8
Pad Arrangement ............................................................................................................................12
Bump information ..........................................................................................................................13
Pad coordinates...............................................................................................................................14
Bump Size ......................................................................................................................................22
Block Function ...............................................................................................................................24
1. System Interface ................................................................................................................................ 24
2. External Display Interface (RGB, VSYNC interfaces)...................................................................... 24
3. Address Counter (AC) ....................................................................................................................... 24
4. Graphics RAM (GRAM) ................................................................................................................... 24
5. Grayscale Voltage Generating Circuit ............................................................................................... 25
6. Timing Generator............................................................................................................................... 25
7. Oscillator (OSC) ................................................................................................................................ 25
8. Liquid crystal driver Circuit............................................................................................................... 25
9. Internal logic power supply regulator ................................................................................................ 25
10. Liquid crystal drive power supply circuit ........................................................................................ 25
Instruction.......................................................................................................................................26
Driver Code Read(R00h) ........................................................................................................................ 29
Driver Output Control (R01h) ................................................................................................................ 29
LCD AC Driving Control (R02h) ........................................................................................................... 29
Entry Mode (R03h)................................................................................................................................. 30
Display Control 1 (R07h) ....................................................................................................................... 30
Display Control 4 (R0Ah)....................................................................................................................... 33
External Display Interface Control 1 (R0Ch) ......................................................................................... 33
Frame Marker Position (R0Dh) .............................................................................................................. 34
External Display Interface Control 2 (R0Fh).......................................................................................... 35
Power Control 1 (R10h).......................................................................................................................... 35
Power Control 1 (R12h).......................................................................................................................... 35
RAM access instruction .......................................................................................................................... 36
RAM Address Set (Horizontal Address) (R20h) .................................................................................... 36
RAM Address Set (Vertical Address) (R21h) ........................................................................................ 36
Write Data to GRAM (R22h) ................................................................................................................. 36
Read Data from GRAM (R22h).............................................................................................................. 40
Gamma Control (R30h to R3Dh)............................................................................................................ 41
Gamma control (R40h toR4Dh) ............................................................................................................. 41
Gamma control (R70h toR7Dh) ............................................................................................................. 41
Window address control instruction ....................................................................................................... 43
RAM Horizontal Start Address Position (R50h)................................................................................ 43
RAM Horizontal End Address Position (R51h)................................................................................. 43
RAM Vertical Start Address Position (R52h).................................................................................... 43
RAM Vertical End Address Position (R53h)..................................................................................... 43
New Vision Microelectronics Inc. Page 2

Driver Output Control 1 (R60h) ............................................................................................................. 43

Base Image Display Control (R61h)....................................................................................................... 43
Vertical Scroll Control (R6Ah)............................................................................................................... 43
Partial display control instruction ........................................................................................................... 45
Display Position (R80h),.................................................................................................................... 45
RAM Address (Start/End Line Address) (R81h/R82h) ..................................................................... 45
Display Position (R83h),.................................................................................................................... 45
RAM Address (Start/End Line Address) (R84h/R85h) ..................................................................... 45
Panel interface control ............................................................................................................................ 46
Panel interface control 0 (R90h) ........................................................................................................ 46
Power Control 4 (R14h)..................................................................................................................... 50
Power Control 10 (R1Ah) .................................................................................................................. 51
Power Control 11 (R1Bh) .................................................................................................................. 52
Power Control 12 (R1Ch) .................................................................................................................. 52
Power Control 13 (R1Dh) .................................................................................................................. 52
Internal use(R1Eh,R1Fh)(R65h) ........................................................................................................ 53
OTP Control(R66h) ................................................................................................................................ 53
CABC Control ........................................................................................................................................ 54
Interface Specifications ..................................................................................................................57
System Interface ..................................................................................................................................... 58
1. 80-system 18-bit interface............................................................................................................. 58
2. 80-system 16-bit interface............................................................................................................. 59
3. 80-system 9-bit interface............................................................................................................... 60
4. 80-system 8-bit interface............................................................................................................... 61
5. Data transfer synchronization in 8/9-bit bus interface mode......................................................... 62
6. Serial Peripheral interface (SPI).................................................................................................... 62
RGB interface timing .....................................................................................................................65
6-bit RGB interface............................................................................................................................ 67
16-bit RGB interface.......................................................................................................................... 68
18-bit RGB interface.......................................................................................................................... 69
VSYNC Interface ...........................................................................................................................71
Partial Display Function .................................................................................................................75
Window Address Function .............................................................................................................76
8-color Display Mode.....................................................................................................................77
OTP Operation ...............................................................................................................................78
CABC(Content Adaptive Brightness Control) ...............................................................................80
Gamma Correction .........................................................................................................................81
Power Supply Setting .....................................................................................................................89
Voltage Generation.........................................................................................................................90
Application .....................................................................................................................................91

Electrical Characteristics ................................................................................................................92

Absolute Maximum Ratings ................................................................................................................... 92
DC Characteristic.................................................................................................................................... 92
AC Characteristics .................................................................................................................................. 93
Serial interface Timing Characteristics................................................................................................... 94
Reset Timing Characteristics .................................................................................................................. 95
Liquid crystal driver Output Characteristics........................................................................................... 96
RGB Interface Timing Characteristics.................................................................................................... 96
Revision history..............................................................................................................................98

Introduction
NV3029 is a 262,144-color one-chip SOC driver for a-TFT liquid crystal display with resolution of
240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes
RAM for graphic data of 240RGBx320 dots, and power supply circuit.
NV3029 has four kinds of system interfaces which are i80-system MPU interface (8-/9-/16-/18-bit bus
width),VSYNC interface (system interface + VSYNC, internal clock, DB[17:0]), serial data transfer
interface (SPI) and RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, DB[17:0]).
In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and
widow address function enables to display a moving picture at a position specified by a user and still
pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh
data only to minimize data transfers and power consumption.
NV3029 can operate with 1.65V I/O interface voltage, and an incorporated voltage follower circuit to
generate voltage levels for driving an LCD. The NV3029 also supports a function to display in 8 colors
and a sleep mode, allowing for precise power control by software and these features make the NV3029 an
ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone,
PDA and PMP where long battery life is a major concern.

Features
¾ One-chip controller driver for 240RGB x 320-dot graphics display in 262,144 colors on TFT panel
¾ One-chip solution for a-Si TFT panel
¾ System interface
– High-speed interface via 8-, 9-, 16-, 18-bit parallel ports
– Clock synchronous serial interface
¾ Moving picture display interface
– RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, DB17-0) via 6-, 16-, 18-bit ports
– VSYNC interface
¾ Window address function to specify a rectangular area in the internal RAM to write data
– Writes data within a rectangular area on the internal RAM via moving picture interface
– Reduces data transfer by specifying the area on the RAM to rewrite data
– Enables displaying the data in the still picture RAM area with a moving picture simultaneously
¾ Color display control functions
– correction function to display in 262k colors
– 1-line unit vertical scroll function
¾ Low -power consumption architecture (allowing direct input of interface I/O power supply)
– 8-color display function
– Input power supply voltages: IOVCC = 1.65V ~ 3.6 V (interface I/O power supply)
VCI = 2.5V ~ 3.3 V (liquid crystal analog circuit power supply)
(VCI-VCL ≤ 6.0V)
¾ Incorporates a liquid crystal drive power supply circuit
– Source driver liquid crystal drive/Vcom power supply: DDVDH-GNDA = 4.5V ~ 6.0V
– Gate drive power supply: VGH-VGL ≤ 28.0V
– Vcom drive (Vcom power supply): VcomH = 2.5V ~(DDVDH-0.5)V
VcomL = (VCL+0.5)V ~ GND
¾ 172800-byte internal RAM
¾ CABC(Content Adaptive Brightness Control)
¾ Internal liquid crystal drive circuit: 720-channel source output and 320-channel gate output
¾ N-line-inversion liquid crystal drive to invert polarity of liquid crystal in a cycle of arbitrary line
period
¾ Internal oscillator, Hardware Reset
¾ TFT storage capacitor: Cst only

Block Diagram
18 Index
register
IOVCC (IR)
MPU I/F
IM[3:0]
-18 bit 7
CS -16 bit
-9 bit Address
RS 18 Control LCD
-8 bit Counter
Register Source S1~72
WR (AC)
(CR) Driver 0
RD
SDA SPI I/F
18
SDO RGB I/F Graphics
18
18 bit Operation
DB0-17
16 bit
VSYNC
6 bit
HSYNC 18
Read Write Grayscale VREG1OUT
Latch Latch Reference
DOTCLK
VSYNC I/F 18
Voltage VGS
18
ENABLE
Graphics RAM
(GRAM)
CABC
VDD
Block
VCI Regulator
GND Brightness
Control
BC_CTRL
LCD G1~G32
VCI Gate
Timing 0
VCI1 RC-OSC Driver
Controller
GND
VCOM
Charge-pump Power Circuit
Generator VCOM
C11P
C22P
C12N
C21N
C22N
C13N
C13P
C11N
VCL
C12P
C21P
DDVDH
VGH
VGL

Pin Function
Power supply
Signal Connect to Function
IOVCC I/O voltage Low voltage power supply for interface logic circuits(1.65~3.3V)
LED driver Power supply for LED driver interface.(1.65~3.3V)
VDD3-P Power If LED driver is not used, fix this pin at IOVCC.
Power supply to liquid crystal power supply analog circuit. Connect
VCI Analog Power
to an external power supply of 2.5V ~ 3.3V.
Regulated Digital circuit power pad.
VDD Voltage Connect these pins with the 1uF capacitor.
GNDR I/O Ground System ground level for I/O circuits.
GND Logic Ground System ground level for logic blocks

Analog System ground level for analog circuit blocks
GNDA Ground Connect to GND on the FPC to prevent noise
Regulated Digital circuit power pad.
VDDR Voltage Connect these pins with VDD.
Test pins
Signal I/O Function
TREGB I Dummy pin. Connect this pad to GND.
DUMMYR1
I Dummy pin. Leave these pads open.
DUMMYR2
TMODE[3:0] - Dummy pin. Leave these pads open.
TMUX[2:0] - Dummy pin. Leave these pads open.
EXCLK - Dummy pin. Leave these pads open.
DB[23:18] - Dummy pin. Leave these pads open.
VCIR_EXIN - Dummy pin. Leave these pads open.
DUMMY - Dummy pin. Leave these pads open.
VCI1 Dummy pin. Leave these pads open.

Interface logic pins
Signal I/O Function

Select the MPU system interface mode
MPU interface
IM3 IM2 IM1 IM0 DB pins
Mode
0 0 0 0 Setting invalid
DB[17:10],
0 0 1 0 i80-system 16-bit interface
DB[8:1]
0 0 1 1 i80-system 8-bit interface DB[17:10]
IM[3:0] I 0 1 0 ID Serial Peripheral Interface (SPI) SDA, SDO
0 1 1 * Setting invalid
1 1 * * Setting invalid
When the serial peripheral interface is selected, IM0 pin is used for the device code
ID setting.
This signal will reset the device and must be applied to properly initialize the chip.
RESET I
Signal is active low.
EXTC I Dummy pin. Leave these pads open.
A chip select signal.
Low: the NV3029 is selected and accessible
CS I
High: the NV3029 is not selected and not accessible
Fix to the GND level when not in use.
A register select signal.
Low: select an index or status register
RS I
High: select a control register
Fix to either IOVCC or GND level when not in use.
A write strobe signal and enables an operation to write data when the signal is low.
WR I Fix to either IOVCC or GND level when not in use.
SPI Mode: Synchronizing clock signal in SPI mode.
A read strobe signal and enables an operation to read out data when the signal is low.
RD I
Fix to either IOVCC or GND level when not in use.
SPI interface input pin.
SDA I The data is latched on the rising edge of the SCL signal.
If not used, fix this pin at IOVCC or GND.

SPI interface output pin.

SDO O The data is outputted on the falling edge of the SCL signal.
Let SDO as floating when not used. If not used, open this pin
Tearing effect output pin to synchronize MPU to frame writing, activated by S/W
TE O command. When this pin is not activated, this pin is low.
If not used, open this pin
Pixel clock signal in RGB I/F mode.
DOTCLK I
Vertical sync. Signal in RGB I/F mode.
VSYNC I
Horizontal sync. Signal in RGB I/F mode.
HSYNC I
ENABLE I Data enable signal in RGB I/F mode. If not used, fix this pin at IOVCC or GND.
An 18-bit parallel bi-directional data bus for MPU system interface mode
8-bit I/F: DB[17:10] is used.
9-bit I/F: DB[17:9] is used.
16-bit I/F: DB[17:10] and DB[8:1] is used.
DB0- 18-bit I/F: DB[17:0] is used.
I/0
DB17 18-bit parallel bi-directional data bus for RGB interface operation
6-bit RGB I/F: DB[17:12] are used.
16-bit RGB I/F: DB[17:13] and DB[11:1] are used.
18-bit RGB I/F: DB[17:0] are used.
If not used, fix this pin at IOVCC or GND

Driver input/output pins
Signal I/O Function
S1 to S720 O Source driver output pads.
G1 to G320 O Gate driver output pads
Output voltage of 1st step up circuit. Input voltage to 2nd step up circuit.
DDVDH O Generated power output pad for source driver block. Connect this pad to the
capacitor for stabilization.
VGH O Power supply for the gate driver
VGL O Power supply for the gate driver

Power supply for generating VCOM low level. 3rd step up circuit output voltage.
VCL O
Connect a capacitor for stabilization.
C11P,C11N
- Connect the charge-pumping capacitor for generating DDVDH level.
C12P,C12N
C21P,C21N
- Connect the charge-pumping capacitor for generating VGH,VGL level.
C22P,C22N
C31P,C31N - Connect the charge-pumping capacitor for generating VCL level.
Output voltage generated from the reference voltage.
The voltage level is set with the VRH bits.
VREG1OUT is (1) a source driver grayscale reference voltage,
VREG1OUT
(2) high reference voltage,
(3) Vcom amplitude reference voltage.
VREG1OUT = 3.0 ~ (DDVDH – 0.5)V.
Low reference voltage for grayscale voltage generator.
VGS I
Connect an external resistor or to system ground.
Power supply pad for the TFT-display counter electrode.
VCOM O Charge recycling method is used with VCI and IOGND voltage.
Connect this pad to the TFT-display counter electrode.
VCOMH O Dummy pin. Leave these pads open.
VCOML O Dummy pin. Leave these pads open.

Output pin for PWM(Pulse width modulation)signal of LED driving.
BC O
If not used, open this pad.
Output pin for enabling LED driving.
BC_CTRL O
If not used, open this pad.

Pad Arrangement

Bump information
size
Item Pad No. Unit
X Y
Chip size - 15790 720
Input Side 85/72.5/60
Pad Pitch
Output Side 14
Input Side 40±2 56±2
Bumped Pad Top Size
Output Side 14±2 104±2 um
Height In Wafer 15±3
Bumped Pad Height Tolerance In Chip Under 2
Dimple Height Under 2
Chip Thickness - 300±10
Note:
1. scribe lane 80um included in this die size
2. wafer thickness can be varied with the customer’s needs.

Pad coordinates
NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y
1 S720 5075 126 56 S665 4305 261 111 S610 3535 126
2 S719 5061 261 57 S664 4291 126 112 S609 3521 261
3 S718 5047 126 58 S663 4277 261 113 S608 3507 126
4 S717 5033 261 59 S662 4263 126 114 S607 3493 261
5 S716 5019 126 60 S661 4249 261 115 S606 3479 126
6 S715 5005 261 61 S660 4235 126 116 S605 3465 261
7 S714 4991 126 62 S659 4221 261 117 S604 3451 126
8 S713 4977 261 63 S658 4207 126 118 S603 3437 261
9 S712 4963 126 64 S657 4193 261 119 S602 3423 126
10 S711 4949 261 65 S656 4179 126 120 S601 3409 261
11 S710 4935 126 66 S655 4165 261 121 S600 3395 126
12 S709 4921 261 67 S654 4151 126 122 S599 3381 261
13 S708 4907 126 68 S653 4137 261 123 S598 3367 126
14 S707 4893 261 69 S652 4123 126 124 S597 3353 261
15 S706 4879 126 70 S651 4109 261 125 S596 3339 126
16 S705 4865 261 71 S650 4095 126 126 S595 3325 261
17 S704 4851 126 72 S649 4081 261 127 S594 3311 126
18 S703 4837 261 73 S648 4067 126 128 S593 3297 261
19 S702 4823 126 74 S647 4053 261 129 S592 3283 126
20 S701 4809 261 75 S646 4039 126 130 S591 3269 261
21 S700 4795 126 76 S645 4025 261 131 S590 3255 126
22 S699 4781 261 77 S644 4011 126 132 S589 3241 261
23 S698 4767 126 78 S643 3997 261 133 S588 3227 126
24 S697 4753 261 79 S642 3983 126 134 S587 3213 261
25 S696 4739 126 80 S641 3969 261 135 S586 3199 126
26 S695 4725 261 81 S640 3955 126 136 S585 3185 261
27 S694 4711 126 82 S639 3941 261 137 S584 3171 126
28 S693 4697 261 83 S638 3927 126 138 S583 3157 261
29 S692 4683 126 84 S637 3913 261 139 S582 3143 126
30 S691 4669 261 85 S636 3899 126 140 S581 3129 261
31 S690 4655 126 86 S635 3885 261 141 S580 3115 126
32 S689 4641 261 87 S634 3871 126 142 S579 3101 261
33 S688 4627 126 88 S633 3857 261 143 S578 3087 126
34 S687 4613 261 89 S632 3843 126 144 S577 3073 261
35 S686 4599 126 90 S631 3829 261 145 S576 3059 126
36 S685 4585 261 91 S630 3815 126 146 S575 3045 261
37 S684 4571 126 92 S629 3801 261 147 S574 3031 126
38 S683 4557 261 93 S628 3787 126 148 S573 3017 261
39 S682 4543 126 94 S627 3773 261 149 S572 3003 126
40 S681 4529 261 95 S626 3759 126 150 S571 2989 261
41 S680 4515 126 96 S625 3745 261 151 S570 2975 126
42 S679 4501 261 97 S624 3731 126 152 S569 2961 261
43 S678 4487 126 98 S623 3717 261 153 S568 2947 126
44 S677 4473 261 99 S622 3703 126 154 S567 2933 261
45 S676 4459 126 100 S621 3689 261 155 S566 2919 126
46 S675 4445 261 101 S620 3675 126 156 S565 2905 261
47 S674 4431 126 102 S619 3661 261 157 S564 2891 126
48 S673 4417 261 103 S618 3647 126 158 S563 2877 261
49 S672 4403 126 104 S617 3633 261 159 S562 2863 126
50 S671 4389 261 105 S616 3619 126 160 S561 2849 261
51 S670 4375 126 106 S615 3605 261 161 S560 2835 126
52 S669 4361 261 107 S614 3591 126 162 S559 2821 261
53 S668 4347 126 108 S613 3577 261 163 S558 2807 126
54 S667 4333 261 109 S612 3563 126 164 S557 2793 261
55 S666 4319 126 110 S611 3549 261 165 S556 2779 126


166 S555 2765 261 221 S500 1995 126 276 S445 1225 261
167 S554 2751 126 222 S499 1981 261 277 S444 1211 126
168 S553 2737 261 223 S498 1967 126 278 S443 1197 261
169 S552 2723 126 224 S497 1953 261 279 S442 1183 126
170 S551 2709 261 225 S496 1939 126 280 S441 1169 261
171 S550 2695 126 226 S495 1925 261 281 S440 1155 126
172 S549 2681 261 227 S494 1911 126 282 S439 1141 261
173 S548 2667 126 228 S493 1897 261 283 S438 1127 126
174 S547 2653 261 229 S492 1883 126 284 S437 1113 261
175 S546 2639 126 230 S491 1869 261 285 S436 1099 126
176 S545 2625 261 231 S490 1855 126 286 S435 1085 261
177 S544 2611 126 232 S489 1841 261 287 S434 1071 126
178 S543 2597 261 233 S488 1827 126 288 S433 1057 261
179 S542 2583 126 234 S487 1813 261 289 S432 1043 126
180 S541 2569 261 235 S486 1799 126 290 S431 1029 261
181 S540 2555 126 236 S485 1785 261 291 S430 1015 126
182 S539 2541 261 237 S484 1771 126 292 S429 1001 261
183 S538 2527 126 238 S483 1757 261 293 S428 987 126
184 S537 2513 261 239 S482 1743 126 294 S427 973 261
185 S536 2499 126 240 S481 1729 261 295 S426 959 126
186 S535 2485 261 241 S480 1715 126 296 S425 945 261
187 S534 2471 126 242 S479 1701 261 297 S424 931 126
188 S533 2457 261 243 S478 1687 126 298 S423 917 261
189 S532 2443 126 244 S477 1673 261 299 S422 903 126
190 S531 2429 261 245 S476 1659 126 300 S421 889 261
191 S530 2415 126 246 S475 1645 261 301 S420 875 126
192 S529 2401 261 247 S474 1631 126 302 S419 861 261
193 S528 2387 126 248 S473 1617 261 303 S418 847 126
194 S527 2373 261 249 S472 1603 126 304 S417 833 261
195 S526 2359 126 250 S471 1589 261 305 S416 819 126
196 S525 2345 261 251 S470 1575 126 306 S415 805 261
197 S524 2331 126 252 S469 1561 261 307 S414 791 126
198 S523 2317 261 253 S468 1547 126 308 S413 777 261
199 S522 2303 126 254 S467 1533 261 309 S412 763 126
200 S521 2289 261 255 S466 1519 126 310 S411 749 261
201 S520 2275 126 256 S465 1505 261 311 S410 735 126
202 S519 2261 261 257 S464 1491 126 312 S409 721 261
203 S518 2247 126 258 S463 1477 261 313 S408 707 126
204 S517 2233 261 259 S462 1463 126 314 S407 693 261
205 S516 2219 126 260 S461 1449 261 315 S406 679 126
206 S515 2205 261 261 S460 1435 126 316 S405 665 261
207 S514 2191 126 262 S459 1421 261 317 S404 651 126
208 S513 2177 261 263 S458 1407 126 318 S403 637 261
209 S512 2163 126 264 S457 1393 261 319 S402 623 126
210 S511 2149 261 265 S456 1379 126 320 S401 609 261
211 S510 2135 126 266 S455 1365 261 321 S400 595 126
212 S509 2121 261 267 S454 1351 126 322 S399 581 261
213 S508 2107 126 268 S453 1337 261 323 S398 567 126
214 S507 2093 261 269 S452 1323 126 324 S397 553 261
215 S506 2079 126 270 S451 1309 261 325 S396 539 126
216 S505 2065 261 271 S450 1295 126 326 S395 525 261
217 S504 2051 126 272 S449 1281 261 327 S394 511 126
218 S503 2037 261 273 S448 1267 126 328 S393 497 261
219 S502 2023 126 274 S447 1253 261 329 S392 483 126
220 S501 2009 261 275 S446 1239 126 330 S391 469 261


331 S390 455 126 386 S335 -399 261 441 S280 -1169 126
332 S389 441 261 387 S334 -413 126 442 S279 -1183 261
333 S388 427 126 388 S333 -427 261 443 S278 -1197 126
334 S387 413 261 389 S332 -441 126 444 S277 -1211 261
335 S386 399 126 390 S331 -455 261 445 S276 -1225 126
336 S385 385 261 391 S330 -469 126 446 S275 -1239 261
337 S384 371 126 392 S329 -483 261 447 S274 -1253 126
338 S383 357 261 393 S328 -497 126 448 S273 -1267 261
339 S382 343 126 394 S327 -511 261 449 S272 -1281 126
340 S381 329 261 395 S326 -525 126 450 S271 -1295 261
341 S380 315 126 396 S325 -539 261 451 S270 -1309 126
342 S379 301 261 397 S324 -553 126 452 S269 -1323 261
343 S378 287 126 398 S323 -567 261 453 S268 -1337 126
344 S377 273 261 399 S322 -581 126 454 S267 -1351 261
345 S376 259 126 400 S321 -595 261 455 S266 -1365 126
346 S375 245 261 401 S320 -609 126 456 S265 -1379 261
347 S374 231 126 402 S319 -623 261 457 S264 -1393 126
348 S373 217 261 403 S318 -637 126 458 S263 -1407 261
349 S372 203 126 404 S317 -651 261 459 S262 -1421 126
350 S371 189 261 405 S316 -665 126 460 S261 -1435 261
351 S370 175 126 406 S315 -679 261 461 S260 -1449 126
352 S369 161 261 407 S314 -693 126 462 S259 -1463 261
353 S368 147 126 408 S313 -707 261 463 S258 -1477 126
354 S367 133 261 409 S312 -721 126 464 S257 -1491 261
355 S366 119 126 410 S311 -735 261 465 S256 -1505 126
356 S365 105 261 411 S310 -749 126 466 S255 -1519 261
357 S364 91 126 412 S309 -763 261 467 S254 -1533 126
358 S363 77 261 413 S308 -777 126 468 S253 -1547 261
359 S362 63 126 414 S307 -791 261 469 S252 -1561 126
360 S361 49 261 415 S306 -805 126 470 S251 -1575 261
361 S360 -49 126 416 S305 -819 261 471 S250 -1589 126
362 S359 -63 261 417 S304 -833 126 472 S249 -1603 261
363 S358 -77 126 418 S303 -847 261 473 S248 -1617 126
364 S357 -91 261 419 S302 -861 126 474 S247 -1631 261
365 S356 -105 126 420 S301 -875 261 475 S246 -1645 126
366 S355 -119 261 421 S300 -889 126 476 S245 -1659 261
367 S354 -133 126 422 S299 -903 261 477 S244 -1673 126
368 S353 -147 261 423 S298 -917 126 478 S243 -1687 261
369 S352 -161 126 424 S297 -931 261 479 S242 -1701 126
370 S351 -175 261 425 S296 -945 126 480 S241 -1715 261
371 S350 -189 126 426 S295 -959 261 481 S240 -1729 126
372 S349 -203 261 427 S294 -973 126 482 S239 -1743 261
373 S348 -217 126 428 S293 -987 261 483 S238 -1757 126
374 S347 -231 261 429 S292 -1001 126 484 S237 -1771 261
375 S346 -245 126 430 S291 -1015 261 485 S236 -1785 126
376 S345 -259 261 431 S290 -1029 126 486 S235 -1799 261
377 S344 -273 126 432 S289 -1043 261 487 S234 -1813 126
378 S343 -287 261 433 S288 -1057 126 488 S233 -1827 261
379 S342 -301 126 434 S287 -1071 261 489 S232 -1841 126
380 S341 -315 261 435 S286 -1085 126 490 S231 -1855 261
381 S340 -329 126 436 S285 -1099 261 491 S230 -1869 126
382 S339 -343 261 437 S284 -1113 126 492 S229 -1883 261
383 S338 -357 126 438 S283 -1127 261 493 S228 -1897 126
384 S337 -371 261 439 S282 -1141 126 494 S227 -1911 261
385 S336 -385 126 440 S281 -1155 261 495 S226 -1925 126


496 S225 -1939 261 551 S170 -2709 126 606 S115 -3479 261
497 S224 -1953 126 552 S169 -2723 261 607 S114 -3493 126
498 S223 -1967 261 553 S168 -2737 126 608 S113 -3507 261
499 S222 -1981 126 554 S167 -2751 261 609 S112 -3521 126
500 S221 -1995 261 555 S166 -2765 126 610 S111 -3535 261
501 S220 -2009 126 556 S165 -2779 261 611 S110 -3549 126
502 S219 -2023 261 557 S164 -2793 126 612 S109 -3563 261
503 S218 -2037 126 558 S163 -2807 261 613 S108 -3577 126
504 S217 -2051 261 559 S162 -2821 126 614 S107 -3591 261
505 S216 -2065 126 560 S161 -2835 261 615 S106 -3605 126
506 S215 -2079 261 561 S160 -2849 126 616 S105 -3619 261
507 S214 -2093 126 562 S159 -2863 261 617 S104 -3633 126
508 S213 -2107 261 563 S158 -2877 126 618 S103 -3647 261
509 S212 -2121 126 564 S157 -2891 261 619 S102 -3661 126
510 S211 -2135 261 565 S156 -2905 126 620 S101 -3675 261
511 S210 -2149 126 566 S155 -2919 261 621 S100 -3689 126
512 S209 -2163 261 567 S154 -2933 126 622 S99 -3703 261
513 S208 -2177 126 568 S153 -2947 261 623 S98 -3717 126
514 S207 -2191 261 569 S152 -2961 126 624 S97 -3731 261
515 S206 -2205 126 570 S151 -2975 261 625 S96 -3745 126
516 S205 -2219 261 571 S150 -2989 126 626 S95 -3759 261
517 S204 -2233 126 572 S149 -3003 261 627 S94 -3773 126
518 S203 -2247 261 573 S148 -3017 126 628 S93 -3787 261
519 S202 -2261 126 574 S147 -3031 261 629 S92 -3801 126
520 S201 -2275 261 575 S146 -3045 126 630 S91 -3815 261
521 S200 -2289 126 576 S145 -3059 261 631 S90 -3829 126
522 S199 -2303 261 577 S144 -3073 126 632 S89 -3843 261
523 S198 -2317 126 578 S143 -3087 261 633 S88 -3857 126
524 S197 -2331 261 579 S142 -3101 126 634 S87 -3871 261
525 S196 -2345 126 580 S141 -3115 261 635 S86 -3885 126
526 S195 -2359 261 581 S140 -3129 126 636 S85 -3899 261
527 S194 -2373 126 582 S139 -3143 261 637 S84 -3913 126
528 S193 -2387 261 583 S138 -3157 126 638 S83 -3927 261
529 S192 -2401 126 584 S137 -3171 261 639 S82 -3941 126
530 S191 -2415 261 585 S136 -3185 126 640 S81 -3955 261
531 S190 -2429 126 586 S135 -3199 261 641 S80 -3969 126
532 S189 -2443 261 587 S134 -3213 126 642 S79 -3983 261
533 S188 -2457 126 588 S133 -3227 261 643 S78 -3997 126
534 S187 -2471 261 589 S132 -3241 126 644 S77 -4011 261
535 S186 -2485 126 590 S131 -3255 261 645 S76 -4025 126
536 S185 -2499 261 591 S130 -3269 126 646 S75 -4039 261
537 S184 -2513 126 592 S129 -3283 261 647 S74 -4053 126
538 S183 -2527 261 593 S128 -3297 126 648 S73 -4067 261
539 S182 -2541 126 594 S127 -3311 261 649 S72 -4081 126
540 S181 -2555 261 595 S126 -3325 126 650 S71 -4095 261
541 S180 -2569 126 596 S125 -3339 261 651 S70 -4109 126
542 S179 -2583 261 597 S124 -3353 126 652 S69 -4123 261
543 S178 -2597 126 598 S123 -3367 261 653 S68 -4137 126
544 S177 -2611 261 599 S122 -3381 126 654 S67 -4151 261
545 S176 -2625 126 600 S121 -3395 261 655 S66 -4165 126
546 S175 -2639 261 601 S120 -3409 126 656 S65 -4179 261
547 S174 -2653 126 602 S119 -3423 261 657 S64 -4193 126
548 S173 -2667 261 603 S118 -3437 126 658 S63 -4207 261
549 S172 -2681 126 604 S117 -3451 261 659 S62 -4221 126
550 S171 -2695 261 605 S116 -3465 126 660 S61 -4235 261


661 S60 -4249 126 716 S5 -5019 261 771 C12N -4352.5 -281.25
662 S59 -4263 261 717 S4 -5033 126 772 C12N -4292.5 -281.25
663 S58 -4277 126 718 S3 -5047 261 773 C12N -4232.5 -281.25
664 S57 -4291 261 719 S2 -5061 126 774 C11P -4172.5 -281.25
665 S56 -4305 126 720 S1 -5075 261 775 C11P -4112.5 -281.25
666 S55 -4319 261 721 DUMMY30 -7399 126 776 C11P -4052.5 -281.25
667 S54 -4333 126 722 DUMMY1 -7292.5 -281.3 777 C11P -3992.5 -281.25
668 S53 -4347 261 723 DUMMY2 -7232.5 -281.3 778 C11P -3932.5 -281.25
669 S52 -4361 126 724 VCOM -7172.5 -281.3 779 C11P -3872.5 -281.25
670 S51 -4375 261 725 VCOM -7112.5 -281.3 780 C11P -3812.5 -281.25
671 S50 -4389 126 726 VCOM -7052.5 -281.3 781 C11N -3752.5 -281.25
672 S49 -4403 261 727 VCOM -6992.5 -281.3 782 C11N -3692.5 -281.25
673 S48 -4417 126 728 VCOM -6932.5 -281.3 783 C11N -3632.5 -281.25
674 S47 -4431 261 729 VCOM -6872.5 -281.3 784 C11N -3572.5 -281.25
675 S46 -4445 126 730 VCOM -6812.5 -281.3 785 C11N -3512.5 -281.25
676 S45 -4459 261 731 VCOM -6752.5 -281.3 786 C11N -3452.5 -281.25
677 S44 -4473 126 732 DUMMY3 -6692.5 -281.3 787 C11N -3392.5 -281.25
678 S43 -4487 261 733 C22P -6632.5 -281.3 788 VCI1 -3332.5 -281.25
679 S42 -4501 126 734 C22P -6572.5 -281.3 789 VCI1 -3272.5 -281.25
680 S41 -4515 261 735 C22N -6512.5 -281.3 790 VCI1 -3212.5 -281.25
681 S40 -4529 126 736 C22N -6452.5 -281.3 791 VCI1 -3152.5 -281.25
682 S39 -4543 261 737 C21P -6392.5 -281.3 792 VCI1 -3092.5 -281.25
683 S38 -4557 126 738 C21P -6332.5 -281.3 793 VCI1 -3032.5 -281.25
684 S37 -4571 261 739 C21N -6272.5 -281.3 794 VCI1 -2972.5 -281.25
685 S36 -4585 126 740 C21N -6212.5 -281.3 795 VCI -2912.5 -281.25
686 S35 -4599 261 741 VGH -6152.5 -281.3 796 VCI -2852.5 -281.25
687 S34 -4613 126 742 VGH -6092.5 -281.3 797 VCI -2792.5 -281.25
688 S33 -4627 261 743 VGH -6032.5 -281.3 798 VCI -2732.5 -281.25
689 S32 -4641 126 744 VGH -5972.5 -281.3 799 VCI -2672.5 -281.25
690 S31 -4655 261 745 VGH -5912.5 -281.3 800 VCI -2612.5 -281.25
691 S30 -4669 126 746 DUMMY4 -5852.5 -281.3 801 VCI -2552.5 -281.25
692 S29 -4683 261 747 VGL -5792.5 -281.3 802 VCI -2492.5 -281.25
693 S28 -4697 126 748 VGL -5732.5 -281.3 803 GNDR -2432.5 -281.25
694 S27 -4711 261 749 VGL -5672.5 -281.3 804 GNDR -2372.5 -281.25
695 S26 -4725 126 750 VGL -5612.5 -281.3 805 GNDR -2312.5 -281.25
696 S25 -4739 261 751 VGL -5552.5 -281.3 806 GNDR -2252.5 -281.25
697 S24 -4753 126 752 VGL -5492.5 -281.3 807 GNDR -2192.5 -281.25
698 S23 -4767 261 753 DDVDH -5432.5 -281.3 808 GNDR -2132.5 -281.25
699 S22 -4781 126 754 DDVDH -5372.5 -281.3 809 GNDR -2072.5 -281.25
700 S21 -4795 261 755 DDVDH -5312.5 -281.3 810 GNDR -2012.5 -281.25
701 S20 -4809 126 756 DDVDH -5252.5 -281.3 811 GND -1952.5 -281.25
702 S19 -4823 261 757 DDVDH -5192.5 -281.3 812 GND -1892.5 -281.25
703 S18 -4837 126 758 DDVDH -5132.5 -281.3 813 GND -1832.5 -281.25
704 S17 -4851 261 759 DDVDH -5072.5 -281.3 814 GND -1772.5 -281.25
705 S16 -4865 126 760 C12P -5012.5 -281.3 815 GND -1712.5 -281.25
706 S15 -4879 261 761 C12P -4952.5 -281.3 816 GND -1652.5 -281.25
707 S14 -4893 126 762 C12P -4892.5 -281.3 817 GND -1592.5 -281.25
708 S13 -4907 261 763 C12P -4832.5 -281.3 818 GND -1532.5 -281.25
709 S12 -4921 126 764 C12P -4772.5 -281.3 819 GNDA -1472.5 -281.25
710 S11 -4935 261 765 C12P -4712.5 -281.3 820 GNDA -1412.5 -281.25
711 S10 -4949 126 766 C12P -4652.5 -281.3 821 GNDA -1352.5 -281.25
712 S9 -4963 261 767 C12N -4592.5 -281.3 822 GNDA -1292.5 -281.25
713 S8 -4977 126 768 C12N -4532.5 -281.3 823 GNDA -1232.5 -281.25
714 S7 -4991 261 769 C12N -4472.5 -281.3 824 GNDA -1172.5 -281.25
715 S6 -5005 126 770 C12N -4412.5 -281.3 825 GNDA -1112.5 -281.25


826 GNDA -1052.5 -281.25 881 DB23 2960 -281.3 936 DUMMYR2 6272.5 -281.25
827 TREGB -992.5 -281.25 882 TMODE3 3032.5 -281.3 937 DUMMY16 6332.5 -281.25
828 VGS -932.5 -281.25 883 IOVCC 3092.5 -281.3 938 DUMMY17 6392.5 -281.25
829 VGS -872.5 -281.25 884 IOVCC 3152.5 -281.3 939 DUMMY18 6452.5 -281.25
830 EXTC -812.5 -281.25 885 IOVCC 3212.5 -281.3 940 DUMMY19 6512.5 -281.25
831 IM3 -752.5 -281.25 886 IOVCC 3272.5 -281.3 941 DUMMY20 6572.5 -281.25
832 IM2 -692.5 -281.25 887 IOVCC 3332.5 -281.3 942 DUMMY21 6632.5 -281.25
833 IM1 -632.5 -281.25 888 IOVCC 3392.5 -281.3 943 DUMMY22 6692.5 -281.25
834 IM0 -572.5 -281.25 889 IOVCC 3452.5 -281.3 944 VCOM 6752.5 -281.25
835 RESET -512.5 -281.25 890 VDD 3512.5 -281.3 945 VCOM 6812.5 -281.25
836 CS -452.5 -281.25 891 VDD 3572.5 -281.3 946 VCOM 6872.5 -281.25
837 RS -392.5 -281.25 892 VDD 3632.5 -281.3 947 VCOM 6932.5 -281.25
838 WR -332.5 -281.25 893 VDD 3692.5 -281.3 948 VCOM 6992.5 -281.25
839 RD -272.5 -281.25 894 VDD 3752.5 -281.3 949 VCOM 7052.5 -281.25
840 TMODE2 -212.5 -281.25 895 VDD 3812.5 -281.3 950 VCOM 7112.5 -281.25
841 VSYNC -152.5 -281.25 896 VDD 3872.5 -281.3 951 VCOM 7172.5 -281.25
842 HSYNC -92.5 -281.25 897 VDD 3932.5 -281.3 952 VCOMH 7232.5 -281.25
843 ENABLE -32.5 -281.25 898 VDDR 3992.5 -281.3 953 VCOML 7292.5 -281.25
844 DOTCLOCK 27.5 -281.25 899 VDDR 4052.5 -281.3 954 DUMMY25 7399 261
845 TMODE1 87.5 -281.25 900 VDDR 4112.5 -281.3 955 DUMMY26 7385 126
846 SDA 160 -281.25 901 VDDR 4172.5 -281.3 956 DUMMY27 7371 261
847 DB0 245 -281.25 902 VDDR 4232.5 -281.3 957 G2 7357 126
848 DB1 330 -281.25 903 VDDR 4292.5 -281.3 958 G4 7343 261
849 DB2 415 -281.25 904 DUMMY14 4352.5 -281.3 959 G6 7329 126
850 DB3 500 -281.25 905 VREG1OUT 4412.5 -281.3 960 G8 7315 261
851 TMODE0 572.5 -281.25 906 VREG1OUT 4472.5 -281.3 961 G10 7301 126
852 DB4 645 -281.25 907 VREG1OUT 4532.5 -281.3 962 G12 7287 261
853 DB5 730 -281.25 908 VREG1OUT 4592.5 -281.3 963 G14 7273 126
854 DB6 815 -281.25 909 VCIR_EXIN 4652.5 -281.3 964 G16 7259 261
855 DB7 900 -281.25 910 DUMMY15 4712.5 -281.3 965 G18 7245 126
856 TMUX2 972.5 -281.25 911 VCL 4772.5 -281.3 966 G20 7231 261
857 DB8 1045 -281.25 912 VCL 4832.5 -281.3 967 G22 7217 126
858 DB9 1130 -281.25 913 VCL 4892.5 -281.3 968 G24 7203 261
859 DB10 1215 -281.25 914 VCL 4952.5 -281.3 969 G26 7189 126
860 DB11 1300 -281.25 915 VCL 5012.5 -281.3 970 G28 7175 261
861 TMUX1 1372.5 -281.25 916 VCL 5072.5 -281.3 971 G30 7161 126
862 DB12 1445 -281.25 917 VCL 5132.5 -281.3 972 G32 7147 261
863 DB13 1530 -281.25 918 VCL 5192.5 -281.3 973 G34 7133 126
864 DB14 1615 -281.25 919 C31P 5252.5 -281.3 974 G36 7119 261
865 DB15 1700 -281.25 920 C31P 5312.5 -281.3 975 G38 7105 126
866 TMUX0 1772.5 -281.25 921 C31P 5372.5 -281.3 976 G40 7091 261
867 DB16 1845 -281.25 922 C31P 5432.5 -281.3 977 G42 7077 126
868 DB17 1930 -281.25 923 C31P 5492.5 -281.3 978 G44 7063 261
869 EXCLK 2002.5 -281.25 924 C31P 5552.5 -281.3 979 G46 7049 126
870 TE 2075 -281.25 925 C31P 5612.5 -281.3 980 G48 7035 261
871 SDO 2160 -281.25 926 C31P 5672.5 -281.3 981 G50 7021 126
872 BC 2245 -281.25 927 C31N 5732.5 -281.3 982 G52 7007 261
873 BC_CTRL 2330 -281.25 928 C31N 5792.5 -281.3 983 G54 6993 126
874 VDD3_P 2402.5 -281.25 929 C31N 5852.5 -281.3 984 G56 6979 261
875 VDD3_P 2462.5 -281.25 930 C31N 5912.5 -281.3 985 G58 6965 126
876 DB18 2535 -281.25 931 C31N 5972.5 -281.3 986 G60 6951 261
877 DB19 2620 -281.25 932 C31N 6032.5 -281.3 987 G62 6937 126
878 DB20 2705 -281.25 933 C31N 6092.5 -281.3 988 G64 6923 261
879 DB21 2790 -281.25 934 C31N 6152.5 -281.3 989 G66 6909 126
880 DB22 2875 -281.25 935 DUMMYR1 6212.5 -281.3 990 G68 6895 261


991 G70 6881 126 1046 G180 6111 261 1101 G290 5341 126
992 G72 6867 261 1047 G182 6097 126 1102 G292 5327 261
993 G74 6853 126 1048 G184 6083 261 1103 G294 5313 126
994 G76 6839 261 1049 G186 6069 126 1104 G296 5299 261
995 G78 6825 126 1050 G188 6055 261 1105 G298 5285 126
996 G80 6811 261 1051 G190 6041 126 1106 G300 5271 261
997 G82 6797 126 1052 G192 6027 261 1107 G302 5257 126
998 G84 6783 261 1053 G194 6013 126 1108 G304 5243 261
999 G86 6769 126 1054 G196 5999 261 1109 G306 5229 126
1000 G88 6755 261 1055 G198 5985 126 1110 G308 5215 261
1001 G90 6741 126 1056 G200 5971 261 1111 G310 5201 126
1002 G92 6727 261 1057 G202 5957 126 1112 G312 5187 261
1003 G94 6713 126 1058 G204 5943 261 1113 G314 5173 126
1004 G96 6699 261 1059 G206 5929 126 1114 G316 5159 261
1005 G98 6685 126 1060 G208 5915 261 1115 G318 5145 126
1006 G100 6671 261 1061 G210 5901 126 1116 G320 5131 261
1007 G102 6657 126 1062 G212 5887 261 1117 G319 -5131 126
1008 G104 6643 261 1063 G214 5873 126 1118 G317 -5145 261
1009 G106 6629 126 1064 G216 5859 261 1119 G315 -5159 126
1010 G108 6615 261 1065 G218 5845 126 1120 G313 -5173 261
1011 G110 6601 126 1066 G220 5831 261 1121 G311 -5187 126
1012 G112 6587 261 1067 G222 5817 126 1122 G309 -5201 261
1013 G114 6573 126 1068 G224 5803 261 1123 G307 -5215 126
1014 G116 6559 261 1069 G226 5789 126 1124 G305 -5229 261
1015 G118 6545 126 1070 G228 5775 261 1125 G303 -5243 126
1016 G120 6531 261 1071 G230 5761 126 1126 G301 -5257 261
1017 G122 6517 126 1072 G232 5747 261 1127 G299 -5271 126
1018 G124 6503 261 1073 G234 5733 126 1128 G297 -5285 261
1019 G126 6489 126 1074 G236 5719 261 1129 G295 -5299 126
1020 G128 6475 261 1075 G238 5705 126 1130 G293 -5313 261
1021 G130 6461 126 1076 G240 5691 261 1131 G291 -5327 126
1022 G132 6447 261 1077 G242 5677 126 1132 G289 -5341 261
1023 G134 6433 126 1078 G244 5663 261 1133 G287 -5355 126
1024 G136 6419 261 1079 G246 5649 126 1134 G285 -5369 261
1025 G138 6405 126 1080 G248 5635 261 1135 G283 -5383 126
1026 G140 6391 261 1081 G250 5621 126 1136 G281 -5397 261
1027 G142 6377 126 1082 G252 5607 261 1137 G279 -5411 126
1028 G144 6363 261 1083 G254 5593 126 1138 G277 -5425 261
1029 G146 6349 126 1084 G256 5579 261 1139 G275 -5439 126
1030 G148 6335 261 1085 G258 5565 126 1140 G273 -5453 261
1031 G150 6321 126 1086 G260 5551 261 1141 G271 -5467 126
1032 G152 6307 261 1087 G262 5537 126 1142 G269 -5481 261
1033 G154 6293 126 1088 G264 5523 261 1143 G267 -5495 126
1034 G156 6279 261 1089 G266 5509 126 1144 G265 -5509 261
1035 G158 6265 126 1090 G268 5495 261 1145 G263 -5523 126
1036 G160 6251 261 1091 G270 5481 126 1146 G261 -5537 261
1037 G162 6237 126 1092 G272 5467 261 1147 G259 -5551 126
1038 G164 6223 261 1093 G274 5453 126 1148 G257 -5565 261
1039 G166 6209 126 1094 G276 5439 261 1149 G255 -5579 126
1040 G168 6195 261 1095 G278 5425 126 1150 G253 -5593 261
1041 G170 6181 126 1096 G280 5411 261 1151 G251 -5607 126
1042 G172 6167 261 1097 G282 5397 126 1152 G249 -5621 261
1043 G174 6153 126 1098 G284 5383 261 1153 G247 -5635 126
1044 G176 6139 261 1099 G286 5369 126 1154 G245 -5649 261
1045 G178 6125 126 1100 G288 5355 261 1155 G243 -5663 126


1156 G241 -5677 261 1200 G153 -6293 261 1244 G65 -6909 261
1157 G239 -5691 126 1201 G151 -6307 126 1245 G63 -6923 126
1158 G237 -5705 261 1202 G149 -6321 261 1246 G61 -6937 261
1159 G235 -5719 126 1203 G147 -6335 126 1247 G59 -6951 126
1160 G233 -5733 261 1204 G145 -6349 261 1248 G57 -6965 261
1161 G231 -5747 126 1205 G143 -6363 126 1249 G55 -6979 126
1162 G229 -5761 261 1206 G141 -6377 261 1250 G53 -6993 261
1163 G227 -5775 126 1207 G139 -6391 126 1251 G51 -7007 126
1164 G225 -5789 261 1208 G137 -6405 261 1252 G49 -7021 261
1165 G223 -5803 126 1209 G135 -6419 126 1253 G47 -7035 126
1166 G221 -5817 261 1210 G133 -6433 261 1254 G45 -7049 261
1167 G219 -5831 126 1211 G131 -6447 126 1255 G43 -7063 126
1168 G217 -5845 261 1212 G129 -6461 261 1256 G41 -7077 261
1169 G215 -5859 126 1213 G127 -6475 126 1257 G39 -7091 126
1170 G213 -5873 261 1214 G125 -6489 261 1258 G37 -7105 261
1171 G211 -5887 126 1215 G123 -6503 126 1259 G35 -7119 126
1172 G209 -5901 261 1216 G121 -6517 261 1260 G33 -7133 261
1173 G207 -5915 126 1217 G119 -6531 126 1261 G31 -7147 126
1174 G205 -5929 261 1218 G117 -6545 261 1262 G29 -7161 261
1175 G203 -5943 126 1219 G115 -6559 126 1263 G27 -7175 126
1176 G201 -5957 261 1220 G113 -6573 261 1264 G25 -7189 261
1177 G199 -5971 126 1221 G111 -6587 126 1265 G23 -7203 126
1178 G197 -5985 261 1222 G109 -6601 261 1266 G21 -7217 261
1179 G195 -5999 126 1223 G107 -6615 126 1267 G19 -7231 126
1180 G193 -6013 261 1224 G105 -6629 261 1268 G17 -7245 261
1181 G191 -6027 126 1225 G103 -6643 126 1269 G15 -7259 126
1182 G189 -6041 261 1226 G101 -6657 261 1270 G13 -7273 261
1183 G187 -6055 126 1227 G99 -6671 126 1271 G11 -7287 126
1184 G185 -6069 261 1228 G97 -6685 261 1272 G9 -7301 261
1185 G183 -6083 126 1229 G95 -6699 126 1273 G7 -7315 126
1186 G181 -6097 261 1230 G93 -6713 261 1274 G5 -7329 261
1187 G179 -6111 126 1231 G91 -6727 126 1275 G3 -7343 126
1188 G177 -6125 261 1232 G89 -6741 261 1276 G1 -7357 261
1189 G175 -6139 126 1233 G87 -6755 126 1277 DUMMY28 -7371 126
1190 G173 -6153 261 1234 G85 -6769 261 1278 DUMMY29 -7385 261
1191 G171 -6167 126 1235 G83 -6783 126
1192 G169 -6181 261 1236 G81 -6797 261
1193 G167 -6195 126 1237 G79 -6811 126
1194 G165 -6209 261 1238 G77 -6825 261
1195 G163 -6223 126 1239 G75 -6839 126
1196 G161 -6237 261 1240 G73 -6853 261
1197 G159 -6251 126 1241 G71 -6867 126
1198 G157 -6265 261 1242 G69 -6881 261
1199 G155 -6279 126 1243 G67 -6895 126

Bump Size

Align Key
Alignment mark
Alignment mark X Y
L_AMK -7480 260
R_AMK 7480 260

Block Function
1. System Interface
The NV3029 supports the following system interfaces: 80-system high-speed interface via 8-, 9-, 16-, 18-
bit parallel ports and clock synchronous serial interface. The interface is selected by setting the IM3-0
pins.
The NV3029 has 16-bit index register (IR), 18-bit write-data register (WDR), and 18-bit read-data register
(RDR). The IR is the register to store index information from control register and the internal GRAM.
The WDR is the register to temporarily store the data to be written to the internal GRAM. The RDR is the
register to temporarily store the data read from the GRAM. The data from the MPU to be written to the
internal GRAM is first written to the WDR and then automatically written to the internal GRAM in
internal operation. The data is read via the RDR from the internal GRAM. Therefore, invalid data is sent
to the data bus when the first read operation from the internal GRAM is performed. Valid data is read out
when the second and subsequent read operations are performed.
The instruction execution time except starting oscillation takes 0 clock cycle and instructions can be
written consecutively.
2. External Display Interface (RGB, VSYNC interfaces)
The NV3029 supports RGB interface and VSYNC interface as the moving picture display interface
(external display interface). When RGB interface is selected, the display operation is synchronized with
externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface operation, data (DB17-0)
is written in synchronization with these signals according to the polarity of the enable signal (ENABLE) to
prevent flicker on display while rewriting display data.
In VSYNC interface operation, the display operation is synchronized with the internal clock and VSYNC
signal, which is used for frame synchronization. The display data is written to the internal GRAM via
system interface but there are restrictions in setting the speed and the method to write data to the internal
RAM. For details, see the “External Display Interface” section.
The NV3029 allows switching between the external display interface and the system interface by
instruction so that the optimal interface is selected for the kind of picture on the panel (still and/or moving
picture). The NV3029 writes the display data to the internal GRAM to enable transferring data only when
the frame data is updated, which contributes to the reduction of data to be transferred from the system and
saving power required for the moving picture display.
3. Address Counter (AC)
The address counter (AC) gives an address to the internal GRAM. When the address setting instruction is
written in the IR, the address information is sent from the IR to the AC. When the data is written to the
internal GRAM, the AC is automatically incremented (plus one) or decremented (minus one). The
window address function enables writing data only within the rectangular area specified in GRAM by
setting.
4. Graphics RAM (GRAM)
GRAM is graphics RAM, which can store a maximum 172800-byte (240RGB x 320 (dots) x 18(bits)/8)
bit pattern data using 18 bits per pixel.

5. Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates liquid crystal drive voltage according to the grayscale
data in the gamma-correction registers to enable a maximum 262k-color display.
6. Timing Generator
The timing generator generates timing signals to operate internal circuits such as GRAM. The NV3029
generates timing signals for display operation such as the RAM read operation and for internal operation
such as RAM access from MPU and outputs them separately to avoid mutual interference. Also FMARK
is generated internally and output from the timing generator.
7. Oscillator (OSC)
The NV3029 generates the RC oscillation clock signal by internal oscillator. Adjust the oscillation
frequency according to operating voltage and frame frequency.
8. Liquid crystal driver Circuit
The liquid crystal driver circuit of the NV3029 consists of 720-channel source driver (S1 ~ S720) and 320-
channel gate driver (G1 ~ G320). The display pattern data is latched when 720 bits of data are input. The
latched data control the source driver and generates liquid crystal drive waveform. The shift direction of
720-bit source output from the source driver is determined by instruction (SS bit). The shift direction of
gate output from the gate driver can be changed by setting the GS bit. The gate pin assignment can be
changed by setting the SM bit. Sets SM and GS bits to select the optimal scan mode for the module.
9. Internal logic power supply regulator
The internal logic power supply regulator generates internal logic power supply VDD.
10. Liquid crystal drive power supply circuit
The liquid crystal drive power supply circuit generates the voltage levels to drive liquid crystal,
VREG1OUT,DDVDH,VGH,VGL,VCL,and Vcom.

Instruction

No. Register name RW RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA

R84h Partial Image 2 start W/R 1 0 0 0 0 0 0 0
18 17 16 15 14 13 12 11 10
PTEA PTEA PTEA PTEA PTEA PTEA PTEA PTEA PTEA
R85h Partial Image 2 End W/R 1 0 0 0 0 0 0 0
18 17 16 15 14 13 12 11 10
R90h Panel IF Control 1 W/R 1 0 0 0 0 0 0 DIVI1 DIVI0 0 0 0 RTNI4RTNI3RTNI2RTNI1RTNI0
VCSI VCSI VCSI VCSI

R91h Panel IF Control 2 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0
E V[2] V[1] V[0]
NOWI NOWI NOWI
R92h Panel IF Control 3 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0 0
2 1 0
MCPI MCPI MCPI
[2] [1] [0]
RTNE RTNE RTNE RTNE RTNE RTNE
R95h Panel IF Control 5 W/R 1 0 0 0 0 0 0 DIVE1DIVE0 0 0
5 4 3 2 1 0
VCSE VCSE VCSE VCSE
E V[2] V[1] V[0]
NOW NOW NOW NOW
E[3] E[2] E[1] E[0]
MCPE MCPE MCPE
[2] [1] [0]
VDV0 VDV0 VDV0 VDV0 VDV0 VCM0 VCM0 VCM0 VCM0 VCM0 VCM0
R14h Power control 4 W/R 1 0 0 0 0 0
[4] [3] [2] [1] [0] [5] [4] [3] [2[ [1] [0]
DC1 DC1 DC1 DC0 DC0 DC0
R1Ah Power Control 10 W/R 1 1 0 0 0 0 0 0 0 0 0
[2] [1] [0] [2] [1] [0]
SAP SAP VRH VRH VRH VRH VRH
R1Bh Power Control 11 W/R 1 0 0 0 0 VC[1] VC[0] 0 0 0
[1] [0] [4] [3] [2] [1] [0]
N20v_ N20v_ N20v_ P20v_ P20v_ P20v_ N30v_ N3v_e P5v_c P5v_e
R1Ch Power Control 12 W/R 1 0 0 0 0 0
md[1] md[0] en md[1] md[0] en mode n mp_en n
Gamm En_vr
R1Dh Power Control 13 W/R 1 0 0 0 0 0 0 0 0 EN3 EN2 EN1 0 0 0
a_en eg1
R1Eh Internal use1 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
R1Fh Internal use2 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
R65h Internal use3 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Power Pdin Pdin Pdin Pdin Pdin Pdin Pdin Pdin

R66h OTP Control RW RS por Pprog Pwe Ptm[1]Ptm[0] Pa[1] Pa[0]
_sel [7] [6] [5] [4] [3] [2] [1] [0]
PKP PKP PKP PKP PKP PKP
R40h Gamma Control 11 W 1 0 0 0 0 0 0 0 0 0 0
11[2] 11[1] 11[0] 10[2] 10[1] 10[0]
13[2] 13[1] 13[0] 12[2] 12[1] 12[0]
15[2] 15[1] 15[0] 14[2] 14[1] 14[0]
PRP11 PRP11 PRP11 PRP10 PRP10 PRP10
[2] [1] [0] [2] [1] [0]
VRP1 VRP1 VRP1 VRP1 VRP1 VRP1 VRP1 VRP1 VRP1 VRP1
R46h Gamma Control 15 W 1 0 0 0 0 0 0
1[4] 1[3] 1[2] 1[1] 1[0] 0[4] 0[3] 0[2] 0[1] 0[0]
PKN PKN PKN PKN PKN PKN
11[2] 11[1] 11[0] 10[2] 10[1] 10[0]
13[2] 13[1] 13[0] 12[2] 12[1] 12[0]
PKN PKN PKN PKN1 PKN1 PKN
15[2] 15[1] 15[0] 4[2] 4[1] 14[0]
PRN PRN PRN PKP0 PKP0 PKP0
R4Ch Gamma Control 19 W/R 1 0 0 0 0 0 0 0 0 0 0
11[2] 11[1] 11[0] [2] [1] [0]
VRN1 VRN1 VRN1 VRN1 VRN1 VRN1 VRN1 VRN1 VRN1 VRN1
R4Dh Gamma Control 20 W/R 1 0 0 0 0 0 0
1[4] 1[3] 1[2] 1[1] 1[0] 0[4] 0[3] 0[2] 0[1] 0[0]
R70h Gamma Control 21 W/R 1 0 0 0 0 0 0 0 0 0 0
21[2] 21[1] 21[0] 20[2] 20[1] 20[0]
23[2] 23[1] 23[0] 22[2] 22[1] 22[0]
25[2] 25[1] 25[0] 24[2] 24[1] 24[0]
PRP PRP PRP PRP PRP PRP
21[2] 21[1] 21[0] 20[2] 20[1] 20[0]
VRP2 VRP2 VRP2 VRP2 VRP2 VRP2 VRP2 VRP2 VRP2 VRP2
R76h Gamma Control 25 RW RS 0 0 0 0 0 0
1[4] 1[3] 1[2] 1[1] 1[0] 0[4] 0[3] 0[2] 0[1] 0[0]
21[2] 21[1] 21[0] 20[2] 20[1] 20[0]
23[2] 23[1] 23[0] 22[2] 22[1] 22[0]


Index (IR)
The index register specifies the address of register(R00~RFFh) or RAM which will be accessed.
Driver Code Read(R00h)
Driver Output Control (R01h)
SS: Sets the shift direction of source driver output.

SS = 0: Output from S1 to S720
SS = 1: Output from S720 to S1
When changing the order of RGB dots to the source driver, set the BGR and SS bits as follows.
When SS = 0 and BGR = 0, RGB dots are assigned in the order of R, G, and B.
When SS = 1 and BGR = 1, RGB dots are assigned in the order of B, G, and R.
When changing the SS and BGR bits, the RAM data must be rewritten.
SM[2:0]: scan mode selection
LCD AC Driving Control (R02h)
EOR: EOR = 1 and B/C=1 to set the line inversion.

B/C: Selects the liquid crystal drive waveform.
B/C = 0: selects frame/field inversion.
B/C = 1: selects n-line inversion.
NW[5:0]: Specifies “n”, the number of gate lines from 1 to 64, to set the interval of inverting polarity. The
polarity is inverted at an interval of n+1 gate lines.
GS = 0 GS = 1
SM = 0 G17,18…255,256 G304,303…66,65
SM = 1 G18,17….256,255 G303,304…65,66
SM = 2 G33,35…317,319,2,4…190,192 G288,286…4,2,319,317…131,129
SM = 3 G35,33…319,317,4,2…192,190 G286,288…2,4,317,319…129,131
SM = 4 G17,18…255,256 G304,303…66,65
SM = 5 G18,17….256,255 G303,304…65,66
SM = 6 G33,35…269,271,34,36…270,272 G288,286…52,50,287,285…51,49
SM = 7 G35,33…271,269,36,34…272,270 G286,288…50,52,285,287…49,51

Entry Mode (R03h)
AM: decides the updating direction when writing data to the internal GRAM.
AM = “0”, sets the horizontal direction.
AM = “1”, sets the vertical direction.
When setting a window area by registers R50h ~R53h, the data is updated only in this area based on
I/D[1:0] and AM bits setting.
BGR: The order of RGB is reversed to BGR when writing 18-bit pixel data to the internal GRAM when
BGR = “1”.
DFM: In combination with the TRI setting, sets the format to develop 16-/8-bit data to 18-bit data when
using either 16-bit or 8-bit bus interface. Make sure to set DFM = 0 when not transferring data via 16-bit
or 8-bit interface.
TRI: Selects the format to transfer data bits via 16-bit or 8-bit interface.
In 8-bit interface operation,

TRI = 0: 16-bit RAM data is transferred in two transfers.
TRI = 1: 18-bit RAM data is transferred in three transfers.
In 16-bit bus interface operation.
TRI = 0: 16-bit RAM data is transferred in one transfer.
TRI = 1: 18-bit RAM data is transferred in two transfers.
Make sure TRI = 0 when not transferring data via 16-bit or 8-bit interface. Also, set TRI = 0 during read
operation.
I/D[1:0]: The address counter (AC) will increment by 1 after data written to GRAM if I/D = 1; the AC
will decrement by 1 after data written to GRAM if I/D=0.
Automatic address update (AM, ID)
Display Control 1 (R07h)

D[1:0] Set D[1:0]=”11” to turn on the display panel, and D[1:0]=”00” to turn off the display panel.
When D1 = 1, display is on; when D1 = 0, display is off. When display is off, the display data is retained
in the GRAM, and can be instantly displayed by setting D1 = 1. When D1= 0, the display is off with the
entire source outputs are set to the GND level.
D[1:0] BASEE Source Output(S1-S528) Internal Operation

2’h0 * GND Halt
2’h1 * GND Operation
2’h2 * Non-lit level Operation
0 Non-lit level Operation
2’h3
1 Base-image display Operation
Source output level and display operation
CL: When CL =”1”, the 8-color display mode is selected.

CL Colors
0 262,144
1 8
DTE, GON: Set gate output level as follows.

GON DTE Gate output
0 0 VGH
0 1 VGH
1 0 VGL
1 1 VGH/VGL
BASEE: BASEE = 1 enable base image display. When BASEE = “0”,no base image is displayed.
PTDE[1:0]: Partial image enable bits.

PTDE1/0 = 0: turns off partial image. Only base image is displayed.
PTDE1/0 = 1: turns on partial image. Set the base image display enable bit to 0 (BASEE = 0).
FP [3:0]: Specify the line number of front porch period (a blank period following the end of display).
BP [3:0]: Specify the line number of back porch period (a blank period before the beginning of display).
Internal clock operation mode BP≧2 lines FP≧2 lines FP+BP≦16 lines
RGB interface operation BP≧2 lines FP≧2 lines FP+BP≦16 lines
VSYNC interface operation BP≧2 lines FP≧2 lines FP+BP=16 lines
BP and FP Settings
4’h0 Setting inhibited

4’h2 2(line periods)


4’hA 10(line periods)
4’hB 11(line periods)
4’hC 12(line periods)
4’hD 13(line periods)
4’hE 14(line periods)
4’hF Setting inhibited
Front and Back Porch period (Line periods)
Front and Back Porch periods
ISC[3:0]: Specify the scan cycle of the gate driver when the PTG[1:0] are set to “10” in non-display area.
The scan cycle can be set in odd number of frames from 0 to 31. In this case, polarity is inverted every
scan cycle.
ISC Scan cycle (Fflm)=60HZ
0000 0 frame -
0001 3 frame 50ms
0010 5 frame 84ms
0011 7 frame 117ms
0100 9 frame 150ms
0101 11 frame 184ms
0110 13frame 217ms
0111 15frame 251ms
1000 17frame 284ms
1001 19frame 317ms
1010 21frame 351ms
1011 23 frame 384ms
1100 25frame 418ms
1101 27frame 451ms

1110 29 frame 484ms

1111 31frame 518ms
PTG [1:0]: Set the scan mode of the gate driver in non-display area.
Gate drive operation Source output level
PTG Vcom output
in non-display area in non-display area
00 Normal scan PTS[2:0] setting Vcom alternating output
01 VGL (fixed) - Vcom alternating output
10 Interval scan PTS[2:0] setting Vcom alternating output
11 Setting disabled - -
Note: select frame-inversion AC drive when setting interval scan
PTS[2:0]: Set the source output level in non-display area. When PTS[2] = “1”, the grayscale amplifiers
are halted except V0 and V31 and the step-up operation frequency is slowed down to half when driving
liquid crystal at non-lit level for low power consumption.
PTS[2:0] Source output level Grayscale amplifier Step-up clock frequency
Positive polarity Negative polarity in operation
000 V31 V0 V31 to V0 Register Setting (DC1,DC0)
001 Setting Prohibited Setting Prohibited - -
010 GND GND V31 to V0 Register Setting (DC1,DC0)
011 Hi-Z Hi-Z V31 to V0 Register Setting (DC1,DC0)
100 V31 V0 V31 and V0 Frequency setting by DC1,DC0
101 Setting Prohibited Setting Prohibited - -
110 GND GND V31 and V0 Frequency setting by DC1,DC0
111 Hi-Z Hi-Z V31 and V0 Frequency setting by DC1,DC0
Notes: 1. The power efficiency can be improved by halting grayscale amplifiers and slowing down the
step-up clock frequency only in non-display drive period.
2. The gate output level in non-lit display area drive period is determined by PTG[1:0].
Display Control 4 (R0Ah)
FMARKOE: When FMARKOE=1, NV3029 starts to output FMARK signal in the output interval set by
FMI[2:0]bits.
FMI[2:0]: Set the output interval of FMARK signal according to the display data rewrite cycle and data
transfer.
FMI[2:0] Output Interval
000 1 Frame
001 2 frame
011 4 frame
101 6 frame
External Display Interface Control 1 (R0Ch)
RIM[1:0]: Specify the transfer mode of RGB interface. Set these instruction bits before starting display
operation via external display interface. Do not change the setting during display operation.

RIM[1:0] RGB Interface operation

2’h0 18-bit RGB internal (1transfer/pixel)
2’h1 16-bit RGB internal (1transfer/pixel)
2’h2 6-bit RGB internal (3 transfer/pixel)
RGB interface operation
DM[1:0]: set the interface of display operation. The DM[1:0] bits allow switching between internal clock
operation mode and external display interface operation. However, switching between the RGB interface
operation and the VSYNC interface operation is prohibited.
DM[1:0] Display Interface
2’h0 Internal clock operations
2’h1 RGB interface
2’h2 VSYNC interface
Display Interface
RM Select the interface to access the GRAM. Set RM = 1 when writing display data to the internal RAM
via RGB interface. By setting the RM = 0, the display data can be rewritten via system interface while
performing display operation via RGB interface.
RM RAM Access Interface

0 System interface/VSYNC interface
1 RGB interface
RAM Access Interface
NV3029 allows setting the optimum interface mode for the kind of display on the screen by setting
instruction bits as follows.
Operation Mode RAM Access(RM) Display Operation Mode(DM[1:0]

Internal operating clock System interface(RM=0) Internal clock operation
only(Displaying still pictures) (DM[1:0]=00)
RGB interface(1) RGB interface(RM=1) RGB interface
(Displaying moving pictures) (DM[1:0]=01)
RGB interface(2) System interface(RM=0) RGB interface
(Rewriting still pictures while (DM[1:0]=10)
displaying moving pictures)
VSYNC interface System interface(RM=0) VSYNC interface
(Displaying moving pictures) (DM[1:0]=11)
Frame Marker Position (R0Dh)
FMP[8:0]: Sets the output position of frame cycle (frame marker).

When FMP[8:0]=0, a high-active pulse FMARK is output at the start of back porch period for one display
line period (1H).
Make sure the 9’h000≦FMP≦BP+NL+FP

FMP[8:0] FMARK Output Position
9'h000 0th line
9'h001 1st line
9'h002 2nd line

9'h003 3rd line

. .
. .
. .
9'h14D 333rd line
9'h14E 334th line
9'h14F 335th line
9'h150~9’h1FF Setting disabled
External Display Interface Control 2 (R0Fh)
DPL: Sets the signal polarity of DOTCLK pin.

DPL = 0: input data on the rising edge of DOTCLK
DPL = 1: input data on the falling edge of DOTCLK
EPL: Sets the signal polarity of ENABLE pin.

EPL = 0: writes data DB17-0 when ENABLE = “0” and disables data write operation when
ENABLE = “1”.
EPL = 1: writes data DB17-0 when ENABLE = “1” and disables data write operation when
ENABLE = “0”.
HSPL: Sets the signal polarity of HSYNC pin.

HSPL = 0: low active
HSPL = 1: high active
VSPL: Sets the signal polarity of VSYNC pin.
VSPL = 0: low active
VSPL = 1: high active
Power Control 1 (R10h)
SLP: When SLP = “1”, NV3029 enters the sleep mode. In sleep mode, the internal display
operation halts to reduce current consumption.
PSON: Power supply ON bit. When turning on the power supply, set PSON=1 to start internal power
supply operation.

RAM access instruction
RAM Address Set (Horizontal Address) (R20h)
RAM Address Set (Vertical Address) (R21h)
AD[16:0]: set GRAM address initially in the AC (Address Counter).

The address in the AC is automatically updated according to the combination of AM, I/D[1:0]
settings as the data is written to the internal GRAM so that data is written consecutively
without resetting the address in the AC.
AD[16:0] GRAM Data Map

17’h00000~17’h000EF 1st line GRAM Data
17’h00100~17’h001EF 2nd line GRAM Data
17’h00200~17’h002EF 3rd line GRAM Data
17’h00300~17’h003EF 4th line GRAM Data
… …
17’h13D00~17’h13DEF 318th line GRAM Data
17’h13E00~17’h13EEF 319th line GRAM Data
17’h13F00~17’h13FEF 320th line GRAM Data
GRAM Address Mapping
Write Data to GRAM (R22h)
WD[17:0]: Set the write access of GRAM. The data are transformed into 18-bit bus before written to
GRAM through the write data register. After the write data register is set, the address is automatically
updated according to the AM and I/D bits while writing data consecutively.

18-Bit interface(262,144colors)
GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
write data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
One pixel
GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
One pixel
1st Transfer(Upper) 2nd Transfer(Lower)
DB
GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
write data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
One pixel
Write data to GRAM (18/16/9-bit interfaces): Bit assignment

8-Bit interface(65,536colors) TR1=0

1st Transfer 2nd Transfer
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
One pixel
8-Bit interface(262,144colors) TR1=1,DFM=0
1st Transfer 2nd Transfer 3rd Transfer
11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
One pixel
8-Bit interface(262,144colors) TR1=1,DFM=1
DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
write data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
One pixel
Write data to GRAM (8-bit interface): Bit assignment

18-Bit RGB interface(262,144colors)
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
One pixel
17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1
write data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 11 10 9 8 7 6 5 4 3 2 1
One pixel
DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
write data 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
One pixel
Write data to GRAM (18/16/6-bit RGB interfaces): Bit assignment

Read Data from GRAM (R22h)
RD[17:0]: 18-bit data read from the GRAM. The bit assignment between RD[17:0] and DB[17:0] (data
bus) differs according to the selected interface.
When NV3029 reads data from the GRAM to the microcomputer, the first read operation after setting
RAM address (AD15-0) is dummy read and the first read data is invalid data. Valid data is sent to the data
bus as NV3029 reads out the second and the subsequent words.
18-Bit RGB interface
GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
One pixel
Read data RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB DB
Output DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read data from GRAM: 18-bit interface

16-Bit interface
One pixel
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
9-Bit interface
One pixel
RD RD
Read data RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB DB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
8-Bit interface
One pixel
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
Read data from GRAM: 16/9/8-bit interface
Gamma Control (R30h to R3Dh)

Gamma control (R40h toR4Dh)
Gamma control (R70h toR7Dh)


PKP5-0 [2:0]/ PKP15-10 [2:0]/PKP25-20[2:0]:Gamma adjustment register for positive polarity output
PRP1-0[2:0]/ PRP11-10[2:0]/PRP21-20[2:0]: Gamma gradient adjustment register for positive polarity
output
PKN5-0 [2:0]/ PKN15-10 [2:0]/PKN25-20[2:0]:Gamma adjustment register for negative polarity output
PRN1-0[2:0]/ PRN11-10[2:0]/PRN21-20[2:0]:Gamma gradient adjustment register for negative polarity
output
VRP1-0[4:0]/ VRP11-10[4:0]/VRP21-20[4:0]:amplification adjustment resistor for positive polarity
output
VRN1-0[4:0]/ VRN11-10[4:0]/VRN21-20[4:0]:amplification average adjustment resistor for negative
polarity output
Window address control instruction

RAM Horizontal Start Address Position (R50h)
RAM Horizontal End Address Position (R51h)
RAM Vertical Start Address Position (R52h)
RAM Vertical End Address Position (R53h)
HSA7-0/HEA7-0: Specify respective addresses at the start and end of the horizontal window address. By
setting HSA and HEA bits, it is possible to limit the area on the GRAM horizontally for writing data. The
HSA and HEA bits must be set before starting RAM write operation. In setting, make sure “00”h≤ HSA7-
0< HEA7-0 ≤ “EF”h.
VSA8-0/VEA8-0: Specify respective addresses at the start and end of the vertical window address. By
setting VSA and VEA bits, it is possible to limit the area on the GRAM vertically for writing data. The
VSA and VEA bits must be set before starting RAM write operation. In setting, make sure “00”h≤ VSA7-
0< VEA7-0 ≤ “13F”h.
Driver Output Control 1 (R60h)

Base Image Display Control (R61h)
Vertical Scroll Control (R6Ah)
SCN[5:0]: Specify the line position where the gate driver starts to scan.
Gate line NO(Scan start position)

SCN[5:0] SM=0 SM=1
GS=0 GS=1 GS=0 GS=1
6’h00 G1 G320 G1 G320

6’h01 G9 G312 G17 G304

6’h02 G17 G304 G33 G288
6’h03 G25 G296 G49 G272
6’h04 G33 G288 G65 G256
6’h05 G41 G280 G81 G240
6’h06 G49 G272 G97 G224
6’h07 G57 G264 G113 G208
6’h08 G65 G256 G129 G192
6’h09 G73 G248 G145 G176
6’h0A G81 G240 G161 G160
6’h0B G89 G232 G177 G144
6’h0C G97 G224 G193 G128
6’h0D G105 G216 G209 G112
6’h0E G113 G208 G225 G96
6’h0F G121 G200 G241 G80
6’h10 G129 G192 G257 G64
6’h11 G137 G184 G273 G48
6’h12 G145 G176 G289 G32
6’h13 G153 G168 G305 G16
6’h14 G161 G160 G2 G319
6’h15 G169 G152 G18 G303
6’h16 G177 G144 G34 G287
6’h17 G185 G136 G50 G271
6’h18 G193 G128 G66 G255
6’h19 G201 G120 G82 G239
6’h1A G209 G112 G98 G223
6’h1B G217 G104 G114 G207
6’h1C G225 G96 G130 G191
6’h1D G233 G88 G146 G175
6’h1E G241 G80 G162 G159
6’h1F G249 G72 G178 G143
6’h20 G257 G64 G194 G127
6’h21 G265 G56 G210 G111
6’h22 G273 G48 G226 G95
6’h23 G281 G40 G242 G79
6’h24 G289 G32 G258 G63
6’h25 G297 G24 G274 G47
6’h26 G305 G16 G290 G31
6’h27 G313 G8 G306 G15
6’h28-6’h3F Setting disabled Setting disabled Setting disabled Setting disabled
NL[5:0]: Set the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping
is not affected by the number of lines set by this instruction. The number of lines must be the same or
more than the number of lines necessary for the size of the liquid crystal panel.
NL[5:0] Number of lines NL[5:0] Number of lines NL[5:0] Number of lines

6’h00 Setting inhibited 6’h0E Setting inhibited 6’h1C Setting inhibited
6’h01 Setting inhibited 6’h0F Setting inhibited 6’h1D 240(lines)
6’h02 Setting inhibited 6’h10 Setting inhibited 6’h1E 248
6’h03 Setting inhibited 6’h11 Setting inhibited 6’h1F 256
6’h04 Setting inhibited 6’h12 Setting inhibited 6’h20 264
6’h07 Setting inhibited 6’h15 176lines 6’h23 288


6’h0A Setting inhibited 6’h18 Setting inhibited 6’h26 312
6’h0B Setting inhibited 6’h19 Setting inhibited 6’h27 320
6’h0C Setting inhibited 6’h1A Setting inhibited 6’h28-6’h3F Setting inhibited
6’h0D Setting inhibited 6’h1B Setting inhibited
liquid crystal drive lines
GS: Sets the direction of scan by the gate driver in the range determined by SCN[5:0] and NL[5:0].
When GS = 0, the scan direction is from G1 to G320.
When GS = 1, the scan direction is from G320 to G1
REV: When setting REV = 1, the grayscale inversion is enabled. This enables NV3029 to display the
same image from a same set of data whether the liquid crystal panel is normally black or white.
Source output in Display Area
REV GRAM Data
Positive polarity Negative polarity
18’h00000 V31 V0
0 … … …
18’h3FFFF V0 V31
18’h00000 V0 V31
1 … … …
18’h3FFFF V31 V0
VLE: Enables vertical scroll display by setting VLE = 1.
VL[8:0]: Set the scrolling line amount of the base image. The RAM data in the start line address is
displayed on the line, which is set by this instruction. Make sure BSA(0) + VL ≤ BEA (320).
NDL: Set the source output level in non-lit display area. NDL bit can keep the non-display area lit on.
Non-display area
NDL
Positive Negative
0 V31 V0
1 V0 V31
Partial display control instruction

Partial Image 1:
Display Position (R80h),
RAM Address (Start/End Line Address) (R81h/R82h)
Partial Image 2:
Display Position (R83h),
RAM Address (Start/End Line Address) (R84h/R85h)

RW RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP
R/W 1 0 0 0 0 0 0 0
R80 0[8] 0[7] 0[6] 0[5] 0[4] 0[3] 0[2] 0[1] 0[0]
Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W 1 0 0 0 0 0 0 0
R81 0[8] 0[7] 0[6] 0[5] 0[4] 0[3] 0[2] 0[1] 0[0]
Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W 1 0 0 0 0 0 0 0
R82 0[8] 0[7] 0[6] 0[5] 0[4] 0[3] 0[2] 0[1] 0[0]
Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP PTDP

R/W 1 0 0 0 0 0 0 0
R83 1[8] 1[7] 1[6] 1[5] 1[4] 1[3] 1[2] 1[1] 1[0]
Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W 1 0 0 0 0 0 0 0
R84 1[8] 1[7] 1[6] 1[5] 1[4] 1[3] 1[2] 1[1] 1[0]
Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W 1 0 0 0 0 0 0 0
R85 1[8] 1[7] 1[6] 1[5] 1[4] 1[3] 1[2] 1[1] 1[0]
Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PTDP0[8:0]: Set the start display position of partial image 1.

PTSA0[8:0] and PTEA0[8:0]: Sets the start line and end line addresses of the RAM area, respectively for
the partial image 1. Make sure that PTSA0≤ PTEA0when enables the instruction.
PTDP1 [8:0]: Set the start display position of partial image 2.
PTSA1 [8:0] and PTEA1[8:0]: Sets the start line and end line addresses of the RAM area, respectively
for the partial image 2. Make sure that PTSA1≤ PTEA1when enables the instruction.
Make sure not to overlap display areas of partial image 1 and partial image 2 with each other.
Panel interface control
Panel interface control 0 (R90h)
RTNI[4:0]: Sets 1H (line) period when synchronizing NV3029’s display operation with internal clock
signal.
RTNI[4:0] Clock per line RTNI[4:0] Clock per line

5’h10 16 clocks 5’h18 24 clocks
5’h11 17 clocks 5’h19 25 clocks
5’h12 18 clocks 5’h1A 26 clocks
5’h13 19 clocks 5’h1B 27 clocks
5’h14 20 clocks 5’h1C 28 clocks
5’h15 21 clocks 5’h1D 29 clocks
5’h16 22 clocks 5’h1E 30 clocks
5’h17 23 clocks 5’h1F 31 clocks
clocks per line (internal clock operation: 1 clock = 1 OSC)
DIVI[1:0]: set the division ratio of the internal oscillation clock, when NV3029’s display operation is
synchronized with internal oscillation clock. NV3029’s internal operation is synchronized with the

frequency divided internal oscillation clock. When changing the DIVI[1:0] setting, the width of the
reference clock for liquid crystal panel control signals is changed. The frame frequency can be adjusted by
setting RTNI[4:0] and DIVI[1:0].
DIVI[1:0] Division Ratio Internal Operation Clock Unit

2’h0 1/1 One OSC clock
2’h1 1/2 2 OSC clock
OSC: internal oscillation clock
Division ratio of the internal operation clock frequency
VCSIV[2:0]: Sets Vcom charge sharing time when synchronizing with internal clock signal.
0 Setting disabled
1 1clock
2 2clocks
3 3clocks
4 4clocks
5 5clocks
6 6clocks
7 7clocks
VCSIE: Set Vcom charge sharing off/on when synchronizing with internal clock signal.
NOWI[2:0]: Set the gate output non-overlap period when synchronizing with internal clock signal.
Note: The clock in this table is a frequency-divided internal clock.
NOWI[2:0] Gate output non-overlap period
3’h0 0(clock period)
3’h1 1clock
3’h2 2clocks
3’h3 3clocks
3’h4 4clocks
3’h5 5clocks
3’h6 6clocks
3’h7 7clocks

MCPI[2:0]: Set the source output timing when synchronizing with internal clock signal.
MCPI[2:0] Source output timing from a reference point

3’h0 Setting disabled
3’h1 1clock
3’h2 2clocks
3’h3 3clocks
3’h4 4clocks
3’h5 5clocks
3’h6 6clocks
3’h7 7clocks
Note: The clock in this table is a frequency-divided internal clock.
RTNE[5:0]:.Set the number of DOTCLK in 1H period combined with DIVE[1:0]. Specify this instruction
in RGB operation.
DIVE[1:0]: DIVE[1:0] sets the division ratio of DOTCLK, when the NV3029 performs display operation
via RGB interface. The NV3029’s internal operation is synchronized with the frequency divided
DOTCLK in RGB interface operation.
Division 18-bit,1transfer DOTCLK= 8-bit,3 transfer

DIVE[1:0] DOTCLK=5MHZ
Ratio RGB interface 5MHZ RGB interface
2’h0 Setting disabled Setting disabled - Setting disabled -
2’h1 1/4 4DOTCLKS 0.8us 12DOTCLKS 0.8us
2’h2 1/8 8DOTCLKS 1.6uS 24DOTCLKS 1.6us
2’h3 1/161 16DOTCLKS 3.2uS 48DOTCLKS 3.2us
Internal operation clock unit (DOTCLK)
RTNE[5:0] DOTCLK per line(1H) RTNE[5:0] DOTCLK per line(1H)

6’h00-0F Setting disabled 6’h28 40clocks
6’h10 16clocks 6’h29 41clocks
6’h11 17 clocks 6’h2A 42clocks
6’h12 18 clocks 6’h2B 43clocks
6’h13 19 clocks 6’h2C 44clocks
6’h14 20 clocks 6’h2D 45clocks
6’h15 21 clocks 6’h2E 46clocks
6’h16 22 clocks 6’h2F 47clocks
6’h17 23 clocks 6’h30 48clocks
6’h1A 26 clocks 6’h33 51clocks
6’h1B 27 clocks 6’h34 52clocks
6’h1C 28 clocks 6’h35 53clocks
6’h1D 29 clocks 6’h36 54clocks
6’h1E 30 clocks 6’h37 55clocks
6’h1F 31 clocks 6’h38 56clocks

6’h21 33 clocks 6’h3A 58clocks

6’h22 34 clocks 6’h3B 59clocks
6’h23 35 clocks 6’h3C 60clocks
6’h24 36 clocks 6’h3D 61clocks
6’h25 37clocks 6’h3E 62clocks
6’h26 38 clocks 6’h3F 63clocks
6’h27 39 clocks
DOTCLK per line (1H period)
VCSEE: Set Vcom charge sharing off/on in RGB interface operation.
VCSEV[2:0]: Sets Vcom charge sharing time in RGB interface operation.

0 Setting disabled
1 1clock
2 2clocks
3 3clocks
4 4clocks
5 5clocks
6 6clocks
7 7clocks
NOWE[3:0]: Set the gate output non-overlap period in RGB operation.

NOWE[3:0] Non-overlap period NOWE[3:0] Non-overlap period
4’h0 0(internal clock period*see note) 4’h8 8(internal clock period*see note)
4’h1 1 4’h9 9
4’h2 2 4’hA 10
4’h3 3 4’hB 11
4’h4 4 4’hC 12
4’h5 5 4’hD 13
4’h6 6 4’hE 14
4’h7 7 4’hF 15
Note: 1clock=(Number of data transfers/pixel) x DIVE (division ratio)[DOTCLK]

MCPE[2:0]: Specify the source output timing and Vcom alternating timing for liquid crystal AC drive in
RGB operation.
Source output position

MCPE[2;0]
Vcom alternating timing
3’h0 Setting disabled
3’h1 1clock
3’h2 2clocks
3’h3 3clocks
3’h4 4clocks
3’h5 5clocks
3’h6 6clocks
3’h7 7clocks
Source output timing from a reference point
Note: 1clock=(Number of data transfers/pixel) x DIVE (division ratio)[DOTCLK]
Vdv_otp, vcm_otp are initially loaded from OTP and can be written by register later.
VCM0[5:0]+VCM_otp[5:0]=VCM[5:0]
VDV0[4:0]+VDV_otp[4:0]=VDV[4:0]
VCM[5:0]: Adjust the VcomH level (the higher level of Vcom AC voltage). The VCM5-0 bits can set the
VcomH level 0.4 ~ 0.98 times the VREG1OUT level. When VCM4-0 = “111111”, stop the internal
volume adjustment and adjust the VcomH with external resistance from VcomR.
VDV[4:0] Adjust the factor of VREG1OUT to set the amplitude of Vcom.
VCM<5:0> VCOMH VCM<5:0> VCOMH

000000 Vreg1out*0.685 100000 Vreg1out*0.845
000001 Vreg1out*0.690 100001 Vreg1out*0.850
000010 Vreg1out*0.695 100010 Vreg1out*0.855
000011 Vreg1out*0.700 100011 Vreg1out*0.860
000100 Vreg1out*0.705 100100 Vreg1out*0.865
000101 Vreg1out*0.710 100101 Vreg1out*0.870
000110 Vreg1out*0.715 100110 Vreg1out*0.875
000111 Vreg1out*0.720 100111 Vreg1out*0.880
001000 Vreg1out*0.725 101000 Vreg1out*0.885
001001 Vreg1out*0.730 101001 Vreg1out*0.890
001010 Vreg1out*0.735 101010 Vreg1out*0.895
001011 Vreg1out*0.740 101011 Vreg1out*0.900
001100 Vreg1out*0.745 101100 Vreg1out*0.905
001101 Vreg1out*0.750 101101 Vreg1out*0.910
001110 Vreg1out*0.755 101110 Vreg1out*0.915
001111 Vreg1out*0.760 101111 Vreg1out*0.920
010000 Vreg1out*0.765 110000 Vreg1out*0.925
010001 Vreg1out*0.770 110001 Vreg1out*0.930
010010 Vreg1out*0.775 110010 Vreg1out*0.935
010011 Vreg1out*0.780 110011 Vreg1out*0.940
010100 Vreg1out*0.785 110100 Vreg1out*0.945
010101 Vreg1out*0.790 110101 Vreg1out*0.950
010110 Vreg1out*0.795 110110 Vreg1out*0.955

010111 Vreg1out*0.800 110111 Vreg1out*0.960

011000 Vreg1out*0.805 111000 Vreg1out*0.965
011001 Vreg1out*0.810 111001 Vreg1out*0.970
011010 Vreg1out*0.815 111010 Vreg1out*0.975
011011 Vreg1out*0.820 111011 Vreg1out*0.980
011100 Vreg1out*0.825 111100 Vreg1out*0.985
011101 Vreg1out*0.830 111101 Vreg1out*0.990
011110 Vreg1out*0.835 111110 Vreg1out*0.995
011111 Vreg1out*0.840 111111 Vreg1out*1.000
VDV<4:0> |COMH-VCOML| VDV<4:0> |VCOMH-VCOML|

00000 Vreg1out*0.70 10000 Vreg1out*0.94
00001 Vreg1out*0.72 10001 Vreg1out*0.96
00010 Vreg1out*0.74 10010 Vreg1out*0.98
00011 Vreg1out*0.76 10011 Vreg1out*1.00
00100 Vreg1out*0.78 10100 Vreg1out*1.02
00101 Vreg1out*0.80 10101 Vreg1out*1.04
00110 Vreg1out*0.82 10110 Vreg1out*1.06
00111 Vreg1out*0.84 10111 Vreg1out*1.08
01000 Vreg1out*0.86 11000 Vreg1out*1.10
01001 Vreg1out*0.88 11001 Vreg1out*1.12
01010 Vreg1out*0.90 11010 Vreg1out*1.14
01011 Vreg1out*0.92 11011 Vreg1out*1.16
01100 Vreg1out*0.94 11100 Vreg1out*1.18
01101 Vreg1out*0.96 11101 Vreg1out*1.20
01110 Vreg1out*0.98 11110 Vreg1out*1.22
01111 Vreg1out*1.00 11111 Vreg1out*1.24
Note 1) Adjust VREG1OUT and VCM0-5 so that the VcomH level is set within the range of 3.0V~
(DDVDH-0.5)V
Note 2) Adjust VREG1OUT and VDV0-4 so that the Vcom amplitude is set to 6.0V or less
Power Control 10 (R1Ah)

DC1 DC1 DC1 DC0 DC0 DC0[
R/W 1 0 0 0 0 0 0 0 0 0 0
R1A [2] [1] [0] [2] [1] 0]
Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DC0[2:0]: Sets the step-up factor of the step-up circuit 1. To improve the drivability of the step-up circuit
1 and the display quality, use a higher step-up operation frequency, inevitably with the increase of power
consumption. make the trade-off between the quality of display and power consumption.
DC0[2:0] Step-up circuit 1: step-up frequency (fDCDC1)
000 fosc
001 fosc/2
010 fosc/4
011 fosc/8
100 fosc/16
101 Setting inhibited
step-up frequency (Step-up Circuit 1)
Note: Make sure to set DC0 and DC1 so that fdcdc2 is maintained.

DC1[2:0]: Sets the step-up factor of the step-up circuit 2. To improve the drivability of the step-up circuit
2 and the display quality, use a higher step-up operation frequency, inevitably with the increase of the
power consumption. make the trade-off between the quality of display and power consumption.
DC1[2:0] Step-up circuit 2: step-up frequency (fDCDC1)

000 fosc/16
001 fosc/32
010 fosc/64
011 fosc/128
100 fosc/256
step-up frequency (Step-up Circuit 2)
Note: Make sure to set DC0 and DC1 so that fdcdc2 is maintained.
Power Control 11 (R1Bh)

Power Control 12 (R1Ch)
Power Control 13 (R1Dh)
SAP SAP VRH VRH VRH VRH VRH
R1B R/W 1 0 0 0 0 VC[1] VC[0] 0 0 0
[1] [0] [4] [3] [2] [1] [0]
P5v_c
N20v_ N20v_ N20v_ P20v_ P20v_ P20v_ N3v_ N3v_e P5v_
R1C R/W 1 0 0 0 0 0 0 mp_e
md[1] md[0] en md[1] md[0] en mode n en
n
Gamm En_vr
R1D R/W 1 0 0 0 0 0 0 0 0 EN EN EN 0 0 0
a_en eg1
P20v_md[1:0]: Specify VGH and VGL voltage level.

N20v_md[1:0]: Specify VGH and VGL voltage level.
N3v_mode: VCL = -VDD when set NV3v_mode to “0”. VCL = -VCI when set NV3v_mode to “1”.
P5v_en: DDVDH = 2*VCI when set P5v_en to “1”.
Gamma_en: Enables the grayscale amplifier when setting γEN = 1.
P5v_cmp_en:When p5v_cnp_en=0, comparator in 5V is off. When P5v_cnp_en=1, comparator in 5V is
on.
P5v_en: Enable DDVDH when set P5v_en to “1”.
N3v_en: Enable VCL when N3V_en to “1”.
P20v_en and N20v_en: Specify VGH and VGL voltage level.
En[2:0]: Enable pump biasing circuit when En[2:0]=”111”
En_vreg1: Enable/disable signal for Vreg1out OP. en_vreg1=1 enable, en_vreg1=0, disable
(Vreg1out=Hi-z).
P20v_md[1:0] VGH
00 disable
01 2*DDVDH
10 2*DDVDH + VCI
11 3*DDVDH
N20v_md[1:0] VGL
00 disable
01 VCL-DDVDH
10 -2*DDVDH
11 VCL-2*DDVDH
VC[1:0]: Sets the factor applied to VciLVL to generate the reference voltages DDVDH.
VC[1:0] DDVDH(Reference Voltage) (V)

00 5.2
01 5.4
10 5.6
11 5.8
Table VCIOUT output level
SAP[1:0]: Adjust the constant current in the operational amplifier circuit in source driver. Setting a
larger constant current stabilizes the operational amplifier circuit, but current consumption also increases.
VRH[4:0] Set the amplifying rate (1.6 ~ 1.9) of VCI applied to output the VREG1OUT level, which is a
reference level for the VCOM level and the grayscale voltage level.
VRH<4:0> Vreg1out VRH<4:0> Vreg1out
00000 Halt (Hi-z) 10000 Halt (Hi-z)
00001 vciLVL * 2.00 10001 2.5*2.00
00010 vciLVL * 2.05 10010 2.5*2.05
00011 vciLVL * 2.10 10011 2.5*2.10
00100 vciLVL * 2.15 10100 2.5*2.15
00101 vciLVL * 2.20 10101 2.5*2.20
00110 vciLVL * 2.25 10110 2.5*2.25
00111 vciLVL * 2.30 10111 2.5*2.30
01000 vciLVL * 1.60 11000 2.5*1.60
01001 vciLVL * 1.65 11001 2.5*1.65
01010 vciLVL * 1.70 11010 2.5*1.70
01011 vciLVL * 1.75 11011 2.5*1.75
01100 vciLVL * 1.80 11100 2.5*1.80
01101 vciLVL * 1.85 11101 2.5*1.85
01110 vciLVL * 1.90 11110 2.5*1.90
01111 vciLVL * 1.95 11111 2.5*1.95
Make sure that VC and VRH setting restriction:VREG1OUT≤(DDVDH-0.5)
Internal use(R1Eh,R1Fh)(R65h)
OTP Control(R66h)
Power Pdin Pdin Pdin Pdin Pdin Pdin Pdin Pdin
R66 R/W 1 POR Pprog Pwe Ptm[1] Ptm[0] Pa[1] Pa[0]
_sel [7] [6] [5] [4] [3] [2] [1] [0]
PDIN[7:0]: Program data OTP.

PA[1:0]: Programming address.
PTM[1:0]: Test mode,
PWE: Define program cycle.
PPROG: Program mode enabling.
Power_sel: Power supply select.
POR: Write this bit to generate a pulse to read an OTP cell addressed by Pa.
OTP table:

IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
reserv reserv reserv reserv reserv reserv reserv reserv reserv reserv reserv reserv reserv reserv reserv reserv
e e e e e e e e e e e e e e e e
0 0 0 VDV4 VDV3 VDV2 VDV1 VDV0 0 0 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0
CABC Control
CABC Control 0(RC0h): Read Display Brightness Value
RC0 W 1 X X X X X X X X BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0
This command read the display brightness value.

When CABC OFF(CABC_C=0), the BV[7:0] is the value of DBV[7:0] register.
When CABC ON(CABC_C=1), the BV[7:0] is the CABC brightness value
CABC Control 1(RC1h): Write Display Brightness Value
This command is used to adjust the brightness value of the display. DBV[7:0]: 8 bit, for display brightness
of manual brightness setting and CABC in NV3029. There is a PWM output signal, LEDPWM pin, to
control the LED driver IC in order to control display brightness.
CABC Control 2(RC2h): Write CTRL Display Value
This command is used to control display brightness.
BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.
BCTRL Description
0 Brightness Control Block OFF (DBV[7:0]=00h)
1 Brightness Control Block ON (DBV[7:0] is active)
DD: Display Dimming Control. This function is only for manual brightness setting.
DD Description
0 Display Dimming OFF
1 Display Dimming ON
BL: Backlight Control On/Off
BL Description
0 Backlight Control OFF
1 Backlight Control ON
Dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=1,
e.g. BCTRL: 0 -> 1 or 1-> 0. When BL bit change from “On” to “Off”, backlight is turned off without

gradual dimming, even if dimming-on(DD=1) are selected.
CABC_C: CABC ON/OFF, CABC_C=0, CABC off. When CABC_C=0, LED_PWM is determined by
DBV7-0, BCTRL, DD and BL, when CABC_C!=0, the LED_PWM is determined by internal CABC
block.
CABC Control 3(RC3h): Write CABC Minimum Brightness
This command is used to set the minimum brightness value of the display for CABC function.
CMB[7:0]: CABC minimum brightness control, this parameter is used to avoid too much brightness
reduction. When CABC is active, CABC can not reduce the display brightness to less than CABC
minimum brightness setting. Image processing function is worked as normal, even if the brightness can not
be changed. This function does not affect to the other function, manual brightness setting. Manual
brightness can be set the display brightness to less than CABC minimum brightness. Smooth transition and
dimming function can be worked as normal. When display brightness is turned off (BCTRL=0 of “Write
CTRL Display (B3h)”), CABC minimum brightness setting is ignored. In principle relationship is that 00h
value means the lowest brightness for CABC and FFh value means the highest brightness for CABC.
CABC Control 4(RC4h)
PWM_DIV[7:0]: PWM_OUT output period control. This command is used to adjust the PWM waveform
period of PWM_OUT. The PWM period can be calculated using the equation in the following.
5.8MHz
f =
( PWM _ DIV [7 : 0] + 1) × 255
PWM_DIV[7:0]
fpwm_out
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 22.74KHz
0 0 0 0 0 0 0 1 11.37KHz
0 0 0 0 0 0 1 0 7.58KHz
0 0 0 0 0 0 1 1 5.64KHz
0 0 0 0 0 1 0 0 4.54KHz
. .
. .
1 1 1 1 1 1 0 0 89.9Hz
1 1 1 1 1 1 0 1 89.53Hz
1 1 1 1 1 1 1 0 89.17Hz
1 1 1 1 1 1 1 1 88.81Hz

THREW[4:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that
makes display image white (data=”63) to the total of pixels by image process. After this parameter sets the
number of pixels that makes display image white, threshold grayscale value (DTH) that makes display
image white is set so that the number of the pixels set by this parameter does not change
.
THREW[4:0]
Description
D4 D3 D2 D1 D0
0 0 0 0 0 0%
0 0 0 0 1 1%
…… ……
1 1 1 1 0 30%
1 1 1 1 1 31%
Dim_bt[2:0]: This parameter is used set the transition time of brightness level change in case of user
controlled dimming (CABC_C=0).
Dim_bt [2:0]
Description
D2 D1 D0
0 0 0 1 frames
0 0 1 2 frames
0 1 0 4 frames
0 1 1 8 frames
1 0 0 16 frames
1 0 1 32 frames
1 1 0 64 frames
1 1 1 128 frames
Dim_bs[2:0]: sets the dimming step in case of internal controlled dimming (CABC_C =1).
Dim_bs[2:0]
Description
D2 D1 D0
0 0 0 1 step
0 0 1 2 step
0 1 0 4 steps
0 1 1 8 steps
1 0 0 16 steps
1 0 1 32 steps
1 1 0 32 steps
1 1 1 32 steps

Interface Specifications
The NV3029 has the system interface for instruction setting, and the external display interface for moving
pictures. The NV3029 can be used to select the an optimum interface for the display (moving or still
picture) in order to transfer data efficiently.
As the external display interface, the NV3029 has the RGB interface and the VSYNC interface, enabling
data rewrite operation without flickering the moving picture on the screen.
In RGB interface operation, display operations are performed in synchronization with synchronizing
signals VSYNC, HSYNC, and DOTCLK. Display data are written to the internal RAM according to the
polarity of the data enable signal (ENABLE) via the moving picture display data bus (DB17-0) in
synchronization with VSYNC, HSYNC, and DOTCLK.
In VSYNC interface operation, the internal display operation is synchronized with frame synchronization
signal(VSYNC). The VSYNC interface mode enables to display the moving picture display through the
system interface. In this case, there are some constraints of speed and method to write data to the internal
RAM.
NV3029 works in one of the following 4 modes. The operation mode is set via the control register. When
switching from one mode to another, make sure to follow the relevant sequence in setting instruction bits.
Operation Mode RAM Access Setting (RM) Display Operation Mode(DM)

Internal clock operation Internal clock operation
System interface(RM=0)
(displaying still pictures) (DM1-0=00)
RGB interface(1) RGB interface
RGB interface(RM=1)
(displaying moving pictures) (DM1-0=01)
RGB Interface(2)
RGB interface
(rewriting still pictures while System interface(RM=0)
(DM1-0=01)
displaying moving pictures)
VSYNC interface VSYNC interface
System interface(RM=0)
(displaying moving pictures) (DM1-0=10)
Notes: 1 Instructions are set only via system interface.
2 The RGB and VSYNC Interfaces cannot be used simultaneously.
System Interface and RGB Interface connection

System Interface
The following kinds of system interface are available with the NV3029 and the interface is selected by
setting the IM3/2/1/0 pins. The system interface is used for instruction setting and RAM access.
IM3 IM2 IM1 IM0 MPU-Interface Mode DB Pins in use

0 0 0 0 Setting disabled
0 0 1 0 80-system 16-bit interface DB17 to10 and 8-to-1
0 0 1 1 80-system 8-bit interface DB17 to 10
0 1 0 * Serial peripheral interface (SPI) DB1-0
0 1 1 * Setting disabled
1 0 1 0 80-system 18-bit interface DB17 to 0
1 0 1 1 80-system 9-bit interface DB17 to9
1 1 * * Setting disabled
1. 80-system 18-bit interface
The 80-system 18-bit parallel data transfer is selected by setting the IM3/2/1/0 pins to “1010” levels.
80-system 18-bit interface (1 transfer/pixel, 262,144 colors)

The 80-system 16-bit parallel data transfer is selected by setting the IM3/2/1/0 pins to “0010” levels. The
262K or 65K color can be display through the 16-bit MPU interface. When the 262K color is displayed,
two transfers (1st transfer: 2 bits, 2nd transfer:16bits or 1st transfer:16bits,2nd transfer:2bits) are necessary
for the 16-bit MPU interface.
80-system 16-bit interface

The 80-system 9-bit parallel data transfer using the DB17~DB9 pins is selected by setting the IM3/2/1/0
pins to “1011”. When transferring a 16-bit instruction, it is divided into upper and lower 8 bits (the LSB is
not used), and the upper 8 bits are transferred first. The RAM write data are also divided into the upper
and lower 9 bits, and the upper bits are transferred first. The unused pins DB8-0 pins must be fixed to
either IOVcc or GND level. When writing the index register, the upper byte (8 bits) must be written.
80-system 9-bit interface (2 transfers/pixel, 262,144 colors)

The 80-system 8-bit parallel data transfer using the DB17-10 pins is selected by setting the IM3/2/1/0 pins
to “0011”. When transferring a 16-bit instruction, it is divided into upper and lower 8 bits and the upper 8
bits are transferred first. The RAM data is also divided into the upper and lower 8 bits, and the upper bits
are transferred first. The RAM write data are expanded into 18 bits internally. The unused pins DB9-0
must be fixed to either IOVCC or GND level. When writing the index register, the upper byte (8 bits) must
be written.
80-system 8-bit interface 65,536 colors (2 transfers/pixel): TRI = 0
1 st Transfer 2 nd Transfer
input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
RGB R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
80-system 8-bit interface 262,144 colors (3 transfers/pixel): TRI = 1, DFM = 0
1 st Transfer 2 nd Transfer 3 rd Transfer

input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
80-system 8-bit interface 262,144 colors (3 transfers/pixel): TRI = 1, DFM = 1
1 st Transfer 2 nd Transfer 3 rd Transfer

17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
80-system 8-bit interface

5. Data transfer synchronization in 8/9-bit bus interface mode
NV3029 supports a data transfer synchronization function to reset upper and lower counters which count
the transfers numbers of upper and lower byte in 8/9-bit interface mode. If a mismatch arises in the
numbers of transfers between the upper and lower byte counters due to noise and so on, the “00”h register
is written 4 times consecutively to reset the upper and lower counters so that data transfer will restart with
a transfer of upper byte. This synchronization function can effectively prevent display error if the
upper/lower counters are periodically reset.
Data transfer synchronization in 8/9-bit system interface
6. Serial Peripheral interface (SPI)
The Serial Peripheral Interface (SPI) is selected by setting the IM3/2/1 pins to the “010” levels
respectively. The SPI is available via the chip select line (CS), the serial transfer clock line (SCL), the
serial data input (SDA), and the serial data output (SDO).
Instructions
input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction
IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction code
Data format for SPI

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2
1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
Data transfer from SPI

External Display Interface

The following interfaces are available as the external display interface (RGB interface). The interface is
selected by setting the RIM1-0 bits.
RIM1 RIM0 RGB Interface DB pin
0 0 18-bit RGB interface DB17-0
0 1 16-bit RGB interface DB17-13,11-1
1 0 6-bit RGB interface DB17-12
1 1 Setting disabled
The display operation via the RGB interface is synchronized with VSYNC, HSYNC, and DOTCLK. The
RGB interface transfers minimum necessary data and rewriting the RAM area defined by window address
function. It is necessary to set back and front porch periods before and after a display period, respectively.
NV3029 has the RGB interface for moving picture display and incorporates RAM for storing
moving picture data with highspeed write function in low power consumption. NV3029 allows the use of
system interface to rewrite data, such as icons, in still picture RAM area while displaying a moving picture.
RGB interface

RGB interface timing
The timing chart of 16/18-bit RGB interface is as follows.
One frame
Back porch
Front porch period
period
VSYNC
HSYNC
DOTCLK
ENABLE
DB17-0
VLW = 1H or more
VSYNC
1H
HLW>=1CLK
HSYNC
1CLK
DOTCLK
DTST>=1CLK
ENABLE
DB17-0
Valid data
16/18-bit RGB interface timing

The timing chart of 6-bit RGB interface is as follows.
6-bit RGB interface timing
Note In 6-bit RGB interface mode, RGB dots are transferred each in synchronization with one DOTCLK
input. For this reason, set the cycle of each signal (HSYNC, VSYNC, ENABLE) to contain
DOTCLK inputs of a multiple of 3.
RAM access via system interface in RGB interface mode
NV3029 allows RAM access via the system interface in RGB interface mode. In RGB interface
mode, data are written to the internal RAM in synchronization with DOTCLK while ENABLE is “Low”.
When writing data to the internal RAM via the system interface, set ENABLE “High” to stop writing data
via the RGB interface. Then set RM = “0” to make RAM accessible via the system interface. When
restarting RAM access in RGB interface mode, wait for one read/write cycle. Then, set RM = “1” and the
index register to R22h to start accessing RAM via the RGB interface. If RAM accesses via two interfaces
conflicts, there is no guarantee that data are written to the internal RAM.
The following figure shows the operation of rewriting data in the still picture RAM area via the system
interface when displaying a moving picture via the RGB interface.

Frame Frame
rewrite rewrite
VSYNC
ENABLE
DOTCLK
DB17-0
System Index
RAM Rewrite data outside the RAM
Index
RM=0 address moving picture address RM=0
interface R22
set RAM area set
R22
Rewrite Rewrite
Rewrite still picture
moving moving
picture area picture area
Note 1) In RGB interface operation, RAM address (AD16-0) is set in the address counter on the falling edge of VSYNC.
Note 2) Set a RAM address (AD16-0) and the index to R22h before starting RAM access via RGB interface.
Updating a still picture area while displaying a moving picture
6-bit RGB interface
The 6-bit RGB interface is selected by setting the RIM1-0 bits to “10”. Display data are transferred to the
internal RAM in synchronization with the display operation via the 6-bit RGB data bus (DB17-12)
according to the data enable signal (ENABLE). Unused pins (DB11 to 0) must be fixed to either Vci or
GND level. Instructions are set only via a system interface.
6-bit RGB interface

Data format for 6-bit interface
Data transfer synchronization in 6-bit RGB interface mode
NV3029 has transfer counters to count the first 3 data transfers in 6-bit RBG interface mode. The transfer
counters are always reset to the state of the first data transfer on the falling edge of VSYNC. If there is a
mismatch in the number of data transfer, the counters are reset to the state of the first data transfer at the
start of each frame (on the falling edge of VSYNC) and data transfer will restart correctly from the next
frame. Because internal display operation is executed in units of pixels (RGB: 3 DOTCLKs), the number
of DOTCLK inputs in one frame period must be a 3 multiple to transfer data in units of pixels. Otherwise,
there will be a discrepancy in data transfer and its effect will continue to the next frame display.
6-bit data transfer synchronization

16-bit RGB interface
The 16-bit RGB interface is selected by setting the RIM1-0 bits to 01. Display data are transferred to the
internal RAM in synchronization with the display operation via the 16-bit RGB data bus
(DB17-13, 11-1) according to the data enable signal (ENABLE). Instructions are set only via system
interface.


The 18-bit RGB interface is selected by setting the RIM1-0 bits to 00. Display data are transferred to the
internal RAM in synchronization with the display operation via the 18-bit RGB data bus (DB17-0)
according to the data enable signal (ENABLE). Instructions are set only via a system interface.
RAM data Write
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
One pixel 262,144 colors available in 18-bit RGB interface

Notes for external display interface
a) These functions are not available in RGB interface mode.

Function External display Interface Internal Display Operation
Partial display Not available Available
Scroll function Not available Available
Interfaced scan Not available Available
Graphics operation function Not available Available
b) The VSYNC, HSYNC, and DOTCLK signals must be supplied during display period.

c) The reference clock to generate liquid crystal panel controlling signals in RGB interface operation is
DOTCLK, not the internal clock generated from the internal oscillator.
d) In 6-bit RGB interface operation, 6-bit dot data (R, G, and B) is transferred in synchronization with
DOTCLK. In other words, it takes three DOTCLKs to transfer one pixel data.
e) In 6-bit RGB interface operation, make sure to set the cycles of VSYNC, HSYNC, DOTCLK,
ENABLE signals so that the data transfer is completed in units of pixels.
f) When switching between the internal operation mode and the external display interface operation
mode, follow the sequences below in setting instruction.
g) In RGB interface operation, front porch period continues after the end of frame period until next
VSYNC input is detected.
h) In RGB interface mode, the RAM address (DB15-0) is set in the address counter for every frame on
the falling edge of VSYNC.
Internal clock operation/RGB interface mode switching

VSYNC Interface
NV3029 has VSYNC interface to display moving pictures with system interface and the frame
synchronizing signal of VSYNC. The VSYNC interface is selected by setting DM1-0 = “10” and RM =
“0”.
VSYNC interface
In VSYNC interface mode, the internal display operation is synchronized with the VSYNC signal. By
writing data to the internal RAM via the system interface at a speed faster to a certain degree than that of
internal display operation, the VSYNC interface enables moving picture display with the system interface
and screen rewriting operation without flicker. The frame rate is determined by the pulse rate of VSYNC
signal.
VSYNC
Updating screen Updating screen

Write data to
RAM through
system interface
Display operation
synchronized with
internal clocks
Moving picture data transfer via VSYNC interface

The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the
system interface, which are calculated from the following formula.
Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (FP) +
BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation.
Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the
falling edge of VSYNC until the start of RAM write operation must also be taken into account.
An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is
as below.
[Example]
Display size: 240 RGB × 320 lines
Lines: 320 lines (NL = 1000111)
Back porch: 14 lines (BP = 1110)
Front porch: 2 lines (FP = 0010)
Frame frequency: 60 Hz
Frequency fluctuation: 10%
Internal oscillator clock (fosc.) [Hz] = 60 x [320+ 2 + 14] x 16 clocks x (1.1/0.9) ≒ 394KHz
When calculate the internal clock frequency, the oscillator variation is needed to be taken into
consideration. In the above example, the calculated internal clock frequency with ±10% margin variation
is considered and ensures to complete the display operation within one VSYNC cycle. The causes of

frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI
voltage variation.
Minimum speed for RAM writing [Hz] > 240 x 320 x 394K / [ (14 + 320 – 2)lines x 16clocks] ≒ 5.7
MHz
The above theoretical value is calculated based on the premise that the NV3029 starts to write data into the
internal GRAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the
physical display line and the GRAM line address where data writing operation is performed. The GRAM
write speed of 5.7MHz or more will guarantee the completion of GRAM write operation before the
NV3029 starts to display the GRAM data on the screen and enable to rewrite the entire screen without
flicker.
Notes in for the VSYNC interface
1. Because of possible variation to be taken into account, enough margin should be allowed in
setting the RAM writing speed.
2. After drawing 1 frame, a front porch period continues until the next input of VSYNC is detected.
3. When switching from the internal clock operation mode (DM[1:0] = “00”) to the VSYNC interface
mode or inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of
the frame.
4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface
mode.

VSYNC/internal clock operation mode switching sequences

Partial Display Function
The partial display function allows the NV3029 to drive lines selectively to display partial images by
setting partial display control registers. The lines not used for displaying partial images are driven at non-
lit display level to reduce power consumption
The power efficiency can be enhanced in combination with8-color display mode. Check the display
quality when using low power consumption functions.

Window Address Function

The window address function enables writing display data consecutively within a rectangular area
(window address area) made on the internal RAM. The window address area is defined by setting the
horizontal address register (start: HSA7-0, end: HEA 7-0 bits) and the vertical address register (start:
VSA8-0, end: VEA8-0 bits). The AM and I/D bits set the transition direction of the RAM address (either
increment or decrement, horizontal or vertical, respectively). Setting these bits enables the NV3029 to
write data including image data consecutively without taking data wrap position into account.
The window address area must be made within the GRAM address map area. Also, the GRAM address
(AD16-0) must be set to an address within the window address area.
Automatic address update within a Window Address Area

8-color Display Mode

The NV3029 has a function to display in eight colors. In 8-color mode, the available grayscales are only
V0 and V31, and the power supplies for other grayscales (V1 to V30) are cut off to reduce power
consumption.
The γ- correction registers, PKP0-PKP5 and PKN0-PKN5, are disabled in 8-color display mode.
In 8-color display mode, the Gamma-micro-adjustment registers are invalid and only the upper bits of
RGB are used for display.
Grayscale Amplifier
8-color Display Mode

OTP Operation
Operate mode
The Por, PProg and PWE determine the OTP operate mode.
Load_otp Pprog Pwe Operation OTP[31:0]

L L L Standby Data Latch
L L H Invalid Invalid data Out
L H L Program Enable Invalid data Out
L H H Program Access Invalid data Out
H L L Read Access Data Out
H L H Invalid Invalid data Out
H H L Invalid Invalid data Out
H H H Invalid Invalid data Out
Write Truth Table

In Programming state, the PA indicates which byte of OTP will be programmed.
Pa[1:0] Write data input Write OTP cell Cell output
0 Pdin[7:0] Cell[7:0] OTP[7:0]
1 Pdin[7:0] Cell[15:8] OTP[15:8]
2 Pdin[7:0] Cell[23:16] OTP[23:16]
3 Pdin[7:0] Cell[31:24] OTP[31:24]
Program OTP
Tvds Tvdr
1.8V
Tvps
0V Tpps 7.5V 0V
VDD
1.8V 1.8V
Tppr
0V 0V
DDVDH
Tpw Tvph
Pprog
Pwe
Tas Tah Tvr
Pa[1:0] XXX Valid Addr. Valid Addr. XXX
Tds Tdh
Pdin[7:0] XXX Valid Data Valid Data XXX
Load_otp=0V,OTP[31:0]=XXX,PTM[1:0]=[00],GND=0V

Read OTP
Tvds Tvdr
1.8V
0V 0V
VDD
1.8V
0V Trst Tpor 0V
DDVDH
Load_otp
Taa
OTP[31:0] XXX Data out XXX
Pprog=0V,Pwe=0V,Pa=don’t care, Pdin[7:0]=don’t care, GND=0V,Ptm[1:0]=[00]
Note: The read out data of OTP are reverse. So, you should write reverse data into OTP and then you can get
the original data.
Timing parameters
EO01X32GCV1A
Parameter Symbol Unit
Min Max
Rising Time/Falling Timing Tt/Tf - 1 ns
Data Access Time Taa - 70 ns
Power-on Pulse Width Time Tpor 70 - ns
Address/Data Setup Time Tas/Tds 4 - ns
Address/Data Hold Time Tah/Tdh 9 - ns
External VPP Setup Time Tvps 0 - ns
External VPP Hold Time Tvph 0 - ns
Program Recovery Time Tvr 10 - us
Program Pulse Width Tpw 90 110 us
VDD Setup Time Tvds 0 - ms
VDD Recovery Time Tvdr 0 - ms
Power on Reset Time Trst 20 - ns
PPROG Setup Time Tpps 10 - ns
PPROG Recovery Time Tppr 10 - ns

CABC(Content Adaptive Brightness Control)
NV3029 provide a dynamic backlight control function as CABC(Content Adaptive Brightness Control) to
reduce the power consumption of the luminance source. NV3029 will refer the gray scale content of
display image to output a PWM waveform to LED driver for backlight brightness control. Content
adaptation means that the content of gray sale can be increased while simultaneously lowering brightness
of the backlight to achieve the same perceived brightness. The adjusted gray level scale and thus the power
consumption reduction depend on the content of the image.
NV3029 can calculate the backlight brightness level and send a PWM pulse to LED driver via LEDPWM
pin for backlight brightness control purpose. The figure in the following is the basic timing diagram which
is applied NV3029 to control LED driver.
The period Tperiod of PWM pulse can be changed by the PWM_DIV[7:0] bits of the command
“PWM_DIV(C4h)”. The LED-on time Ton and the LED-off time Toff are decided by the backlight
brightness level which is calculated with CABC in NV3029. if CABC is off, then LEDPWM will forced
to”L” level.
The pwm period value will be calculated via the equation as below.
5.8MHz
f =
( PWM _ DIV [7 : 0] + 1) × 255

Gamma Correction
NV3029 has the gamma-correction function to display in 262,144 colors for liquid crystal panels. The
gamma-correction is performed with 3 groups of registers determining eight reference grayscale levels,
which are gradient adjustment, amplitude adjustment and fine-adjustment registers for positive and
negative polarities. Each register group is set independently to other register groups, making the NV3029
available with liquid crystal panels of various characteristics.

Grayscale amplifier unit
In grayscale amplifier unit, 8-levels VIN0~VIN7 are determined by gradient and fine adjustment registers.
Then, the 8 levels are divided by the internal ladder resistors between grayscale amplifier and 32 grayscale
levels(V0~V31) are generated.
Grayscale Voltage Generation


γ correction registers
The gamma correction registers of the NV3029 consists of gradient-adjustment, amplitude-adjustment,

fine-adjustment registers to correct grayscale voltage levels according to the gamma characteristics of the
liquid crystal panel. These register settings make adjustments to the relationship between the grayscale
number and its corresponding grayscale voltage level and the setting can be made differently for positive
and negative polarities (the reference level and the register settings are the same for all RGB dots). The
function of each register is as follows.
1.Gradient adjustment registers

The gradient adjustment registers are used to adjust the gradients in the middle grayscale range without
changing the dynamic range. Adjustments are made by changing the resistance values of the resistors
(VRHP(N)/VRLP(N)) in the middle of the ladder resistor unit. The gradient adjustment registers consist
of positive and negative polarity registers to allow asymmetric drive.
2. Amplitude adjustment registers
The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage by changing
the resistance values of the resistors (VRP(N)1/0) at both ends of the ladder resistor unit. Same with the
gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers.
3. Fine adjustment registers
The fine adjustment registers are used for minute adjustment of grayscale voltage. The fine adjustment
register represent one voltage level to be selected in the 8-to-1 selector among 8 levels generated from the
ladder resistor unit. Same with other registers, the fine adjustment registers consist of positive and
negative polarity registers.
Register Positive Negative Function

Gradient PRP0[2:0] PRN0[2:0] Variable resistor VRHP(N)
PRP1[2:0] PRN1[2:0] Variable resistor VRLP(N)
Amplitude VRP0[4:0] VRN0[4:0] Variable resistor VRP(N)0
VRP1[4:1] VRN1[4:1] Variable resistor VRP(N)1
Fine PKP0[2:0] PKN0[2:0] 8 to 1 selector(grayscale 1-3 voltage levels)
adjustment PKP1[2:0] PKN1[2:0] 8 to 1 selector(grayscale 4 voltage levels)
PKP2[2:0] PKN2[2:0] 8 to 1 selector(grayscale 10 voltage levels)
PKP5[2:0] PKN5[2:0] 8 to 1 selector(grayscale 28-30 voltage levels)

Reference voltage generating block (Ladder resistor units and 8-to-1 selectors)
Block configuration
The ladder resistor and 8-to-1 selector unit shown in page 144 consists of two ladder resistor unit including
variable resistors and 8-to-1 selectors which selects a voltage generated by the ladder resistor unit and
output the reference voltage from which grayscale voltages are generated. The correction registers
represent the resistance values of these resistors in the ladder resistor unit and the reference levels selected in the 8-
to-1 selectors (see Table 68 γ correction register).
Variable resistors
The NV3029 uses variable resistors for the following three purposes: gradient adjustment
(VRHP(N)/VRLP(N)); amplitude adjustment (1) (VRP(N)0); and amplitude adjustment (2) (VRP(N)1). The
resistance values are determined by gradient adjustment and amplitude adjustment registers as below.
Register Resistance
Register Resistance Resistance Register
VRP(N)1 VRHP(N)
VRP(N)0[4:0] VRP(N)0 VRP(N)1 PRP(N)0/1[2:0]
[4:0] VRLP(N)
00000 0R 00000 0R 000 0R
00001 1R 00001 1R 001 4R
00010 2R 00010 2R 010 8R
011 12R
… … … …
100 16R
11101 29R 11101 29R 101 20R
11110 30R 11110 30R 110 24R
11111 31R 11111 31R 111 28R
Amplitude Adjustment Amplitude Adjustment 2 Gradient Adjustment
8 to 1 selector
The 8-to-1 selector selects one voltage level according to the fine adjustment register setting among the
voltages generated by ladder resistors, and outputs the selected level as one of the reference voltages
(VINP(N)1~6). The following table shows the correspondence between the selected voltage levels and the fine-
adjustment register settings for respective reference voltage levels (VINP(N)1~6).
Value in Register Voltage level

VINP VINP VINP VINP VINP VINP
PKP(N)0/1[2:0]
（N）1 （N）2 （N）3 （N）4 （N）5 （N）6
000 KVP(N)1 KVP(N)9 KVP(N)17 KVP(N)25 KVP(N)33 KVP(N)41

The grayscale levels are determined by the following formulas.
Voltage Calculation Formula (Positive Polarity)

Reference Macro Adjustment
Formula Pin
Voltage Value
VgP0 - VGAM1OUT-VD*VRP0 /sumRP KVP0
PKP0 2-0=000 VGAM1OUT-VD((VRP0+5R) /sumRP KVP1
VINP1
PKP1 2-0=000 VGAM1OUT-VD((VRP0+33R+VRHP) /sumRP KVP9
VINP2
PKP1 2-0=110 VGAM1OUT-VD((VRP0+39R+VRHP) /sumRP K VP15
VINP3
VINP4
PKP4 2-0=001 VGAM1OUT-VD((VROP0+81R+VRHP) /sumRP KVP34
VINP5
PKP5 2-0=000 VGAM1OUT-VD((VRP0+87R+VRHP+VRLP) /sumRP KVP41
VINP6 PKP5 2-0=100 VGAM1OUT-VD((VRP0+103R+VRHP+VRLP) /sumRP KVP45
VINP7 - VGAM1OUT-VD((VRP0+120R+VRHP+VRLP) /sumRP KVP49
SumRP=128R+VRHP+ VRLP+ VRP0+VRP1,
VD=(VGAM1OUT-VGS)
sumRPx (sumRN/ (sumRP+sumRN))]/ [sumRPx sumRN/ (sumRP+sumRN) +EXVR])

Voltage Calculation Formula (Negative Polarity)

Reference Macro Adjustment
Formula Pin
Voltage Value
VINN0 - VGAM1OUT-VD*VRN0 /sumRN KVN0
PKN0 2-0=000 VGAM1OUT-VD((VRN0+5R) /sumRN KVN1
VINN1
PKN1 2-0=000 VGAM1OUT-VD((VRN0+33R+VRHN) /sumRN KVN9
VINN2
VINN3
VINN4
VINN5
PKN5 2-0=000 VGAM1OUT-VD((VRN0+87R+VRHN+VRLN) /sumRN KVN41
VINN6
PKN5 2-0=100 VGAM1OUT-VD((VRN0+103R+VRHN+VRLN)/sumRN KVN45
VINN7 - VGAM1OUT-VD((VRN0+120R+VRHN+VRLN)/sumRN KVN49
SumRP=128R+VRHN+VRLN+VRN0+VRN1
VD=(VGAM1OUT-VGS)
sumRPx (sumRN/ (sumRP+sumRN))]/ [sumRPx sumRN/ (sumRP+sumRN) +EXVR]

Relationship between RAM data and voltage output levels
V0
Negative polarity
Output
level
Positive polarity
V31
RAM data
000000
111111
Note: The source output and RAM data relationship is the same for all RGB dot
RAM data and the output voltage relationship (REV = 0)
Sn
Negative polarity
Vcom
Positive polarity
Source output and Vcom relationship

Power Supply Setting

When supplying and cutting off power, follow the following sequence. The setting time for oscillators,
step-up circuits and operational amplifiers depends on external resistance and capacitance.
Power ON sequence Power supply OFF sequence
Power supply(Vci,IOVcc) ON Normal display DTE=1,D=2h3,GON=1,

Vci
IOVcc
GND Display OFF sequence
IOVcc Vci
IOVcc,Vci simultaneously
Vcom disable
Pump disable
Power supply OFF setting
Power ON reset DTE=0,D=2'h0,GON=0
Power supply(Vci,IOVcc) OFF
Vci
IOVcc
Use setting(1)
Initial instruction setting NL,BP,FP,Gamma settings GND
and others Vci IOVcc
IOVcc,Vci simultaneously
Power supply user setting

R10h: APE=1, AP, BT, SAP=1
R11h: VC, DC0, DC1
R12h: VRH,PON=1,VON=0
R13h: VCM, VDV, VCOMG=1
Power supply
Startup time
(8 frames x 1/OSC) Other mode setting LCD
instruction Power supply
ON sequence
Display on sequence

Voltage Generation
The pattern diagram of voltage setting and an example of waveforms of NV3029 are as follows.
Pattern Diagram for Voltage Generation
Note: The DDVDH, VGH and VGL output voltages will become lower than their theoretical levels
(ideal voltages) due to current consumption at each output level. The voltage levels in the
following relationships (DDVDH – VREG1OUT) > 0.5V and (VcomDC – GND) > 0.5V are
the actual voltage levels. When the alternating cycle of Vcom is set high (e.g., the polarity
inverts at every line cycle), current consumption will increase. In this case, check the voltage
before use.
VGH
VREG1OUT
VcomDC
Vcom
VRS
Sn (Source driver output)
Gn
(panel Interface output)
VGL
TFT display application voltages

Application
EXTC
IM3
IM2
IM1
IM0
RESE
T
CS
RS
WR
RD
VSYNC
HSYN
C
ENABLE
DOTCLK
SDA
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
TE
SDO
BC
BC_CTR
L
VDD3_P
DB18
DB19
DB20
DB21
DB22
DB23

Electrical Characteristics
Absolute Maximum Ratings
Item Symbol Unit Ratings Notes

Power-supply voltage(1) Vci,IOVCC V -0.3 to +3.6 1,2
Power-supply voltage(2) VCI-GNDA V -0.3 to +3.6 1,3
Power-supply voltage(3) DDVDH-GNDA V -0.3 to +6.0 1,4
Power-supply voltage(4) VGH-VGL V -0.3 to +30.0 1,4
Power-supply voltage(5) GNDA-VGL V +3.0 to +13.0 1,7
Power-supply voltage(6) DDVDH-VGL V +4.0 to +19.0 1,5
Power-supply voltage(7) VCI-VGL V +3.0 to + 16.8 1,7
Input voltage Vt V -0.3 to 3.9 1
Operating temperature Topr ℃ -40 to +85 1,8
Storage temperature Tstg ℃ -55 to +110 1
DC Characteristic
VCI = 2.4 ~ 3.3V, IOVCC = 1.65~3.3V, Ta = -40 ~ 85 °C
Not
Item Symbol Unit Test Condition Min. Typ. Max.
e
Input high voltage V 0.8* - IOVCC 2,3
VIH IOVCC = 1.65V ~ 3.3 V
IOVCC
0.2*
Input low voltage VIL V IOVCC = 1.65V ~ 3.3 V – 0.3V - 2,3
IOVCC
Output high voltage 0.8 *
VOH V IOH = -0.1mA - - 2
(DB0-17 pins, FMARK) IOVCC
Output low voltage IOVCC = 1.65 ~ 2.4 V 0.2*
VOL V - - 2
(DB0-17 pins, FMARK) IOL = 0.1mA IOVCC
I/O leak current ILi µA Vin = 0 ~ IOVCC -1 1 4
VCI=IOVCC=VCI=2.8V,
Current consumption during Ta=25C, GRAM data
normal operation =0000h, Frame
IOP(VCI) mA - - 8.5
(VCI-GND)+(IOVCC- rate=70HZ, REV=0,
GND) SAP=100,AP=100,DC0=
000,DC1=010,B/C=0,
Current consumption during VC=001,VRH=0011,
Sleep operation VCM=10011,VDV=1000
IOP(VCI) µA 0,VCOMG=1,CL=0 - - 130 5,6
(VCI-GND)+(IOVCC-
GND) Panel load
Notes: 1.If used beyond the absolute maximum ratings, the LSI may permanently be damaged. It is
strongly recommended to use the LSI within the electrical characteristics conditions in normal
operation. Exposure to a condition not within the electrical characteristics may affect reliability
of the device.
2. Make sure (RVCI=VCI) (high) ≥ GND (low) and IOVCC (high) ≥ GND (low).
3. Make sure VCI (high) ≥GNDA (low).
4. Make sure DDVDH (high) ≥GNDA (low).
5. Make sure DDVDH (high) ≥ VGL (low).
6. Make sure VGH (high) ≥GNDA (low).
7. Make sure GNDA (high) ≥ VGL (low).
8. The DC/AC characteristics of die and wafer products are guaranteed at 85 ºC.

AC Characteristics
80-system Bus Interface Timing Characteristics (18-/16-bit Transfer Mode)
IOVCC = 1.65V to 3.30V, VCI = 2.5V ~ 3.3V

Item symbol Unit Min. Typ. Max.
Write tCYCW ns 125 - -
Bus cycle time
Read tCYCR ns 450 - -
Write (RS~CS, WR) 0
Setup time tAS ns - -
Read (RS~CS, RD) 10
Write high-level pulse width ns 70 - -
PWHW
Read high-level pulse width ns 250 - -
PWHR
Write/Read rise/fall time tWRr ,tWRf ns - - 25
Address hold time tAH ns 2 - -
Write data setup time tDSW ns 25 - -
Write data hold time tH ns 10 - -
Read data delay time tDD ns - - 150
Read data hold time tDHR ns 5 - -
Write low-level pulse width PWLW ns 45 - 500
Read low-level pulse width PWLR ns 170 - -
80-system Bus Interface Timing Characteristics (9-/8-bit Transfer Mode)
IOVCC = 1.65V to 3.30V, VCI = 2.5V ~3.3V

Write tCYCW ns 70 - -
Bus cycle time
Read tCYCR ns 450 - -
Write (RS~CS, WR) 0
Setup time tAS ns - -
Read (RS~CS, RD) 10
Write high-level pulse width ns 25 - -
PWHW
Read high-level pulse width ns 250 - -
PWHR
Write/Read rise/fall time tWRr ,tWRf ns - - 25
Address hold time tAH ns 2 - -
Write data setup time tDSW ns 25 - -
Write data hold time tH ns 10 - -
Read data delay time tDD ns - - 150
Read data hold time tDHR ns 5 - -
Write low-level pulse width PWLW ns 30 - -
Read low-level pulse width PWLR ns 170 - -

Serial interface Timing Characteristics
IOVCC = 1.65 V to 3.30 V, VCI= 2.5V ~ 3.3V

Item Symbol Unit Min. Typ. Max.
Write (received) tSCYC ns 100 - 20,000
Serial clock cycle time
Read (Transmitted) tSCYC ns 350 - 20,000
Serial clock high-level Write (received) tSCH ns 40 - -
pulse width Read (Transmitted) tSCH ns 150 - -
Serial clock low-level Write (received) tSCL ns 40 - -
pulse width Read (Transmitted) tSCL ns 150 - -
Serial clock rise/fall time tSCr, tSCf ns - - 20
Chip select setup time tCSU ns 20 - -
Chip select hold time tCH ns 60 - -
Serial input data setup time tSISU ns 30 - -
Serial input data hold time tSIH ns 30 - -
Serial output data delay time tSCO ns - - 130
Serial output data hold time tSOH ns 5 - -

80-system Bus Interface Operation
Reset Timing Characteristics
IOVCC= 1.65 V to 3.3 V, VCI= 1.8V ~ 3.3V

Reset low-level width tRES us 20 - -
Reset rise time tTRES us - - 10
tRES t rRES Send instructions

and data
VIH
RESET
VIL VIL 20ms
Reset operation

Liquid crystal driver Output Characteristics

Item symbol Unit Test Condition Min. Typ. Max. Note
VCI=3.00v,DDVDH=5.50V
VREG1OUT=5.00V,
RC oscillation fosc=6MHZ (drive
320 lines),Ta=25℃
Tdd1 us - - 17 10
REV=0,AP=010,SAP=010,
VRP14-00=0,VRN14-00=0,
Source-drive PKP52-00=0,PKN52-00=0,
output delay PRP12-00=0,PRN12-00=0,
time Load resistance R=10kΩ,
Load capacitance C=20Pf
Time to reach the target voltage
Tdd2 us level+/-35mv from Vcom Polarity - - 17 11
inversion timing
Transient from a same grayscale at
all source pins
Liquid crystal drive output

RGB Interface Timing Characteristics
18-/16-bit RGB Interface, IOVCC= 1.65 V to 3.30 V, VCI = 2.5V ~ 3.3V

VSYNC/HSYNC setup time tSYNCS clock 0 1
ENABLE setup time tENS ns 10 -
ENABLE hold time tENH ns 20 -
DOTCLK low-level pulse width PWDL ns 40 -
DOTCLK high-level pulse width PWDH ns 40 -
DOTCLK cycle time tCYCD ns 100 -
Data setup time tPDS ns 10 -
Data hold time tPDH ns 40 - -
DOTCLK,VYSNC,HSYNC trgbr,
ns - - 25
rise/fall time trgbf

6-bit RGB Interface, IOVCC = 1.65 V to 3.30 V, VCI= 2.5V ~ 3.3V

VSYNC/HSYNC setup time tSYNCS clock 0 -
ENABLE setup time tENS ns 10 -
ENABLE hold time tENH ns 25 -
DOTCLK low-level pulse width PWDL ns 25 -
DOTCLK high-level pulse width PWDH ns 25 -
DOTCLK cycle time tCYCD ns 60 - -
Data setup time tPDS ns 10 - -
Data hold time tPDH ns 25 - -
DOTCLK,VYSNC,HSYNC rise/fall time trgbr, trgbf ns - - 25
RGB interface operation

Revision history
Version No Date Page Introduction
1.0 2010-6-23 New build

1.1 2010-6-24 51 Modify register R1Ch
1.2 2010-7-23 25 Add register R1Eh and R1Fh
1.3 2010-8-2 91 Modify Application
1.4 2010-8-5 8,91 Add “SDA”,” VDDR” pin function
1.5 2010-8-6 7,62 Modify “Data transfer from SPI” Figure
1.6 2010-8-12 91
1.7 2010-10-11 90,52,82 Modify gamma diagram and add register
1.8 2010-10-12 30 (R1Ch)description
1.9 2010-10-14 80

Information furnished is believed to be accurate and reliable. However, New Vision

Microelectronics Inc. assumes no responsibility for the consequences of use of such
information nor for any infringement of patents or other rights of third parties, which may
result from its use. No license is granted by implication or otherwise under any patent or
patent rights of New Vision Microelectronics Inc. Specifications mentioned in this publication
are subject to change without notice. This publication supersedes and replaces all information
if previously supplied.

NV3029datasheet V1.9

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New Vision Microelectronics Inc.

NV3029 Data sheet

240RGB x 320dot, 262,144-color

Preliminary Version 1.9

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Driver Output Control 1 (R60h) ............................................................................................................. 43

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Electrical Characteristics ................................................................................................................92

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GND Logic Ground System ground level for logic blocks

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Interface logic pins

Signal I/O Function

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SPI interface output pin.

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Driver input/output pins

Signal I/O Function

S1 to S720 O Source driver output pads.

G1 to G320 O Gate driver output pads

VGL O Power supply for the gate driver

VCOML O Dummy pin. Leave these pads open.

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NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y

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NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y

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NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y

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NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y

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NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y

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NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y

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NO Pad_name X Y NO Pad_name X Y NO Pad_name X Y

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L_AMK -7480 260

R_AMK 7480 260

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2. External Display Interface (RGB, VSYNC interfaces)

3. Address Counter (AC)

4. Graphics RAM (GRAM)

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5. Grayscale Voltage Generating Circuit

8. Liquid crystal driver Circuit

9. Internal logic power supply regulator

10. Liquid crystal drive power supply circuit

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PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA

R90h Panel IF Control 1 W/R 1 0 0 0 0 0 0 DIVI1 DIVI0 0 0 0 RTNI4RTNI3RTNI2RTNI1RTNI0

VCSI VCSI VCSI VCSI

R1Eh Internal use1 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

R1Fh Internal use2 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

R65h Internal use3 W/R 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1