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Abstract— Embedded world constantly improving on daily
basis, no matter if it comes to integration level, power
consumption or performances. Central role in these challenges
takes System-on-Chip (SoC) with its heterogeneous structure and
great performances. This paper presents how SoC components
communicate with each other with emphasis on Digital Signal
Processor (DSP) communication to general purpose processors
and possibilities of computation offloading.
Keywords—System-on-Chip, DSP, CPU, offloading, IPC,
GPU, HSA,
I. INTRODUCTION
No so long ago there was only one main chip called central
processor unit (CPU) which was responsible for all the work
that had to be done. That means we have one general purpose
unit in charge of different types of tasks. Beside that you need
lots of different components like memory to store data, audio
chip to decode music, GPU (Graphic Processing Unit) to draw
graphic and other smaller components that all have important
tasks.
The evolution of electronic and capabilities of high level
integration ensured production of different components in one
chip better known as System-on-Chip. SoC encapsulates most
of all required modules like GPU, DSP, memory or power
management circuits in one silicon chip. Very high level of
integration and short wiring means it also uses less power
which is mandatory in embedded devices like smartphones
and tablets.
As we can see SoC ensures better integration and its
heterogeneous structure with different types of processing
units give us better performances. In this paper we will focus
more on interconnection between different units in one single
SoC. In our case it will be communication between DSP and
CPU as well as computational offloading of CPU which
presents one of key aspects in heterogeneous processing
structures.
In second section we describe reasons why SoC are used
and why they present perfect solution for processing large
amount of different types of data. In section 3 we describe
how different processing units inside SoCs are interconnected
and concept of coherent memory with purpose to reach
maximum performances and ensures easier computational
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offload. In section 4 we evaluate what are benefits of fast core
interconnection and task offloading.
II. RELATED WORK
Nowadays electronic devices are pushed in a corner with
large amount of data they need to process. Reason why this
happening is that we demand from them not just to be able to
do some computational work, we demanding from them to be
more similar to us. They are becoming more anthropogenic.
Simple examples will prove these points. Smartphones
need to know how many people are on picture, are they
laughing, and is there any sunlight as well as time and location
of created picture. Another example even more obvious is in
ADAS industry. Vehicles need to know their environment
even more from humans. How many other vehicles are on the
road, they speed, own speed, they need to recognize traffic
signs and pedestrians. They even need to recognize its owner
or parks itself at parking place.
All these inputs are consisting of a large amount of data
which need to be processed at very short time. We don’t speak
about seconds. At speed of 200 km/h in one second we pass
over 50 meters of road. Here we speak about milliseconds and
even less time to collect data, process them and make some
actions.
To be able to process all these data in very short time we
must have all different types of processing units in a system
which behave like one unit. This is the point where silicon
vendors like Qualcomm, TI, Samsung, Intel and many others
started to produce powerful SoCs as a unique solution.
Figure 1
 Qualcomm Snapdragon 820 shown on Figure 1 consists of
general purpose processors, like ARM Cortex, DSP cores
responsible for image processing and algorithms and in charge
of graphic there is GPU.
This concept of general purpose processing unit with
combination of specific designed cores is basic for most of
SoC vendors. Table 1 presents some comparison in SoC
production between two vendors.
Qualcomm Texas Instruments
Vendor
Snapdragon 820 TDA2x
2xArm-Cortext A-15
CPU 4xKryo @ 2200MHz
2xArm-Cortext M-4
Hexagon 680 @
DSP 4x500MHz 2 x C66x @750 MHz
GPU Adreno 530 @ 624 2x SGX544 @ 384
MHz MHz
Table 1
III. MAIN PART
Having such a powerful SoCs, drives us to think how can
we use these resources to gain maximum performances? First
of all we need to know how these different types of cores are
connected and in which way they can interact with each other.
For example if we have a CPU which is running some task
and we want to some part of this task runs on DSP, somehow
data from CPU must be transferred to DSP. In this paper we
present concept of coherent cached memory used in
heterogeneous system architectures knows as HSA [3].
Cache coherency ensures that all cores in our SoC see the
same data [1]. For example some if CPU creates object in its
local cache then when we pass that object to DSP, both of
them must be able to see same data. There are three
mechanisms [2] to maintain coherency:
 Caching disabled
 Software managed coherency
 Hardware managed coherency
Disabled caching is the simplest one but it will downgrade
performances and in reality is not used.
Software managed coherency presents traditional solution
where device driver must clean dirty data from cache and
invalidate old data to enable sharing data with other cores.
Cache cleaning and invalidation needs to be done in a right
time. If done too often it waste its core, if done to infrequently
it will result in stale data. This is presented on Figure 2:
Figure 2
Software managed coherency only takes advantages in one
case where number of cores in system reach hundred and more
[4].
Hardware managed coherency simplifies software. This
means once data is marked as ‘shared’ there is no need to be
updated. Both CPU and DSP see exactly the same value. This
requires a coherent bus protocol which will allow cores to
research cache to see if data is already on chip or need to be
fetched from external memory. Example of full memory
coherency is presented on Figure 3:
Figure 3
With shared virtual memory CPU and DSP can share
physical memory and operate on same virtual memory
address. This means both processors can use same buffer at
same time.
Heterogeneous system architecture always requires
hardware coherency. Scope of shared virtual memory can be
limited to shared buffers. This means only shared buffers will
be visible for both cores, not the whole memory. Full
coherency besides allowing cores to use whole shared memory
also supports atomic operations and synchronization between
cores. HSA also defines different segments of memory like
global, shared and private, but the best thing is that each
address is unique no matter is it private or global.
IV. EVALUATION
Using this powerful mechanism of hardware managed
coherency offloading tasks from one core to another has never
been easier.
Performances also rise to another level. Using same shared
memory cores not need to waste time to clear own cache or to
invalidate data on extern memory. Power consumption is
reduced, what is very significant for mobile and tablet
industry. Offloading tasks to DSPs which has been optimized
for it use less power than general purpose CPU for same task.
Architectures like HSA use new task queuing system and
context-switching, were tasks and threads can be switched
even when threads are in running time.
All these advanced mechanisms ensure maximum SoC
utilization not just from software and hardware developers but
from end users also.
References
[1] Kai Li, Paul Hudak, “Memory coherence in shared virtual memory
systems”, Journal ACM Trasactions on Computer Systems (TOCS)
[2] Sultan Almakdi, Abdulwahab Alazeb, Mohammed Alshehri: "Cache
coherence mechanisms", College of Computer Science and Information
System, Najran University, Najran, Saudi Arabia
[3] Heterogeneous System Architecture Overview, Phil Rogers, HSA
Foundation President
[4] Xiaocheng Zhou, Hu Chen, Sai Luo, Ying Gao, Shoumeng Yan, Wei
Liu, Brian Lewis, Bratin Saha, "A Case for Software Managed
Coherence in Many-core Processors", Intel corporation