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3D Multi-gate Transistors: Concept, Operation,


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Article · March 2015


DOI: 10.17265/2328-2223/2015.01.001

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Journal of Electrical Engineering 3 (2015) 1-14
doi: 10.17265/2328-2223/2015.01.001
D DAVID PUBLISHING

3D Multi-gate Transistors: Concept, Operation, and


Fabrication

Nader Shehata1,2, Abdel-Rahman Gaber3, Ahmed Naguib3, Ayman E. Selmy4, Hossam Hassan3, Ibrahim Shoeer3,
Omar Ahmadien3 and Rewan Nabeel3
1. Department of Engineering Mathematics and Physics, Faculty of Engineering, Alexandria University, Alexandria 21544, Egypt
2. CSNP (Center of Smart Nanotechnology and Photonics), Smart CI Research Center, Alexandria University, Alexandria 21544,
Egypt
3. Department of Electrical Engineering, Faculty of Engineering, Alexandria University, Alexandria 21544, Egypt
4. School of Sciences and Engineering, the American University in Cairo, P.O. Box 74 New Cairo 11835, Egypt

Abstract: The multi-gate transistors such as Fin-FETs, Tri-gate FETs, and Gate-all-around (GAA) FETs are remarkable breakthrough
in the electronic industry. 3D Transistor is taking the place of the conventional 2D planar transistor for many reasons. 3D transistors
afford more scalability, energy efficient performance than planar transistors and increase the control on the channel region to reduce the
short channel effect, which enables us to extend Moore’s law to further extent. In this paper, we will present a review about their
structure, operation, types and fabrication.

Key words: Fin-FET, transistor fabrication.

1. Introduction Transistors have many different types: the planar


transistors, and the non-planar transistors, including
Since the 1970’s, the electronics industry has been
the Multi-gate transistors, called Fin-FET’s, and 3D
subjected to Moore’s law. According to Moore, every
transistors. These transistors employ a single gate
eighteen months approximately the size of the
stacked on top of two vertical gates allowing for
transistor gets reduced to half of its original size. So,
essentially almost three times the surface area for
the number of transistors on the integrated circuit
electrons to travel [1]. FinFET transistors reduce
duplicates. Basically, a transistor is a three-terminal
leakage and consume less power than planar
semiconductor device used to amplify and/or switch
transistors. The additional gate control enables as
electronic signals and power. Either current or voltage
much transistor current flowing as possible when the
between two of the terminals can be controlled by
transistor is in the “on” state (for performance), and
applying an electric current or voltage to the third
nearly zero possible when it is in the “off” state (to
terminal. A transistor can amplify a signal where the
minimize power), and enables the transistor to switch
controlled “output” signal can be higher than the
very quickly between the two states [3]. The acronym
controlling “input” signal. Today, some transistors are
3D here does not refer to images but to physical and
packaged individually, but many more are integrated in
novelty of a design and manufacturing technique, just
electronic chips integrated circuits, IC’s. The transistor
as you can store more cars in a multi-storey garage
is the fundamental building block of modern electronic
than in a flat parking lot, more circuitry can be packed
devices [1, 2].
in three dimensions, but of course with a trade off
Corresponding author: Nader Shehata, assistant professor, with complex design. [1]
Ph.D., research field: nanoelectronics. E-mail:
nader.shehata@alexu.edu.eg.
2 3D Multi-gate Transistors: Concept, Operation, and Fabrication

2. Structure Through keeping the ratio between the effective


channel length and fin width bigger than 0.5, the
Every Silicon wafer consists of hundreds of chips,
channel doping will decrease, impurity in channel will
each chip consists of millions of transistors, and every
decrease, so volume inversion effect will increase and
transistor consists of two regions called “source” and
higher performance will be achieved specially in
“drain”. In Fig. 1, MOSFET (metal oxide
lower bias region [3].
semi-conductor field effect transistor) device is
Multi-gate transistors can be fabricated on SOI
illustrated, in NMOS the two regions are n-type, and
substrate or standard bulk substrate. Fig. 3 shows the
separated by a p-type region called the substrate.
different ways in which the gate electrode can be
PMOS devices are constructed in a different way
wrapped around the channel region of a transistor (a)
where the two regions are p-type and the substrate is
SOI Double-gate FETs: we can notice the “hard
of n-type.
mask”, which is a thick dielectric that prevents the
A thin layer of insulator material covers the region
formation of an inversion channel at the top of the
between the source and the drain, over it, there is a
silicon “fin”. Gate control is exerted on the channel
metal electrode, from which the word “Metal” came in
from the sides of the device; (b) SOI triple-gate
the name “MOSFET” (metal oxide semi-conductor
(tri-gate) MOSFETS: Gate control is exerted on the
field effect transistor), and it is named the “gate”.
channel from three sides of the device (the top, as well
When a voltage is applied at the gate terminal, a
as the left and right sides); (c) SOI -gate MOSFET:
channel of electrons is formed between the source and
Gate control is improved over the tri-gate MOSFET
the drain, so this device acts as a voltage controlled
shown in (b) because the electric field from the sides
current source [2-4].
In tri-gate transistors, there are conducting channels
on the three sides of the vertical fin. It has one gate
electrode on the top and two gate electrodes on the
sides, so the control of the gate increases in a way that
in the “on” state current passes as much as possible,
and in the “off” state current passes is almost zero.
This makes the switching velocity between the two
states higher, which results in a better performance for
the transistor [1]. In addition, the performance
advantage can be provided by the control of the Fig. 1 Schematic diagram of ordinary MOSFET.
effective width of the conducting channel [5]. This
width is greater in 3D tri-gate transistor because it
increases in the third dimension of this structure,
which is the main difference between 2D (Planar) and
3D transistors without increasing the overall footprint
of the transistor as shown in Fig. 2.
By controlling the effective channel length, the
short channel effect can be controlled in 3D transistors
and since the fins are vertical, high packing density
can be achieved by packing transistors close together,
Fig. 2 Channel effective width in planar and multi-gate
and this will result in higher performance [1-3]. transistors.
3D Multi-gate
e Transistors
s: Concept, Operation,
O and
d Fabrication
n 3

reduuced in the SO OI Fin-FET bby reducing thhe tox while inn


the bulk it incrreases with the reduction n of the tox.
Con nsidering thee width of tthe fin in th he threshold,,
volttage decreasees with the inccrease of width in both thee
douuble gate and the tri-gate SSOI Fin-FET, but with lesss
sensitivity in thhe latter duee to the thiird gate thatt
commpromises thee loss of conttrol of the othher two gates..
Also we can finnd that the ttri-gate is beetter than thee
douuble gate SOII Fin-FET in tthe voltage th hreshold, andd
alsoo in the sub-tthreshold swiing where thee tri-gate hass
provved to be moore effective aand reliable [7
7].
Considering
C the DIBL (drain-indu uced barrierr
lowwering) whichh is caused by the traveelling of thee
deppletion regionn from the draain to the chaannel; we cann
findd that the DIBL
D is lowwer in the tri-gate
t bulkk
commpared to double
d gate SOI Fin-FE ET. Anotherr
paraameter affectting the DIB BL is the wid dth. When itt
incrreases, the DIBL alsoo increases with moree
Fig. 3 Differrent types of multi-gate
m transistors.
sensitivity in doouble gate SOI Fin-FET than that inn
of the gate exerts
e some control
c on thhe bottom sidde of tri-g
gate bulk. Onne more elem ment is the chhannel lengthh
the channel;; (d) SOI -gaate MOSFET: Gate controol of whiich when inccreased; the eeffect of the electric fieldd
the bottom ofo the channeel region is better
b than inn the wasshes out so thhe DIBL decrreases a bit. This
T happenss
-gate MOSF FET. The nam mes -gate andd -gate reflectt the in both
b structurres but the ttri-gate showws much lesss
shape of thhe gates; (e) SOI gate-alll-around “GA AA” valuues of DIBL in smaller chhannel lengthss [7].
MOSFET. GateG control is i exerted on the channel fromf The
T last param meter of commparison in thhis section iss
all four sidees of the devvice. In this case, there is no the temperature. It was foundd that the peak k temperaturee
buried oxidee underneath the silicon chhannel. All off the wass lower in thee bulk reachinng 426 K while 448.5 K inn
above deevices weere made using SOI the double gate [7]. Maybe this happen ns due to thee
(silicon-on-iinsulator) substrates,
s SOI substrrates opeening under thhe channel in the bulk [8]. Now we cann
consist of a thin single-ccrystal siliconn layer sittingg on get to the concluusion that tri--gate has an upper
u hand att
top of an inssulator, usuallly silicon diooxide. Multi--gate all the
t points of comparison
c m
mentioned and d it is the keyy
FETs can alsoa be madde with bulkk silicon waafers to future
f reliablee designs [7].
instead of ann SOI substraate, in this caase the channnel is
2.2 Pi Gate and Omega Gatee
connected tot the substrrate silicon without
w insullator
between them m, as shown in Fig. 3f [1--5]. Π-gate
Π and Ω-gate
Ω are tripple gate deviices, with ann
exteended gate electrode, which reduces r thee
2.1 Double Gate
G and Tri--gate
short-channel efffects and inccreases the current
c drive..
Now we get to comppare the characteristics off the Thiis extension blocks the drain electric field liness
double gatee and the trii-gate SOI Fin-FET.
F Talkking fromm reaching thet channel by forming an opposingg
about the thrreshold extraccted using thee constant currrent virttual gate eleectrode. Because of term minating thee
method [6, 7]; it was found that the threshold is draiin electric fiield, the shoort-channel efffect will bee
4 3D Multi-gate
e Transistors
s: Concept, Operation,
O and
d Fabrication
n

reduced, as the extensioon operates as a a virtual back


b so does
d the denssity of the elecctrons in the channel.
gate. This teermination allmost preventts the occurreence Therefore,
T if VG  VD ≤ VTTH, then the channel
c stopss
of DIBL andd eventually the punch thhrough effect [9]. neaar the drain annd this is callled “Pinched off”, but thee
An econom mic advantage of the Pii gate is thaat it devvice still condducts due too the field efffect that thee
simplifies thhe fabricationn process off the compliccated elecctrons are suubjected to in the deplletion regionn
GAA mannufacturing with almoost the same s arouund the draiin junction, so they reacch the drainn
specificationns and nearrly the sam me short-chaannel termminal (Fig. 4cc) [2].
characteristiics [10]. Equation
E Q = CV states that, to achieve a strongg
conntrol of Q by V, the value of C must bee maximized..
3. Operatiion
Onee of the wayys to achievee that is by reducing thee
To underrstand the opperation of any type off the thicckness of thee dielectric llayer separatting the twoo
multi-gate transistors
t w must firsst have a brief
we b plattes, the capaccitance betweeen two platees is given byy
introductionn about the operation
o of traditional
t pllanar (ε.A
A)/t where “ε”” is the dielecttric constant—
—permittivityy,
MOSFET. “A”” is the area of
o each platee, and “t” is thet dielectricc
thicckness. The main
m goal heree is to lower the thicknesss
3.1 Planar MOSFET
M
“t” to increase the capacitaance, and thee acceleratedd
Planar MOSFET
M connsists of gatte, insulator and advvancement in silicon fabriication techn nology makess
substrate (Fig. 1). If we applied posiitive potentiaal on thatt goal easier [2].
[
the gate, it reepels the posiitive charges (holes in NM
MOS) As
A the thickkness of thhe oxide in ncreases, thee
of the p-typpe substrate, so this regioon is depleted of capacitance betw ween the gatee and the siliccon substratee
carriers andd remains with
w the fixedd negative ions.
i decreases. Thus, from Q = C CV, we note that a givenn
After we increase thee voltage, negative
n carrriers volttage results in less chargee on the gate and hence a
(electrons inn NMOS) aree attracted froom this substtrate low
wer electron density
d in thee channel. Therefore, thee
to the region underneeath the inssulator mateerial, devvice suffers frrom a higherr on resistancce, producingg
forming a channel
c (chaannel inversioon) between the lesss drain currennt for a givenn gate and drrain voltages..
source and the
t drain. If a voltage is applied betw
ween Forr this reasonn, the semiiconductor industry i hass
the source and
a the drainn, current floows. The volltage conntinued to redduce the gate ooxide thickneess [2].
VD controls the
t amount of
o this currentt [2-4]. 3.2 Multi-gate MOSFET
M
To operaate this deviice, two pottentials mustt be
T operationn of multi-gaate FETs shares the samee
The
applied, onee at the gate node
n (VG) annd another onne at
the drain noode (VD). If VG < VTH (w
where VTH iss the
threshold vooltage which is the least voltage
v needeed to
create a chhannel), thenn no channell exists and the
device is offf. In this casee ID = 0 regarddless of the value
v
of VD. Whenn VG > VTH, thhen ID > 0 (Fiigs. 4a-b) [2]..
If VD rem
mains higherr than VS, then
t the volltage
increases as we go from the
t source to the drain at each
e
point away along the channel with reespect to ground.
As the gaate voltage is constantt, the potenntial
difference between the gate and the innsulator interrface
decreases allong the x-axxis as we appproach the drrain, Fig.. 4 Operation
n of planar MO
OSFET.
3D Multi-gate Transistors: Concept, Operation, and Fabrication 5

idea as planar MOSFET, as we can consider it an through the depletion region affects the current
advanced version of traditional MOSFET, but passing through the channel and the drain voltage
minimization of the transistor has some drawbacks, becomes the dominant voltage affecting the current.
which affect the functionality of the transistor. Gate Punch through can be minimized by several methods,
leakage current, tunneling leakage of carriers at high the first method is decreasing the thickness of the
doping levels, rising power dissipation and short oxide, which provides more control for the gate
channel effect are some examples to these drawbacks voltage over the channel current, the second method is
as a result of the minimization process. increasing the substrate doping, which prevents the
3.2.1 Short Channel Effects merging of the depletion regions of the source and the
Short channel effect is the most important drawback. drain, and other method is using shallower junctions
It results from some consequences: the presence of a which confines the depletion regions making the
depletion region between the source and the drain linkage more difficult [11].
results in the presence of an electric field flowing in Surface scattering: It is the degradation in the
the depletion region. This depletion region is created surface mobility of the channel carriers to half of that
by the source and drain junctions occurring to of the bulk region due to the vertical component of the
shorten the effective channel length. This electric field electric field causing the collision with the interfacing
affects the carriers flowing in the channel decreasing surface between the channel and the bulk region [11].
the gate control on them. The gate control is also 3.2.2 Relation between Threshold Voltage and
influenced by the drain voltage and the distance Channel Length
between the source and the drain, as the drain voltage The threshold voltage is the least gate-to-source
increases the effect of the electric field increases [1-5]. voltage capable of creating a conducting channel by
The main consequences of Short Channel effect as attracting bulk charges that causes channel inversion
follows. [2]. In small dimensioned MOSFETs, the actual
Velocity saturation: As we go smaller in size, the threshold voltage is less than that calculated value
size of all parts in the transistor decreases including estimated by the standard equation, because the
the length of the channel, which increases the electric equations assume that all the bulk charges attracted to
field due to the inversely proportional relation of the generate the channel are due to the gate voltage only,
length and the electric field E = -dv/dx. When the while some charges are attracted due the electric field
electric field increases the velocity of carriers generated by the PN junction charges at the source
increases according to the relation between electric and the drain [11].
field and charged particles V = μ*E, but this velocity Another factor affecting the threshold voltage is hot
will not increase infinitely, and will actually stop carriers degradation which means that there are high
increasing at a specific value which is called energy electrons penetrating the oxide and getting
(saturation velocity) because of increasing the rate of trapped and accumulated there, decreasing the device
collision between carriers. This effect in velocity will characteristics by increasing the channel field thus
result in channel mobility degradation, which will decreasing the threshold voltage [11].
affect the flow of current in the channel region It was found that in tri-gate NMOS 22 nm
decreasing the performance of the transistor [1-11]. technology that the threshold voltage is less than that
Punch through: It is the merging between the of tri-gate NMOS 32 nm technology, it also has a
depletion regions of the drain and the source into a faster increase with the drain voltage because it
single depletion region [12]. The field flowing provides the gate with more control [11].
6 3D Multi-gate Transistors: Concept, Operation, and Fabrication

3.2.3 Electrostatic Control of Channel confinement effects if the wire was large enough, but
A MOSFET device is free of short-channel effects in smaller section FETs, this confinement causes
if the gate length is at least 4 to 6 times larger than the electron distribution that differs from the predicted
natural length of the device. λ is the natural length that one from classical theory [16].
refers to the potential distribution of the whole In the planar or wider multi-gate FETs, inversion
structure [5]. It represents the field lines penetration layers are localized at the surface of the silicon film,
from the source and the drain in the channel region. but in narrower wires it can be found in the center of
From Poisson’s equation, the natural length is given the film. This causes the phenomenon of “volume
by: inversion” which affects the mobility and threshold
voltage behaviors [5-16]. Volume inversion is a
 si
n  tox t si (1) phenomenon that happens to very thin film multi-gate
n ox
SOI MOSFETs, in this case the inversion carriers are
where, “n” is the equivalent number of gates (n = 2 for not confined near the surface of the film, but at its
a double gate device, n = 3 for a tri-gate device, n = 4 center [17]. The carriers concentration profile at VG =
for a GAA transistor), εsi is the electrical permittivity VTH + 0.7 in tri-gate SOI transistors in strong inversion
of the channel, εox is the electrical permittivity of the for different square cross sections [15, 16].
gate dielectric, tsi is the film thickness and tox is the Confinement raises the formation of sub-bands. As
gate dielectric thickness [13, 14]. the gate voltage increases, the electron concentration
3.2.4 Quantum Effects increases, so a larger number of sub-bands become
The continuous decrease of the device dimensions populated. All these factors lead to inter-sub-band
leads to the appearance of Quantum effects, like scattering between electrons from different energy
Quantum confinement, volume inversion, and current sub-bands [15]. Inter-sub-band scattering increases
oscillation, which introduces new challenges in device with each new sub-band that becomes populated,
physics and modeling [15]. Carriers in narrow triple or which results in mobility reduction. Therefore,
quadruple FETs are confined in two directions (y and oscillations of the drain current occur, when the gate
z), which are perpendicular to the direction of carriers voltage is increased. Current oscillations can be
flow x, as shown in Fig. 5. We can neglect the observed as a function of gate voltage, when the drain

Fig. 5 Element volume in a channel region.


3D Multi-gate Transistors: Concept, Operation, and Fabrication 7

voltage is not significantly larger than the energy material. Because poly-silicon is a semiconductor, its
separation between sub-bands, which is expressed by work function can be modulated by adjusting the type
“ΔE” divided by the electron charge “q” [15-19]. and level of doping [23], the silicon dioxide -SiO2-
3.2.5 Tri-gate Impact on I-V Characteristics interface has been well studied and is known to have
For large dimensions (as in 90 nm technology), the relatively few defects. By contrast, many
ratio between the drain to source current and the simple metal-insulator interfaces contain significant levels of
gate transistor value is 1.1:1, while for smaller defects, which can lead to Fermi level pinning,
dimensions (as in 22.5 technology) the ratio between charging, or other phenomena that ultimately degrade
them is 1.44:1 [20, 21]. the device performance, fabrication processes where
A new revolutionary speed and gain performance the initial doping requires very high temperature
introduced at FPGAs based on 22 nm 3D tri-gate annealing. Metal gates would melt under such
technology. These FPGAs will operate 37% faster at conditions whereas poly-silicon would not. Using
low power compared to 32 nm planar FPGAs, and will poly-silicon paved the way for a one-step process of
save more than 50% of the power consumed, which etching the gates compared elaborating multi-steps that
makes them suitable in handheld devices as they can we see today in metal-gate processes [24].
operate at less energy, but would still have poor gate While poly-silicon gates have been the de facto
delay at low voltage [3]. That’s how the problem of standard for the last twenty years, however, they do
leakage current flowing through the channel when the have some problems, which have led to their likely
gate voltage equals zero seems to be solved; as lower future replacement by metal gates. Poly-silicon is not a
amount of it flows through the channel of the tri-gate great conductor, which reduces the signal propagation
transistors than that flowing in planar transistors. The speed through the material. The resistivity can be
dynamic power is reduced with reducing the transistor lowered by increasing the level of doping, but even
channel dimensions, which means that the technology highly doped poly-silicon is not as conductive as most
of 3D tri-gate improves the control over static and metals. To improve conductivity further, sometimes a
active power dissipations of FPGAs [3]. high-temperature metal such as tungsten, titanium,
cobalt, and more recently nickel is alloyed with the top
4. Fabrication layers of the poly-silicon. Such a blended material is
4.1 Fabrication Materials and Technology called silicide. The silicide-poly-silicon combination
has better electrical properties than poly-silicon alone
A metal gate, in the context of a lateral metal-oxide- and still does not melt in subsequent processing. Also
semiconductor MOS stack, is just that the gate material the threshold voltage is not significantly higher than
is made from a metal. The primary criterion for the gate with poly-silicon alone, because the silicide material is
material is that it is a good conductor. For decades the not near the channel [25]. From the 45 nm node
industry has been moving away from metal (most onwards, the metal gate technology returns, together
typically aluminum evaporated in a vacuum chamber with the use of high-dielectric (high-k) materials,
onto the wafer surface) being used as the gate material pioneered by Intel developments.
in the MOS stack, due to fabrication complications [22]. One of the problems in the planar MOSFET was the
A material called poly-silicon was used to replace quantum tunneling effect when reducing the insulator
aluminum because the threshold voltage and the drain (normally SiO2). One of the solutions applied in the
to source on-current is modified by the work function tri-gate manufacturing was using high-k material other
difference between the gate material and channel than SiO2 whose k = 3.9 but using high-k materials with
8 3D Multi-gate Transistors: Concept, Operation, and Fabrication

poly-Si had two effects. Firstly, high-k dielectrics and The photoresist is then exposed to ultraviolet light.
poly-Si are incompatible due to the Fermi level pinning The exposed areas become soluble and are no longer
at the poly-Si/high-k interface [26], which causes high resisting the etching chemicals or etching solvents. To
threshold voltages in MOSFET transistors. Secondly, control the soluble areas over the surface, masks are
the coupling of low surface optical phonon modes, used. Those masks cover some areas of the photoresist
which results from the polarization of high-k dielectric, and leave other areas uncovered. Thus, when the mask
reduces the electron mobility [27]. This was partly on top is exposed to UV light, areas which are covered
solved by metal/high-k junction at the gate as the metal by the opaque features on the mask are shielded and
prevents the coupling of the phonons to the channel insoluble, while other uncovered areas (which UV
under certain conditions improving the mobility [28, passes through) become soluble (Fig. 6c).
29] like Hafnium dioxide -HfO2- high-k/TiN metal There are two types of photoresists: positive and
gate but still the problem of high threshold voltage, negative photoresists. Positive photoresists are initially
also it requires definite type of n-channel and p-channel insoluble and become soluble after UV exposure.
materials of certain work function for high Negative photoresists are initially soluble and become
performance CMOS logic [30]. Now Intel has insoluble after UV exposure. Negative photoresists are
engineered n-type and p-type metal electrodes that more sensitive to light, but their photolithographic
have the correct work functions on the high- K for resolution is not as high as that of the positive
high-performance CMOS [27, 31]. photoresists. Therefore, negative photoresists are used
4.2 Fabrication Process Overview less commonly in the manufacturing of high-density
integrated circuits.
In general, both planar and multi-gate transistors After the exposure step, the exposed areas of the
share same fabrication processes, but the main photoresist can be easily removed by a solvent (chemical
difference is how these steps are applied to produce a reaction happens), then the silicon oxide areas that are
specific device with its specifications, like length, not covered by the insoluble/hardened photoresist can
width, etc. The process steps for devices fabrication be etched (removed) by a chemical solvent, such as
will be briefly explained, and then there will be a focus Hydrofluoric acid. After etching the silicon dioxide by a
on the main types of multi-gate transistor. solvent, an access called “window” becomes available
4.2.1 Planar MOSFET directly to the silicon substrate (Figs. 6d-e).
Device fabrication process has some major steps that The remaining photo-resistive areas can be easily
are generally needed to manufacture a transistor device, stripped by another solvent leaving the rest of the
whether planar or 3D multi-gate; but in multi-gate, patterned silicon oxide feature over the silicon
these steps are extended much more to achieve the new substrate (Fig. 6f).
design of it. Starting by the planar MOS transistor Then, the resulting surface is covered by a thin high
fabrication, detailed process steps are shown in Fig. 6 quality oxide. This oxide will eventually form the gate
[32, 33]. oxide (insulator) for this MOS transistor. After that,
The process starts with a silicon substrate that faces another layer of poly-silicon (metal) is used on top of
thermal oxidation to end up with a thin SiO2 layer. The the previous Gate thin high quality oxide (Figs. 6g-h),
entire oxide surface is covered with a layer of a then the gate electrode is made according to the desired
photo-resistive material, essentially light sensitive specifications and dimensions, so the poly-silicon is
called photoresist. The photoresist is initially insoluble patterned and etched away in the sub-sequence of steps
during the development (Figs. 6a-b). shown in Figs. 6i-l.
3D Multi-gate
e Transistors
s: Concept, Operation,
O and
d Fabrication
n 9

Fig. 6 Fabriication processses of planar trransistor.

Afterwardds, the area of the thin gate oxide not In


n diffusion, the unproteccted part of the wafer iss
covered by the poly-silicon is remooved and etcched expposed to an intensive source of opposite-type
o e
away, givingg us a direct clean
c access to
t the bare sillicon imppurity. Ion im mplantation accelerates the impurityy
substrate where
w the dooping will taake place. After
A ionss to a very higgh level then implants the ions into thee
etching the thin
t gate oxidde around the area uncovvered piecce of wafer, inn other wordss, a beam of opposite-type
o e
by the poly--silicon, the entire
e surfacee is highly dooped doppant impurity is to be shot into the wafer. The resultss
with Si-substrate o
opposite-type concentraation of such
s doping here
h are the m most importantt terminals off
impurities. There
T are twoo ways of dopping: diffusioon or the MOS transisttor; the sourcce and the drain, colored inn
ion-implantaation. orannge in Fig. 122m.
10 3D Multi-gate
e Transistors
s: Concept, Operation,
O and
d Fabrication
n

After formming the corrrect desired source and draind In


nsulator layeers are used aat the beginniing as shownn
specificationns, the wholle surface iss covered byy an in Figs.
F 7a-d. Beginning
B w
with Silicon on insulatorr
insulating laayer of silicon dioxide. Then, the oxide ucture is conssidered a step that is comm
stru monly used inn
layer is patterned
p and etched -using
- UV and all kinds of Muulti-Gate FETs. Now coating with a
lithography as before- too form conneccting window ws to positive photo-reesistive layerr takes place and applyingg
the source annd the drain to
t form the MOSFET
M circuuitry UVV exposure, thhen chemicallly removing the solvablee
(Figs. 6n andd 6o). areaas resultant of the lithograaphy UV expo osure.
Finally, the
t surface is covered with evaporrated Afterwards,
A a
another mical solvent is applied too
chem
aluminum too form the deevice interconnnects and metalm the surface of thee wafer to etcch the areas no
ot covered byy
windows, thhen the alumiinum surface is patterned and the photoresist, and
a then etch the rest of thee photoresist..
etched to complete
c thee fabrication process of this So this
t stage endds with the strructure show wn in Fig. 7e.
planar MOS SFET (Fig. 6pp). Then
T coating the
t previous sstructure with h poly-siliconn
4.2.2 Tri-gate FET takees place to foorm the gate eelectrode, passsing throughh
The fabriccation processs of multi-gaate FETs andd the a pllanarization step,
s and endiing with whaat is shown inn
planar MOS SFETs are somehow
s milar in general.
sim Fig. 7f.
Below is thee explanationn of some typpes of Multi-G Gate Now
N a phhotoresist laayer is ap
pplied, thenn
Transistor. Starting
S by thhe tri-gate Trransistor, the SOI lithographing is masked oveer it, and ch
hemically thee
(Silicon-On--Insulator) coonfiguration is usually beegun vent is removved by a reacctant that only
solv y reacts withh
with to reduuce the parasitic capacitannces. Sometim mes, the unprotected layer of gatee electrode. The
T result is a
SOS (Silicoon-On-Sapphiire) is used but b this happpens SOII Tri-Gate FET.
F Afterwaards, some etching
e takess
mostly in eleectronic devicces with RF constrains.
c placce to removee the areas unncovered by the insolublee

Fig. 7 Fabriication processses of tri-gate transistor.


t
3D Multi-gate
e Transistors
s: Concept, Operation,
O and
d Fabrication
n 11

photoresist after the UV U exposuree, and then the posed and theen the resultaant areas nott covered byy
exp
remaining of the photoressist itself is ettched, which was pho
otoresist are etched (Fig. 8e), then the rest of thee
covering thee gate area, ennding with thee structure shhown pho
otoresist is rem
moved (Fig. 88f).
in Figs. 7g-hh. The
T surface iss covered witth poly-silicon
n to form thee
Finally, doping
d proceess takes plaace to shape the gatee electrode then
t it is paatterned and etched. Thee
source and drain
d fins as shown
s in Fig.. 7i. dop
ping is made with
w oppositee type materiaal to form thee
4.2.3 Douuble-Gate FET T finaal double gatee FET as in F
Fig. 8g.
A simple SOI structuree begins this process
p also (Fig.
( 4.2.4
4 Ω-Gate FET
F
8a). The whhole surface is
i covered with
w a photoreesist, Starting
S from
m the stage of the doub
ble-gate FET
T
which is preeferred to bee positive. Exxposure withh the prev
viously explaained, where w
we have patteerned, etchedd
desired massk that matchhes device dimensions
d takes awaay and reacheed out to thee structure sh
hown in Figs..
place, then etching the soluble phootoresist thenn the 9a-cc, then coatedd the surface with poly-sillicon to form
m
underlying silicon
s (areass uncovered), then etchingg the the gate electrodde and patternning it with a mask
m -havingg
unneeded phhotoresist thhat was not exposed.
e Thiis is feattures of the desired gate length- passing throughh
shown in Figgs. 8b-c. etch
hing away thhe soluble phhotoresist -gaate electrodee
The wholle surface iss covered aggain with sillicon areaa not covereed by it- andd finally etch
hing the restt
doped whethher P or N too form the finns for source and inso
oluble photorresist.
drain in Fiig. 8d. The new photo-resistive areea is Again,
A we willl cover the w
whole surface with positivee

Fig. 8 Fabriication processses of double gate


g transistor.
12 3D Multi-gate
e Transistors
s: Concept, Operation,
O and
d Fabrication
n

Fig. 9 Fabriication processses of gate tran


nsistor.

photoresist, then removee the photoreesist stack usingu 9h and


a 9i.
planarizationn techniques.. CMP (chem mical mechannical Now
N we havee to cover thee surface withh poly-siliconn
planarizationn) shown in Figs. 9d--e is a fam mous to create
c the resst of the gatee electrode ov
ver the otherr
planarizationn method in semiconnductor devvices sidees of the finns. CMP is used to plaaten the gatee
fabrication. elecctrode surfacee to make it rready for expo
osure.
Patterningg process theen takes placee to result inn the The
T gate elecctrode now iss formed arou und the threee
structure shoown in Figs. 9f-g, the resuultant photoresist sidees of the fins and the photoresist partss still exist ass
areas work along
a with thhe oxide bar between them m as shown in Figs. 9j-l.
9
fins’ basemeents. These areas
a will bee removed inn the Finally,
F remoove the insoluuble photo-reesistive partss
final step. by chemical etcching to end up with the final devicee
A silicon doped material is then coated
c abovee the shown in Fig. 9m ready ffor operation n as Ω -gatee
surface thenn we apply planarization
p to the surfacce to FinFFET.
flatten it. Patterning andd etching thee silicon surrface
5. Conclusion
C ns
processes taake place afteer planarizatiion to createe the
fins, the source and the drrain. The fin is resting on both
b Inn this paperr, a detailed review on the differentt
silicon oxidee and the phottoresist parts as shown in Figs.
F cateegories of 3D
D Multi-gate trransistors waas introduced,,
3D Multi-gate Transistors: Concept, Operation, and Fabrication 13

including the structure, operation, and fabrication. On Students Conference on Engineering and Systems (SCES),
Allahabad, India.
account of the continuous advancement of VLSI
[8] Tsividis, Y. 1999. Operation and Modeling of the MOS
designs and architectures, and the pursuit of more Transistor: Oxford University Press.
speed and ultra-low power electronics chips, the [9] Park, J. T., and Colinge, J. 2002. “Multiple-Gate SOI
traditional planar MOSFET device became the MOSFETS: Device Design Guidelines.” IEEE
Transactions on Electron Devices 49 (12): 2222-9.
bottleneck of the growing demand for larger Systems
[10] Park, J. T., Colinge, J., and Diaz C. H. 2001. “Pi-Gate
on Chip. The drawback of the planar transistors was SOI MOSFET.” IEEE Electron Device Letters 22 (8):
illustrated, like the short channel effect when 405-6.
decreasing the channel length of the device. The idea of [11] D’Agostino, F., and Quercia, D., Short-Channel Effects in
MOSFETs. Introduction to VLSI Design (EECS 467),
Multi-gate FETs became the ideal solution to the
2000.
negative effects of channel decreasing of planar [12] Zeghbroeck, B. V. 2004. Principles of Semiconductor
MOSFET. The different structures and their fabrication Devices. Colarado University.
techniques of Multi-gate devices provide chip makers [13] Yan, R. H., Ourmazd, A., and Lee, K. F. 1992. “Scaling
the Si MOSFET: From Bulk to SOI to Bulk.” IEEE
with devices with small channel length, and faster
Transactions on Electron Devices 39 (7): 1704-10.
switching efficient speed operation, and lower power [14] Kuhn, K. J. 2012. “Considerations for Ultimate CMOS
consumption, due to the much better control over the Scaling.” IEEE Trans. Electron Devices 59 (7): 1813-28.
device channel. Hereunder, it solved the problems of [15] Colinge, J. P. 2007. “Quantum-Wire Effects in Trigate
SOI MOSFETS.” Solid-State Electronics 51 (9): 1153-60.
short channel effects, and gave us a chance to decrease
[16] Colinge, J. P. 2014. “Multigate Transistors: Pushing
the device size, and optimize the usage of die size in Moore’s Law to the Limit.” Presented at 2014
chip fabrication, or even give designer the promise for International Conference on Simulation of Semiconductor
more functionality over same chip size. Processes and Devices (SISPAD), Yokohama, Japan.
[17] Balestra, F., Cristoloveanu, S., Benachir, M., Brini, J., and
References Elewa, T. 1987. “Double-Gate Silicon-Oninsulator
Transistor with Volume Inversion: A New Device with
[1] Ferain, I., Colinge, C. A., and Colinge, J. P. 2011.
Greatly Enhanced Performance.” IEEE Electron Device
“Multigate Transistors as the Future of Classical
Letters 8 (9): 410-2.
Metal-Oxide-Semiconductor Field-Effect Transistors.” [18] Colinge, J. P. 2008. “The New Generation of SOI
Nature 479 (7373): 310-6. MOSFETS.” Romaniam Journal Information Science and
[2] Razavi, B. 2008. Fundamentals of Microelectronics: BR Technology 11 (1): 3-15.
Wiley. [19] Colinge, J., Quinn A. J., Floyd, L., Redmond, G.,
[3] Bhole, M., Kurude, A., and Pawar, S. 2013. “3D Tri-gate Alderman, J. C., Xiong, W., Cleavelin, C. R., Schulz, T.,
Transistor Technology and Next Generation FPGAs.” Schruefer, K., Knoblinger, G. et al. 2006.
International Journal of Engineering Sciences and “Low-Temperature Electron Mobility in Tri-gate SOI
Research Technology 2: 2670-5. MOSFETs.” IEEE Electron Device Letters 27 (2): 120-2.
[4] Rabaey, J. M., Chandrakasan, A. P., and Nikolic, B. 2002. [20] COMSOL Multiphysics Software Site [Online]. Available:
Digital Integrated Circuits, Vol. 2: Prentice Hall www.comsol.com.
Englewood Cliffs. [21] Srivastava, V. M., and Singh, S. P. 2012. “Analysis and
[5] Colinge, J. P. 2013. “3D Transistors.” Presented at 2013 Design of Tri-gate MOSFET with High Dielectrics Gate.”
International Symposium on VLSI Technology, Systems, International Journal of Intelligent Systems and
and Applications (VLSI-TSA), Hsinchu, Taiwan. Applications 4 (5): 16.
[6] Conde, A. O., S´anchez, F. J. G., Liou, J. J., Cerdeira, A., [22] Kumar, V., and Agarwal, S. K. 1998. Physics of
Estrada, M., and Yue, Y. 2002. “A Review of Recent Semiconductor Devices. Vol. 1, Narosa.
Mosfet Threshold Voltage Extraction Methods.” [23] Baliga, B. J. 2010. Fundamentals of Power
Microelectronics Reliability 42 (4): 583-96. Semiconductor Devices. Springer Science & Business
[7] Singhal, S., Kumar, S., Upadhyay, S., and Nagaria, R. K. Media.
2013. “Comparative Study of Double Gate SOI Finfet and [24] Long, R. D., and McIntyre, P. C. 2012. “Surface
Trigate Bulk MOSFET Structures.” Presented at 2013 Preparation and Deposited Gate Oxides for Gallium
14 3D Multi-gate Transistors: Concept, Operation, and Fabrication

Nitride Based Metal Oxide Semiconductor Devices.” [29] Doyle, B., Boyanov, B., Datta, S., Doczy, M., Hareland,
Materials 5 (7): 1297-335. S., Jin, B., Kavalieros, J., Linton, T., Rios, R., and Chau,
[25] Vasileska, D., and Goodnick, S. M. 2005. “Computational R. 2003. “Tri-gate Fully-Depleted CMOS Transistors:
Electronics.” Synthesis Lectures on Computational Fabrication, Design and Layout.” In Proceedings of 2003
Electromagnetics, 1 (1):1-216. Symposium on VLSI Technology, 133-4.
[26] Hobbs, C., Fonseca, L., Knizhnik, A., Dhandapani, V., [30] Lu, Q., Lin, R., Ranade, P., King, T. J., and Hu, C. 2001.
Samavedam, S. B., Taylor, W. J., Grant, J. M., Dip, L. G., “Metal Gate Work Function Adjustment for Future CMOS
Triyoso, D. H., Hegde, R. I., Gilmer, D. C. , Garcia, R., Technology.” In Proceedings of 2001 Symposium on VLSI
Roan, D., Lovejoy, M. L., Rai, R. S., Hebert, E. A., Tseng, Technology, 45-6.
H. H., Anderson, S. H., White, B. E., and Tobin, P. J. 2003. [31] Cheng, K., Khakifirooz, A., Kulkarni, P., Ponoth, S., Kuss,
“Fermi Level Pinning at the Poly-Si/Metal Oxide J., Shahrjerdi, D., Edge, L. F., Kimball, A.,
Interface.” In Proceedings of 2003 Symp. VLSI Tech. Dig, Kanakasabapathy, S., Xiu, K., et al. 2009. “Extremely
9-10. Thin SOI (ETSOI) CMOS with Record Low Variability
[27] Chau, R. “Advanced Metal Gate/High-K Dielectric Stacks for Low Power System-On-Chip Applications.” Presented
For High-Performance CMOS Transistors.” Logic at 2009 IEEE International Electron Devices Meeting
Technology Development, Intel Corporation. (IEDM), Baltimore, USA.
[28] Fischetti, M. V., Neumayer, D. A., and Cartier, E. A. 2001. [32] Kang, S. M., and Leblebici, Y. 2002. CMOS Digital
“Effective Electron Mobility in Si Inversion Layers in Integrated Circuits Analysis & Design. New York:
Metal-Oxide-Semiconductor Systems with a McGraw-Hill, Inc.
High-Insulator: The Role of Remote Phonon Scattering.” [33] Colinge, J. P., et al. 2008. FinFETs and Other Multi-gate
Journal of Applied Physics 90 (9): 4587-608. Transistors. Springer.

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