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Abstract—Short-circuit detection is a fundamental function of IGBTs. Thus, the minimum detection delay is limited to about
most inverters. In this paper, two new fast and easily implementable 1 µs (depending on the turn-on time of the device). The short-
short-circuit detection approaches are presented. The first one of- circuit withstand time of most commercial Si-based IGBTs is
fers a significantly accelerated desaturation detection. The second
one allows a full inverter to be protected by only one short-circuit between 5 and 10 µs. Therefore, the common desaturation de-
detection circuit. Both approaches are verified by simulations and tection is suitable. However, the short-circuit withstand time is
hardware tests. a design parameter for power semiconductors. It depends on the
Index Terms—Desaturation detection, fault analysis, insulated-
chip volume and the desaturation current. The progress in chip
gate bipolar transistor (IGBT), short circuit. design and chip manufacturing leads to thinner chips. Further-
more, the desaturation current depends on the gate channel. An
optimized gate channel for reduced conducting losses in new
I. INTRODUCTION chip technologies leads to a higher desaturation current as well.
HORT-CIRCUIT fault detection circuits are used in many Due to the smaller chip volume and the increased desaturation
S power electronics applications to detect dc-link short cir-
cuits caused by device failure. They are necessary to prevent fur-
current, short-circuit robustness becomes more critical and the
acquired withstand time limits a further reduction of conduction
ther damage to the inverter. Furthermore, in redundant systems losses for new chips. Thus, shorter response time could enable
a short circuit can affect other redundant parts of the system. shorter withstand time and therefore further reduction of the
Therefore, the fault must be detected and cleared. The main de- conduction losses [3].
tection circuit requirement is a fast and reliable fault detection. In [4], a fast desaturation detection is presented. The paper
Moreover, the circuit should be easily implementable at a low focuses on the design issues for desaturation detection at fast
price. switching SiC devices and presents a concept for solving them.
The short-circuit fault can be divided into two different types The fact that in the suggested paper a faster short-circuit detec-
of faults. The first one is the hard switching fault (HSF). It tion is realized results from the devices used. Due to the faster
appears when a device is turned ON while the other device of switching of the SiC devices in comparison to Si devices, a
the half-bridge has already been shorted by a fault. The other shorter blanking time is possible but it must still be longer than
one—namely fault under load (FUL)—appears when a device the maximum fall time of the blocking voltage. Therefore, the
is shorted by a fault while the other device of the half-bridge approach cannot be used to accelerate the desaturation detection
has already been turned ON. Both types must be detected. The for Si devices.
most common detection circuit is the desaturation detection cir- Faster short-circuit detection for Si devices can be realized
cuit. But there are also other possibilities known. An overview by monitoring the gate–emitter voltage vGE . HSF can be de-
is given in [1] and [2]. The disadvantage of the desaturation de- tected by identifying the missing Miller plateau [5]–[7]. In ad-
tection is the blanking time which is necessary after turn-on to dition, a FUL causes a gate voltage peak which can be detected
avoid false detections. This paper focuses on silicon (Si)-based [8], [9]. Another possibility for fast fault detection is to detect
the current transient under short-circuit conditions (di/dt). For
Manuscript received May 20, 2016; revised August 10, 2016; accepted Oc- this purpose, the voltage at the parasitic inductor between power
tober 3, 2016. Date of publication October 19, 2016; date of current version emitter and auxiliary emitter can be used [10], [11]. A combi-
May 18, 2017. Paper 2016-PEDCC-0451.R1, presented at the 2015 IEEE En-
ergy Conversion Congress and Exposition, Montreal, QC, Canada, Sep. 20–24, nation of these approaches is given in [3]. Both approaches are
and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLI- suited to detect a short circuit in a few hundred nanoseconds, but
CATIONS by the Power Electronic Devices and Components Committee of the both systems can only detect the fault in the small time period
IEEE Industry Applications Society. This work was supported by the German
Federal Ministry for Economic Affairs and Energy under Project FuSy (FKZ: during which the fault appears. If this period is missed, e.g., by
01MY12007A). an error in the detection system, the fault cannot be detected
The authors are with the Institute for Drive Systems and Power Elec- anymore. Furthermore, slow rising fault currents cannot be de-
tronics, Leibniz Universität Hannover, Hannover 30167, Germany (e-mail:
tobias.krone@ial.uni-hannover.de; xuchengzhi3@126.com; mertens@ial. tected. To avoid this, the first proposed approach combines the
uni-hannover.de). missing Miller plateau detection and the desaturation detection.
Color versions of one or more of the figures in this paper are available online In this way, no additional blanking time is necessary and the
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2016.2618785 desaturation detection can be accelerated [12].
0093-9994 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
2872 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 53, NO. 3, MAY/JUNE 2017
the gate–emitter voltage directly rises to the gate driver supply VCED, m ax ), V1 must be lower or equal to the highest voltage
voltage (VGE = VCC ). Under this condition, V1, HSF (4) must under normal condition during switching [V1, norm al (3)]. From
exceed the compared voltage. Therefore, the compared voltage this, the maximum R1 can be identified
must be chosen between the lowest voltage under fault con-
dition V1, HSF and the highest voltage under normal condition VM iller, m ax VCED, desat − VCED, m ax VCC
R1 ≤ R3 . (8)
V1, norm al VCC2 −V
M iller, m ax VCC
TABLE I
DESIGN PARAMETER AND COMPONENTS’ VALUES OF THE ACCELERATED
DESATURATION DETECTION (T 1 AND R 4 NOT APPLIED)
TABLE II
DESIGN PARAMETER AND COMPONENTS’ VALUES OF THE EXTENDED
ACCELERATED DESATURATION DETECTION (T 1 AND R 4 APPLIED)
VC C 15 V VC E D , d esa t 8V Vco m p 7V
VM ille r, m ax 12 V VC E D , m a x 4V R1 740 Ω
R2 11.42 kΩ R3 10 kΩ R4 2.9 kΩ
C1 10 pF td e la y 1 µs
Fig. 3. Simulation results of the accelerated desaturation detection circuit (T 1
and R 4 not applied).
D. Test Results
The test results for the accelerated desaturation detection at a
low-side IGBT are given in Fig. 13. The results for vGE and v1
are close to the simulation results. vout is the output signal of the
comparator. It shows that both faults are detected (blue and red
circles) and no false detection occurs under normal switching Fig. 10. Result of the PCB Rogowski coil calibration.
2876 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 53, NO. 3, MAY/JUNE 2017
A. Circuit Design
For the design of the dc-link voltage transient detection cir-
cuit, it is assumed that CDC C1 . Thus, the current through
the detection circuit can be neglected. In this way, the current
through the dc-link capacitor is approximately the difference
Fig. 12. General idea of dc-link voltage transient detection. between input and output currents of the dc-link capacitor
iDC = iDC, out − iDC, in . (9)
conditions. Furthermore, for the HSF the compared voltage is
exceeded in less than 250 ns and the fault is detected by the First measurements showed that the parasitic inductance and
comparator in about 340 ns. parasitic resistance of the dc-link capacitors (see Fig. 11) cannot
In the simulation, the compared voltage is exceeded in 200 ns. be neglected for the circuit consideration. For this reason, they
The 50 ns difference between simulation and experimental test must be considered in the transfer function of the dc-link voltage
results from the input capacitance of the comparator, which VDC (s) with the capacitor current as the input state
is not included in the simulated circuit. Instead, an optimized
capacitance C1 is used. In the test setup, the input capacitance of 1
VDC (s) = − + RDC + LDC s IDC (s). (10)
the comparator is slightly higher than the simulated capacitance CDC s
C1 . Consequently, the delays in simulation and experimental Due to its high forward voltage drop, the diode D1 (see Fig. 11)
tests are not equal. Although the detection time is slightly longer does not influence the circuit behavior in the relevant voltage
than that stated by the simulations, it is still a factor four faster range around the comparator threshold voltage and can therefore
than with a common desaturation detection. be neglected. The objective of this diode is discussed later in
The test results at a high-side IGBT are presented in Fig. 14. this paper. The resulting transfer function of the voltage v1 is
They verify that the proposed circuit can be used for high-side
IGBTs as well and that both faults are detected (red circles). The
1
CD C + RDC s + LDC s2
V1 (s) = −τ1 IDC (s) (11)
detection delays are close to the delays at the low-side IGBT. 1 + τ1 s
where τ1 is the time constant τ1 = C1 R1 .
III. DC-LINK VOLTAGE TRANSIENT DETECTION
V1 (s) shows that beside the current iDC , the voltage v1 is
To detect a short-circuit current in the dc link, the change affected by the derivative of the current and the second derivative
of the dc-link voltage can be analyzed. This can be realized by of the current. For the components’ selection, it must also be
adding a smaller capacitor and a resistor in parallel to the dc- considered that the time constant and the gain of the detection
link capacitor (see Fig. 12). The capacitor voltage follows the circuit are linked by the time constant τ1 .
dc-link voltage. Assuming that the current from the dc source The influence of the derivative and the second derivative to
changes slowly compared to the capacitor current and the short- the dc-link voltage and to v1 are illustrated in Fig. 16. For this
circuit current is mainly fed from the dc-link capacitor in the first investigation, the component values in Table III are used. In the
KRONE et al.: FAST AND EASILY IMPLEMENTABLE DETECTION CIRCUITS FOR SHORT CIRCUITS OF POWER SEMICONDUCTORS 2877
Fig. 13. Test results of the accelerated desaturation detection circuit (LOW side, T 1 and R 4 not applied).
Fig. 14. Test results of the accelerated desaturation detection circuit (HIGH side, T 1 and R 4 not applied).
Fig. 15. Test results of the dc-link voltage transient detection circuit.
2878 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 53, NO. 3, MAY/JUNE 2017
first step, the voltage drop due to the measured capacitor cur-
rent behavior is calculated separately for the capacitor and the
parasitic inductor and resistor (b). This calculation is validated
by comparing the sum of these voltage drops to the measured
one (c). Next, the voltages v1 resulting from these voltage drops
are calculated (d), and again the sum is compared to the mea-
sured voltage (e). The results show that especially the second
derivative combined with the parasitic inductance leads to high-
voltage peaks. This must be considered for the detection circuit
design.
The voltage peaks due to the capacitor current transient can
be reduced by the additional low-pass filter (R1, PT1 , C1, PT1 ),
but as shown in Fig. 16(f), this does not block the high-voltage
peaks effectively. Therefore, the voltage v1 is additionally cut
by a diode D1 at its forward voltage drop (here Vf , D1 = 1.8 V).
The voltage level should be selected slightly above the compared
voltage level Vcom p . Depending on the compared voltage level,
either the reverse voltage drop of a zener diode or the forward
voltage drop of a normal diode can thus be used. With this circuit,
voltage overshoots of v1, PT1 and resulting false detections can
be prevented [see Fig. 16 graph (f)].
For the selection of the compared voltage, the maximum cur-
rent of the dc-link capacitor under normal condition and the
minimum current under short-circuit condition must be identi-
fied (“worst case consideration”). The capacitor current under
normal condition is maximum in case of a maximum recupera-
tion current to the dc source and a maximum phase current. The
minimum current is the minimum short-circuit current which
shall be detected reduced by the maximum input current from
the dc source
IDC, norm , m ax = Iload, m ax − IDC, in, m in (12)
IDC, short, m in = Ishort, m in − IDC, in, m ax . (13) Fig. 16. Transient behavior of dc-link voltage transient detection circuit:
(a) dc-link capacitor current iD C (measured); (b) resulting dc-link voltage drops
Therefore, a gap between these currents is necessary to detect the (calculated separately for capacitor and parasitic inductance and resistance);
short circuit. The optimum compared voltage can be chosen in (c) comparison of calculated and measured overall voltage drop; (d) v 1 result-
the middle of the resulting voltages in case of IDC, norm , m ax and ing from voltage drops (calculated separately); (e) comparison of calculated and
measured overall voltage v 1 ; and (f) effects of the voltage transient suppression
IDC, short, m in . Assuming that the maximum dc source current (calculated).
is the same in both directions (IDC, in, m ax = −IDC, in, m in ), the
optimum compared voltage can be calculated as
TABLE III
τ1 Iload, m ax + Ishort, m in DESIGN PARAMETER AND COMPONENTS’ VALUES OF THE DC-LINK VOLTAGE
Vcom p =− . (14)
CDC 2 TRANSIENT DETECTION
and the error is detected by the comparator (red circles). Besides [10] Z. Wang, X. Shi, L. M. Tolbert, F. Wang, and B. J. Blalock, “A di/dt
the circuit design, the delay depends on the time period until the feedback-based active gate driver for smart switching and fast overcur-
rent protection of IGBT modules,” IEEE Trans. Power Electron., vol. 29,
capacitor current exceeds the minimum detection current. If the no. 7, pp. 3720–3732, Jul. 2014.
resulting short-circuit current inside the dc-link capacitors is [11] F. Huang and F. Flett, “IGBT fault protection based on di/dt feed-
reduced, e.g., by an additional dc source current, the short cir- back control,” in Proc. 2007 IEEE Power Electron. Spec. Conf., 2007,
pp. 1478–1484.
cuit is delayed. Therefore, a slower increase in the short-circuit [12] T. Krone, C. Xu, and A. Mertens, “Fast and easily implementable detection
currents leads to a longer detection time period and to higher circuits for short-circuits of power semiconductors,” in Proc. 2015 IEEE
thermal stress to the devices. Energy Convers. Congr. Expo., Sep. 2015, pp. 2715–2722.
[13] F. Blaabjerg, J. K. Pedersen, U. Jaeger, and P. Thoegersen, “Single current
Summing up, the tests showed that under the given condi- sensor technique in the DC link of three-phase PWM-VS inverters: A
tions, short-circuit faults can be detected by the proposed circuit review and a novel solution,” IEEE Trans. Ind. Appl., vol. 33, no. 5,
and that under normal switching conditions, no false detection pp. 1241–1253, Sep./Oct. 1997.
occurs.
IV. CONCLUSION
Tobias Krone (S’13) received the Dipl.-Ing. degree
In this paper, two approaches for fast accelerated short-circuit in electrical engineering from the Leibniz Universität
fault detection are presented. The first one is an accelerated Hannover, Hannover, Germany, in 2012.
desaturation detection. It is shown that by combining the desat- Since 2012, he has been a Research Associate in
the Institute for Drives Systems and Power Electron-
uration detection and the feedback of the gate–emitter voltage, ics, Leibniz Universität. His research interests include
the fault detection can be accelerated significantly. Furthermore, gate drivers for power semiconductors and converter
the hardware effort is comparable to the common desaturation topologies for fault tolerant drive systems in automo-
tive applications.
detection circuit. The concept is verified by simulations and
tests.
The second proposed approach is suitable for monitoring all
half-bridges of an inverter at the same time regarding short-
circuit faults. This is realized by detecting dc-link voltage tran-
sients. For this purpose, a detection circuit is presented in this Chengzhi Xu received the B.Sc. degree in inte-
paper. It is verified by simulations and tests as well. grated circuit design and integration system from the
Xidian University, Xi’an, China, in 2010 and the
In summary, the first approach is a good possibility to use M.Sc. degree in electrical engineering and infor-
the well-known desaturation detection in applications requiring mation technology from the Leibniz Universität
the fast fault detection. The second approach is a convenient Hannover, Hannover, Germany, in 2014.
In 2014 and 2015, he was a Student Assistant in
short-circuit detection for space- or cost-critical applications. the Institute for Drive Systems and Power Electron-
ics, Leibniz Universität. His main research interests
include gate drivers for power semiconductors.
REFERENCES
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[2] U.-M. Choi, F. Blaabjerg, and K.-B. Lee, “Study and handling meth-
ods of power IGBT module failures in power electronic converter sys- Axel Mertens (S’89–M’92) received the Dipl.-
tems,” IEEE Trans. Power Electron., vol. 30, no. 5, pp. 2517–2533, Ing. and Dr.-Ing. (Ph.D.) degrees from Rheinisch-
May 2015. Westfaelische Technische Hochschule (RWTH)
[3] S. Hain and M. M. Bakran, “New ultra fast short circuit detection method Aachen University, Aachen, Germany, in 1987 and
without using the desaturation process of the power semiconductor,” in 1992, respectively.
Proc. Int. Exhib. Conf. Power Electron. Intell. Motion Renewable Energy In 1989, he was a Research Associate in the
Energy Manage., 2016, pp. 1–8. Wisconsin Electric Machines and Power Electronics
[4] Z. Wang, X. Shi, Y. Xue, L. M. Tolbert, F. Wang, and B. J. Blalock, Consortium, University of Wisconsin, Madison, WI,
“Design and performance evaluation of overcurrent protection schemes USA. From 1993 to 2004, he was with Siemens Drive
for silicon carbide (SiC) power MOSFETs,” IEEE Trans. Ind. Electron., Technologies, Germany, where he was responsible
vol. 61, no. 10, pp. 5570–5581, Oct. 2014. for the control of large drives ranging from three-level
[5] M. Rodriguez, A. Claudio, D. Theilliol, and L. Vela, “A new fault detection high-voltage insulated-gate bipolar transistor inverters to cycloconverters and
technique for IGBT based on gate voltage monitoring,” in Proc. 2007 IEEE load-commutated inverters. In 2004, he was appointed as a Professor of power
Power Electron. Spec. Conf., Jun. 2007, pp. 1001–1005. electronics and drives, Leibniz Universität Hannover, Hannover, Germany. Since
[6] M.-S. Kim, B.-G. Park, R.-Y. Kim, and D.-S. Hyun, “A novel fault de- 2012, he has been the Head of the Department Converter Technology within the
tection circuit for short-circuit faults of IGBT,” in Proc. 2011 26th Annu. Fraunhofer Institute for Wind Energy and Energy System Technology. His re-
IEEE Appl. Power Electron. Conf. Expo., 2011, pp. 359–363. search interests include application of wide bandgap semiconductors, condition
[7] T. Horiguchi et al., “A high-speed protection circuit for IGBTs subjected monitoring of power semiconductor devices, design of power electronic circuits,
to hard-switching faults,” in Proc. 2014 29th Annu. IEEE Appl. Power modular multilevel converters, and control of electronic power converters and
Electron. Expo., Mar. 2014, pp. 2519–2525. drives. His preferred fields of application are industrial drives, electric vehicles,
[8] B.-G. Park, J.-B. Lee, and D.-S. Hyun, “A novel short-circuit detecting and grid connected inverters such as in wind power systems.
scheme using turn-on switching characteristic of IGBT,” in Proc. 2008 Prof. Mertens published more than 100 technical papers and holds a number
IEEE Ind. Appl. Soc. Annu. Meeting., 2008, pp. 1–5. of patents. He is an Associate Editor of the IEEE TRANSACTIONS ON POWER
[9] J.-B. Lee and D.-S. Hyun, “Gate voltage pattern analyze for short-circuit ELECTRONICS and served as the Chairman of the IEEE Joint German Chapter
protection in IGBT inverters,” in Proc. 2007 IEEE Power Electron. Spec. of the IEEE INDUSTRY APPLICATIONS, IEEE POWER ELECTRONICS, and IEEE
Conf., 2007, pp. 1913–1917. INDUSTRIAL ELECTRONICS SOCIETIES.