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Features Description
• MOSFET Input Stage The CA3140A and CA3140 are integrated circuit operational amplifiers
- Very High Input Impedance (ZIN) -1.5TΩ (Typ.) that combine the advantages of high voltage PMOS transistors with
high voltage bipolar transistors on a single monolithic chip. Because of
- Very Low Input Current (Il) -10pA (Typ.) at ±15V
this unique combination of technologies, this device can now provide
- Wide Common Mode Input Voltage Range designers, for the first time, with the special performance features of
(VlCR) - Can be Swung 0.5V Below Negative the CA3130 CMOS operational amplifiers and the versatility of the 741
Supply Voltage Rail series of industry standard operational amplifiers.
- Output Swing Complements Input Common The CA3140A and CA3140 BiMOS operational amplifiers feature gate
Mode Range protected MOSFET (PMOS) transistors in the input circuit to provide
• Directly Replaces Industry Type 741 in Most very high input impedance, very low input current, and high speed per-
Applications formance. The CA3140A and CA3140 operate at supply voltage from
4V to 36V (either single or dual supply). These operational amplifiers
Applications are internally phase compensated to achieve stable operation in unity
gain follower operation, and additionally, have access terminal for a
• Ground-Referenced Single Supply Amplifiers in supplementary external capacitor if additional frequency roll-off is
Automobile and Portable Instrumentation desired. Terminals are also provided for use in applications requiring
• Sample and Hold Amplifiers input offset voltage nulling. The use of PMOS field effect transistors in
the input stage results in common mode input voltage capability down
• Long Duration Timers/Multivibrators to 0.5V below the negative supply terminal, an important attribute for
(µseconds-Minutes-Hours) single supply applications. The output stage uses bipolar transistors
• Photocurrent Instrumentation and includes built-in protection against damage from load terminal
short circuiting to either supply rail or to ground.
• Peak Detectors
The CA3140 Series has the same 8-lead pinout used for the “741” and
• Active Filters other industry standard op amps. The CA3140A and CA3140 are
• Comparators intended for operation at supply voltages up to 36V (±18V).
• Interface in 5V TTL Systems and Other Low
Supply Voltage Systems
Ordering Information
PART NUMBER TEMP. RANGE PACKAGE
• All Standard Operational Amplifier Applications
CA3140AE -55oC to +125oC 8 Lead Plastic DIP
• Function Generators
CA3140AM -55oC to +125oC 8 Lead SOIC
• Tone Controls
CA3140AS -55o o
C to +125 C 8 Pin Can, Lead Formed
• Power Supplies CA3140AT -55oC to +125oC 8 Pin Can
• Portable Instruments CA3140BT -55oC to +125oC 8 Pin Can
• Intrusion Alarm Systems CA3140E -55oC to +125oC 8 Lead Plastic DIP
CA3140M -55oC to +125oC 8 Lead SOIC
CA3140M96 -55oC to +125oC 8 Lead SOIC*
CA3140T -55oC to +125oC 8 Pin Can
* Denotes Tape and Reel
Pinouts
CA3140 (TO-5 STYLE CAN) CA3140 (PDIP, SOIC)
TOP VIEW TOP VIEW
TAB
STROBE OFFSET
8 1 8 STROBE
NULL
OFFSET 1 7 V+
NULL
INV. INPUT 2 7 V+
– –
INV. 2 6 OUTPUT +
+ NON-INV.
INPUT 3 6 OUTPUT
INPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. File Number 957.2
Copyright © Harris Corporation 1993
2-123
This datasheet has been downloaded from http://www.digchip.com at this page
Specifications CA3140, CA3140A
Input Capacitance CI 4 4 pF
Output Resistance RO 60 60 Ω
f = 10 kHz 12 12 nV/√Hz
Source IOM+ 40 40 mA
Sink IOM- 18 18 mA
2-124
Specifications CA3140, CA3140A
Electrical Specifications For Equipment Design. At V+ = 15V, V- = 15V, TA = +25oC, Unless Otherwise Specified
LIMITS
CA3140A CA3140
Input Current II - 10 40 - 10 50 pA
Common Mode Input Voltage Range VICR -15 -15.5 12 -15 -15.5 11 V
(See Figure 17) to to
+12.5 +12.5
NOTES:
1. At VO = 26Vp-p, +12V, 14V and RL = 2kΩ.
2. At RL = 2kΩ.
Input Current II 2 2 pA
Input Resistance RI 1 1 TΩ
2-125
Specifications CA3140, CA3140A
90 90 dB
Common Mode Input Voltage Range (See Figure 17) VICR -0.5 -0.5 V
2.6 2.6 V
Source IOM+ 10 10 mA
Sink IOM- 1 1 mA
Device Dissipation PD 8 8 mW
Sink Current from Term. 8 to Term. 4 to Swing Output Low 200 200 µA
2-126
CA3140A, CA3140
Block Diagram
2mA 4mA
7 V+
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
12pF
4 V-
5 1 8 STROBE
OFFSET
NULL
Schematic Diagram
BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK
7 V+
C1 D7
R13
5k
Q3 R9 Q20
Q1 Q2
50Ω
D8
R10
Q6 Q4 1k
Q5 R14
20k
Q19 R11 R12
20Ω 12k
Q7
Q21
Q17
R1 R8
8k Q8 1k
Q18
6 OUTPUT
D2 D3 D4
D5
INVERTING
2
INPUT
- Q9 Q10
+
NON-INVERTING 3
INPUT C1
R2 R3
500Ω 500Ω 12pF
Q14 Q15 Q16
Q13
Q11 Q12 D6
R4 R5 R6 R7
500Ω 500Ω 50Ω 30Ω
5 1 8 4
OFFSET NULL STROBE V-
ALL RESISTANCE VALUES ARE IN Ω
2-127
CA3140A, CA3140
Circuit Description
As shown in the block diagram, the input terminals may be When the CA3140 is operating such that output terminal 6 is
operated down to 0.5V below the negative supply rail. Two sourcing current, transistor Q18 functions as an emitter-
class A amplifier stages provide the voltage gain, and a follower to source current from the V+ bus (terminal 7), via
unique class AB amplifier stage provides the current gain D7, R9, and R11. Under these conditions, the collector
necessary to drive low-impedance loads. potential of Q13 is sufficiently high to permit the necessary
flow of base current to emitter follower Q17 which, in turn,
A biasing circuit provides control of cascoded constant drives Q18.
current flow circuits in the first and second stages. The
CA3140 includes an on chip phase compensating capacitor When the CA3140 is operating such that output terminal 6 is
that is sufficient for the unity gain voltage follower sinking current to the V- bus, transistor Q16 is the current
configuration. sinking element. Transistor Q16 is mirror connected to D6,
R7, with current fed by way of Q21, R12, and Q20. Transistor
Input Stages Q20, in turn, is biased by current flow through R13, zener
D8, and R14. The dynamic current sink is controlled by
The schematic diagram consists of a differential input stage
voltage level sensing. For purposes of explanation, it is
using PMOS field-effect transistors (Q9, Q10) working into a
assumed that output terminal 6 is quiescently established at
mirror pair of bipolar transistors (Q11, Q12) functioning as
the potential midpoint between the V+ and V- supply rails.
load resistors together with resistors R2 through R5. The
When output current sinking mode operation is required, the
mirror pair transistors also function as a differential-to-single-
collector potential of transistor Q13 is driven below its
ended converter to provide base current drive to the second
quiescent level, thereby causing Q17, Q18 to decrease the
stage bipolar transistor (Q13). Offset nulling, when desired,
output voltage at terminal 6. Thus, the gate terminal of
can be effected with a 10kΩ potentiometer connected across
PMOS transistor Q21 is displaced toward the V- bus, thereby
terminals 1 and 5 and with its slider arm connected to
reducing the channel resistance of Q21. As a consequence,
terminal 4. Cascode connected bipolar transistors Q2, Q5
there is an incremental increase in current flow through Q20,
are the constant current source for the input stage. The base
R12, Q21, D6, R7, and the base of Q16. As a result, Q16
biasing circuit for the constant current source is described
sinks current from terminal 6 in direct response to the
subsequently. The small diodes D3, D4, D5 provide gate
incremental change in output voltage caused by Q18. This
oxide protection against high voltage transients, e.g., static
sink current flows regardless of load; any excess current is
electricity.
internally supplied by the emitter-follower Q18. Short circuit
Second Stage protection of the output circuit is provided by Q19, which is
driven into conduction by the high voltage drop developed
Most of the voltage gain in the CA3140 is provided by the across R11 under output short circuit conditions. Under
second amplifier stage, consisting of bipolar transistor Q13 these conditions, the collector of Q19 diverts current from
and its cascode connected load resistance provided by Q4 so as to reduce the base current drive from Q17, thereby
bipolar transistors Q3, Q4. On-chip phase compensation, limiting current flow in Q18 to the short circuited load
sufficient for a majority of the applications is provided by C1. terminal.
Additional Miller-Effect compensation (roll off) can be
accomplished, when desired, by simply connecting a small Bias Circuit
capacitor between terminals 1 and 8. Terminal 8 is also used
Quiescent current in all stages (except the dynamic current
to strobe the output stage into quiescence. When terminal 8
sink) of the CA3140 is dependent upon bias current flow in
is tied to the negative supply rail (terminal 4) by mechanical
R1. The function of the bias circuit is to establish and
or electrical means, the output terminal 6 swings low, i.e.,
maintain constant current flow through D1, Q6, Q8 and D2.
approximately to terminal 4 potential.
D1 is a diode connected transistor mirror connected in
Output Stage parallel with the base emitter junctions of Q1, Q2, and Q3.
D1 may be considered as a current sampling diode that
The CA3140 Series circuits employ a broad band output senses the emitter current of Q6 and automatically adjusts
stage that can sink loads to the negative supply to the base current of Q6 (via Q1) to maintain a constant
complement the capability of the PMOS input stage when current through Q6, Q8, D2. The base currents in Q2, Q3
operating near the negative rail. Quiescent current in the are also determined by constant current flow D1.
emitter-follower cascade circuit (Q17, Q18) is established by Furthermore, current in diode connected transistor Q2
transistors (Q14, Q15) whose base currents are “mirrored” to establishes the currents in transistors Q14 and Q15.
current flowing through diode D2 in the bias circuit section.
2-128
CA3140, CA3140A
0 10 20 30 40 50 60 65
61 60
50
40
58-66
30 (1.473-1.676)
20
10
0
4-10
(0.102-0.254)
62-70
(1.575-1.778)
20
RL = 2kΩ RL = 2kΩ
CL = 100pF
GAIN BANDWIDTH PRODUCT (MHz)
OPEN-LOOP VOLTAGE GAIN (dB)
10
TA = -55oC
8
+25oC +25oC
125
+125oC
+125oC 6
TA = -55oC
100
5
75 4
50 3
25 2
0 1
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
FIGURE 1. OPEN LOOP VOLTAGE GAIN vs SUPPLY FIGURE 2. GAIN BANDWIDTH PRODUCT vs SUPPLY
VOLTAGE AND TEMPERATURE VOLTAGE AND TEMPERATURE
2-129
CA3140, CA3140A
Typical Performance Curves (Continued)
RL = 2kΩ RL = ∞
CL = 100pF
TA = -55oC
6
+25oC
SLEW RATE (V/µs)
+25oC
5 +125oC
+125oC
20 TA = -55oC 4
15 3
10 2
5 1
0 0
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
FIGURE 3. SLEW RATE vs SUPPLY VOLTAGE AND FIGURE 4. QUIESCENT SUPPLY CURRENT vs SUPPLY
TEMPERATURE VOLTAGE AND TEMPERATURE
20
80 CA3140B
15 60
CA3140, CA3140A
10 40
5 20
0 0
2 4 6 8 2 4 6 8 2
101 102 103 104 105 106 107
10K 100K 1M 4M
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 5. MAXIMUM OUTPUT VOLTAGE SWING vs FIGURE 6. COMMON MODE REJECTION RATIO vs FREQUENCY
FREQUENCY
1000
8 SUPPLY VOLTAGE: V+ = 15V, V- = -15V SUPPLY VOLTAGE: V+ = 15V, V- = -15V
EQUIVALENT INPUT NOISE VOLTAGE (nV√Hz)
6 TA = +25oC
POWER SUPPLY REJECTION RATIO (dB)
TA = +25oC
4
100
CA3140B
2
CA3140, +PSRR
100 80
8
CA3140A
6
4 60
2
10 40 -PSRR
8
6
4
20
POWER SUPPLY REJECTION RATIO
2
(PSRR) = ∆VIO/∆VS
1 0
1 101 102 103 104 105 101 102 103 104 105 106 107
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 7. EQUIVALENT INPUT NOISE VOLTAGE vs FIGURE 8. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FREQUENCY
2-130
CA3140, CA3140A
2
V+ DIFFERENTIAL DC VOLTAGE
5V TO 36V
(ACROSS TERMS 2 AND 3) = 0V
LOGIC 1
7 OUTPUT VOLTAGE = V+ / 2
SUPPLY
2 8 6.2V 5V
0
≈5V 0 500 1000 1500 2000 2500 3000 3500 4000 4500
CA3140 6 TYPICAL TIME (HOURS)
TTL GATE
3
4
FIGURE 11. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT
vs OPERATING LIFE
6
TA = +25oC may be placed at either end of the potentiometer, see Figure
4
12(B), to optimize its utilization range are given in the table
SATURATION VOLTAGE (mV)
2
“Electrical Specifications” shown in this bulletin.
100 SUPPLY VOLTAGE (V+) = +5V
8 +15V
6 An alternate system is shown in Figure 12(C). This circuit
+30V
4 uses only one additional resistor of approximately the value
shown in the table. For potentiometers, in which the resis-
2
tance does not drop to zero Ω at either end of rotation, a
10
8
value of resistance 10% lower than the values shown in the
6 table should be used.
4
Low Voltage Operation
2
1
Operation at total supply voltages as low as 4V is possible
2 4 6 8 2 4 6 8 2 4 6 8
0.01 0.1 1.0 10 with the CA3140. A current regulator based upon the PMOS
LOAD (SINKING) CURRENT (mA) threshold voltage maintains reasonable constant operating
current and hence consistent performance down to these
FIGURE 10. VOLTAGE ACROSS OUTPUT TRANSISTORS Q15 lower voltages.
AND Q16 vs LOAD CURRENT
The low voltage limitation occurs when the upper extreme of
the input common mode voltage range extends down to the
2-131
CA3140, CA3140A
V+ V+ V+
2 7 2 7 2 7
3 4 3 4 3 4
5 5 5
1 1 1
10kΩ 10kΩ
10kΩ
V- V-
V-
(A) BASIC (B) IMPROVED (C) SIMPLER
RESOLUTION IMPROVED
RESOLUTION
FIGURE 12. THREE OFFSET VOLTAGE NULLING METHODS
RS V+ +HV
7 LOAD
LOAD 2
30V
NO LOAD MT2 CA3140 6
120VAC 7 RL
2 3
4
CA3140 6
MT1
RL
3
4
FIGURE 13. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
FOLLOWER
+15V
7
3 0.1µF
SIMULATED
LOAD RESISTANCE (RL) = 2kΩ 10kΩ LOAD
LOAD CAPACITANCE (CL) = 100pF CA3140 6
SUPPLY VOLTAGE: V+ = +15V, V- = -15V 100pF 2kΩ
2
TA = +25oC 4
10 0.1µF
1mV 1mV
8 -15V
10mV 10mV
INPUT VOLTAGE (V)
6 2kΩ
4
2 0.05µF
FOLLOWER
0 INVERTING
INVERTING
-2 5kΩ
-4
+15V
-6 1mV 1mV
7
-8 10mV 10mV 0.1µF
2 SIMULATED
-10 5kΩ LOAD
2 4 6 8 2 4 6 8
0.1 1.0 10 CA3140 6
200Ω
SETTLING TIME (µs)
3 100pF 2kΩ
(A) 4
0.1µF 5.11kΩ
4.99kΩ
-15V
SETTLING POINT
D1 D2
IN914 IN914
(B) TEST CIRCUITS
2-132
CA3140, CA3140A
voltage at terminal 4. This limit is reached at a total supply amplifiers. The exceptionally fast settling time characteristics
voltage just below 4V. The output voltage range also begins are largely due to the high combination of high gain and wide
to extend down to the negative supply rail, but is slightly bandwidth of the CA3140; as shown in Figure 15.
higher than that of the input. Figure 17 shows these
characteristics and shows that with 2V dual supplies, the Input Circuit Considerations
lower extreme of the input common mode voltage range is As mentioned previously, the amplifier inputs can be driven
below ground potential. below the terminal 4 potential, but a series current limiting
Bandwidth and Slew Rate resistor is recommended to limit the maximum input terminal
current to less than 1mA to prevent damage to the input pro-
For those cases where bandwidth reduction is desired, for tection circuitry.
example, broadband noise reduction, an external capacitor
connected between terminals 1 and 8 can reduce the open Moreover, some current limiting resistance should be
loop -3dB bandwidth. The slew rate will, however, also be provided between the inverting input and the output when
proportionally reduced by using this additional capacitor. the CA3140 is used as a unity gain voltage follower. This
Thus, a 20% reduction in bandwidth by this technique will resistance prevents the possibility of extremely large input
also reduce the slew rate by about 20%. signal transients from forcing a signal through the input
protection network and directly driving the internal constant
Figure 14 shows the typical settling time required to reach current source which could result in positive feedback via the
1mV or 10mV of the final value for various levels of large output terminal. A 3.9kΩ resistor is sufficient.
signal inputs for the voltage follower and inverting unity gain
10K 8
SUPPLY VOLTAGE: V+ = 15V, V- = -15V
OPEN LOOP PHASE
-75 6
SUPPLY VOLTAGE: V+ = 15V, V- = -15V 4
TA = +25oC -90
(DEGREES)
RL = 2kΩ, 2
OPEN LOOP VOLTAGE GAIN (dB)
6
80 -135 4
-150 2
60 100
8
6
RL = 2kΩ, 4
40 CL = 100pF 2
10 8
6
20
4
2
0 1
101 102 103 104 105 106 107 108 -60 -40 -20 0 20 40 60 80 100 120 140
FREQUENCY (Hz) AMBIENT TEMPERATURE (oC)
FIGURE 15. OPEN LOOP VOLTAGE GAIN AND PHASE vs FIGURE 16. INPUT CURRENT vs AMBIENT TEMPERATURE
FREQUENCY
RL = ∞
INPUT AND OUTPUT VOLTAGE EXCURSIONS
0 1.5
-2.0 -0.5
-2.5 -1.0
-3.0 -1.5
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V+, V-) SUPPLY VOLTAGE (V+, V-)
FIGURE 17. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE AND
TEMPERATURE
2-133
CA3140, CA3140A
The typical input current is in the order of 10pA when the the Frequency Adjustment Control. This low-driving
inputs are centered at nominal device dissipation. As the impedance requirement is easily met by using a CA3140
output supplies load current, device dissipation will increase, connected as a voltage follower. Moreover, a meter may be
raising the chip temperature and resulting in increased input placed across the input to the CA3080A to give a logarithmic
current. Figure 16 shows typical input terminal current ver- analog indication of the function generators frequency.
sus ambient temperature for the CA3140.
Analog frequency readout is readily accomplished by the
It is well known that MOSFET devices can exhibit slight means described above because the output current of the
changes in characteristics (for example, small changes in CA3080A varies approximately one decade for each 60mV
input offset voltage) due to the application of large differen- change in the applied voltage, VABC (voltage between
tial input voltages that are sustained over long periods at ele- terminals 5 and 4 of the CA3080A of the function generator).
vated temperatures. Therefore, six decades represent 360mV change in VABC.
Both applied voltage and temperature accelerate these Now, only the reference voltage must be established to set
changes. The process is reversible and offset voltage shifts the lower limit on the meter. The three remaining transistors
of the opposite polarity reverse the offset. Figure 11 shows from the CA3086 Array used in the sweep generator are
the typical offset voltage change as a function of various used for this reference voltage. In addition, this reference
stress voltages at the maximum rating of +125oC (for TO-5); generator arrangement tends to track ambient temperature
at lower temperatures (TO-5 and plastic), for example, at variations, and thus compensates for the effects of the nor-
+85oC, this change in voltage is considerably less. In typical mal negative temperature coefficient of the CA3080A VABC
linear applications, where the differential voltage is small and terminal voltage.
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational Another output voltage from the reference generator is used
amplifier employing a bipolar transistor input stage. to insure temperature tracking of the lower end of the
Frequency Adjustment Potentiometer. A large series
Super Sweep Function Generator resistance simulates a current source, assuring similar
temperature coefficients at both ends of the Frequency
A function generator having a wide tuning range is shown in
Adjustment Control.
Figure 18. The 1,000,000/1 adjustment range is accom-
plished by a single variable potentiometer or by an auxiliary To calibrate this circuit, set the Frequency Adjustment
sweeping signal. The CA3140 functions as a non-inverting Potentiometer at its low end. Then adjust the Minimum
readout amplifier of the triangular signal developed across Frequency Calibration Control for the lowest frequency. To
the integrating capacitor network connected to the output of establish the upper frequency limit, set the Frequency
the CA3080A current source. Adjustment Potentiometer to its upper end and then adjust
Buffered triangular output signals are then applied to a sec- the Maximum Frequency Calibration Control for the
ond CA3080 functioning as a high speed hysteresis switch. maximum frequency. Because there is interaction among
Output from the switch is returned directly back to the input these controls, repetition of the adjustment procedure may
of the CA3080A current source, thereby, completing the pos- be necessary. Two adjustments are used for the meter. The
itive feedback loop meter sensitivity control sets the meter scale width of each
decade, while the meter position control adjusts the pointer
The triangular output level is determined by the four 1N914 on the scale with negligible effect on the sensitivity
level limiting diodes of the second CA3080 and the resistor adjustment. Thus, the meter sensitivity adjustment control
divider network connected to terminal No. 2 (input) of the calibrates the meter so that it deflects 1/6 of full scale for
CA3080. These diodes establish the input trip level to this each decade change in frequency.
switching stage and, therefore, indirectly determine the
amplitude of the output triangle. Sine Wave Shaper
Compensation for propagation delays around the entire loop The circuit shown in Figure 20 uses a CA3140 as a voltage
is provided by one adjustment on the input of the CA3080. follower in combination with diodes from the CA3019 Array
This adjustment, which provides for a constant generator to convert the triangular signal from the function generator to
amplitude output, is most easily made while the generator is a sine-wave output signal having typically less than 2% THD.
sweeping. High frequency ramp linearity is adjusted by the The basic zero crossing slope is established by the 10kΩ
single 7-to-6pF capacitor in the output of the CA3080A. potentiometer connected between terminals 2 and 6 of the
CA3140 and the 9.1kΩ resistor and 10kΩ potentiometer
It must be emphasized that only the CA3080A is from terminal 2 to ground. Two break points are established
characterized for maximum output linearity in the current by diodes D1 through D4. Positive feedback via D5 and D6
generator function. establishes the zero slope at the maximum and minimum
levels of the sine wave. This technique is necessary because
Meter Driver and Buffer Amplifier the voltage follower configuration approaches unity gain
Figure 19 shows the CA3140 connected as a meter driver rather than the zero gain required to shape the sine wave at
and buffer amplifier. Low driving impedance is required of the two extremes.
the CA3080A current source to assure smooth operation of
2-134
CA3140, CA3140A
CENTERING
-15V 10kΩ +15V
HIGH
7.5kΩ +15V +15V FREQUENCY
LEVEL 910 62kΩ 10kΩ
360Ω 0.1 kΩ
7 µF 7-60pF
3 + 7
15kΩ 5 EXTERNAL
360Ω CA3080A 6 3 + 7
51 OUTPUT
2 - 7-60 CA3140 6 2 -
4 pF
pF 2 - 11kΩ CA3080 6
5 10kΩ 11kΩ 3 +
2MΩ HIGH 4
4 2.7kΩ
SYMMETRY -15V FREQ. 0.1
-15V EXTERNAL
+15V SHAPE -15V µF -15V
OUTPUT 13kΩ TO OUTPUT
2kΩ
100kΩ
AMPLIFIER
FROM BUFFER METER FREQUENCY 5.1
DRIVER (OPTIONAL) TO
ADJUSTMENT kΩ
39Ω 120Ω 10kΩ SINE WAVE
SHAPER IN914
-15V +15V OUTPUT
AMPLIFIER
THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT USED
(A) CIRCUIT
FREQUENCY
ADJUSTMENT
+15V
(B1) FUNCTION GENERATOR SWEEPING METER DRIVER
POWER
AND BUFFER
Top Trace: Output at junction of 2.7Ω and 51Ω resistors SUPPLY ±15V
AMPLIFIER M
5V/Div and 500ms/Div -15V
GATE DC LEVEL
FINE SWEEP
SWEEP ADJUST
RATE GENERATOR
OFF INT.
EXTERNAL
COARSE V- EXT. INPUT
RATE
SWEEP
LENGTH
V-
(B2) FUNCTION GENERATOR WITH FIXED FREQUENCIES (C) INTERCONNECTIONS
1V/Div and 1sec/Div
Three tone test signals, highest frequency ≥0.5MHz. Note the slight
asymmetry at the three second/cycle signal. This asymmetry is due
to slightly different positive and negative integration from the
CA3080A and from the pc board and component leakages at the
100pA level.
FIGURE 18. FUNCTION GENERATOR
2-135
CA3140, CA3140A
FREQUENCY
500kΩ CALIBRATION
MAXIMUM
FREQUENCY 620kΩ
51kΩ 7
ADJUSTMENT TO CA3080A +15V -15V
10kΩ 3 + OF FUNCTION CA3080A
0.1µF
CA3140 6 GENERATOR 5.6
SWEEP IN (FIGURE 18) 7 7.5
3MΩ - 3 + kΩ
2 4.7kΩ 4 kΩ
5.1kΩ CA3140 6
4 5
TO
+15V 2 - 4 SUBSTRATE WIDEBAND
2kΩ METER 620Ω
0.1µF OF CA3019 OUTPUT
SENSITIVITY
12 ADJUSTMENT 0.1µF AMPLIFIER
1kΩ 7
FREQUENCY 2.4kΩ kΩ 10kΩ
-15V
CALIBRATION 200µA +15V
M METER R3 10kΩ
MINIMUM EXTERNAL
2.5 100 1MΩ
kΩ 11 OUTPUT
kΩ D1 D4
9 9.1kΩ
510Ω -15V
510Ω 6 5 8 2
R1
8 10 14 10kΩ
2kΩ D3 D6 D2 430Ω
6 12 9 1
METER R2
7 POSITION 3.6kΩ 13 1kΩ
ADJUSTMENT 3 4
3/ D5
5 OF CA3086 CA3019
-15V DIODE ARRAY
FIGURE 19. METER DRIVER AND BUFFER AMPLIFIER FIGURE 20. SINE WAVE SHAPER
750kΩ
“LOG”
100kΩ
IN914 SAWTOOTH 18MΩ
FINE
1MΩ 100kΩ
RATE
22MΩ
IN914 SAWTOOTH 8.2kΩ
0.47µF
SYMMETRY +15V SAWTOOTH AND
RAMP LOW LEVEL
SET (-14.5V)
0.047µF COARSE 50kΩ
RATE
4700pF
470pF 75kΩ
SAWTOOTH 51kΩ
+15V
0.1
µF “LOG” +15V
+15V
7
2 - TRIANGLE 36kΩ 7
CA3140 6 3 - 10kΩ GATE
+ 100kΩ CA3140 6 PULSE
3 4
30kΩ + OUTPUT
0.1 TO OUTPUT 2 4
µF 50kΩ AMPLIFIER
-15V
-15V LOG
RATE 10kΩ
ADJUST EXTERNAL OUTPUT
43kΩ
10kΩ TO FUNCTION GENERATOR “SWEEP IN”
SWEEP WIDTH
-15V
7 +15V
3 +
CA3140 6
2 - 4 51kΩ 6.8kΩ 91kΩ 10kΩ
LOGVIO 5
1
TRIANGLE
25kΩ
5 1
3.9Ω SAWTOOTH
TRANSISTORS
4 2 FROM CA3086
-15V ARRAY
100Ω “LOG”
390Ω 3
2-136
CA3140, CA3140A
Sweeping Generator
Figure 21 shows a sweeping generator. Three CA3140's are FIGURE 23. BASIC SINGLE SUPPLY VOLTAGE REGULATOR
used in this circuit. One CA3140 is used as an integrator, a SHOWING VOLTAGE FOLLOWER CONFIGURATION
second device is used as a hysteresis switch that deter- Essentially, the regulators, shown in Figures 24 and 25, are
mines the starting and stopping points of the sweep. A third connected as non inverting power operational amplifiers with
CA3140 is used as a logarithmic shaping network for the log a gain of 3.2. An 8V reference input yields a maximum out-
function. Rates and slopes, as well as sawtooth, triangle, put voltage slightly greater than 25V. As a voltage follower,
and logarithmic sweeps are generated by this circuit. when the reference input goes to 0V the output will be 0V.
Wideband Output Amplifier Because the offset voltage is also multiplied by the 3.2 gain
factor, a potentiometer is needed to null the offset voltage.
Figure 22 shows a high slew rate, wideband amplifier
Series pass transistors with high ICBO levels will also prevent
suitable for use as a 50Ω transmission line driver. This
the output voltage from reaching zero because there is a
circuit, when used in conjunction with the function generator
finite voltage drop (VCEsat) across the output of the CA3140
and sine wave shaper circuits shown in Figures 18 and 20
(see Figure 10). This saturation voltage level may indeed set
provides 18V peak-to-peak output open circuited, or 9V
the lowest voltage obtainable.
peak-to-peak output when terminated in 50Ω. The slew rate
required of this amplifier is 28V/µs (18V peak-to-peak x π x The high impedance presented by terminal 8 is advanta-
0.5MHz). geous in effecting current limiting. Thus, only a small signal
transistor is required for the current-limit sensing amplifier.
Resistive decoupling is provided for this transistor to mini-
+15V mize damage to it or the CA3140 in the event of unusual
+ 50µF 2.2 input or output transients on the supply rail.
SIGNAL
LEVEL - 25V kΩ 2N3053
ADJUSTMENT Figures 24 and 25, show circuits in which a D2201 high
2.5kΩ 3 + 7 IN914 2.7Ω OUT speed diode is used for the current sensor. This diode was
51Ω
CA3140 6 chosen for its slightly higher forward voltage drop character-
200Ω IN914 2.7Ω 2W istic, thus giving greater sensitivity. It must be emphasized
2 - 4
8
1 - 50µF that heat sinking of this diode is essential to minimize varia-
OUTPUT
+ 25V 2.2 2N4037 tion of the current trip point due to internal heating of the
2.4pF kΩ diode. That is, 1A at 1V forward drop represents one watt
DC LEVEL +15V
ADJUSTMENT 3kΩ 2pF
-15V which can result in significant regenerative changes in the
current trip point as the diode temperature rises. Placing the
-15V
1.8kΩ NOMINAL BANDWIDTH = 10MHz small signal reference amplifier in the proximity of the current
200Ω tr = 35ns
sensing diode also helps minimize the variability in the trip
level due to the negative temperature coefficient of the
diode. In spite of those limitations, the current limiting point
FIGURE 22. WIDEBAND OUTPUT AMPLIFIER can easily be adjusted over the range from 10mA to 1A with
a single adjustment potentiometer. If the temperature stabil-
Power Supplies ity of the current limiting system is a serious consideration,
High input impedance, common mode capability down to the the more usual current sampling resistor type of circuitry
negative supply and high output drive current capability are should be employed.
key factors in the design of wide range output voltage A power Darlington transistor (in a heat sink TO-3 case), is used
supplies that use a single input voltage to provide a as the series pass element for the conventional current limiting
regulated output voltage that can be adjusted from system, Figure 24, because high power Darlington dissipation
essentially 0V to 24V. will be encountered at low output voltage and high currents.
Unlike many regulator systems using comparators having a A small heat sink VERSAWATT transistor is used as the
bipolar transistor input stage, a high impedance reference series pass element in the fold back current system, Figure
voltage divider from a single supply can be used in 25, since dissipation levels will only approach 10W. In this
connection with the CA3140 (see Figure 23). system, the D2201 diode is used for current sampling. Fold-
2-137
CA3140, CA3140A
back is provided by the 3kΩ and 100kΩ divider network con- Both regulators, Figures 24 and 25, provide better than 0.02%
nected to the base of the current sensing transistor. load regulation. Because there is constant loop gain at all volt-
age settings, the regulation also remains constant. Line regu-
2N6385 CURRENT
POWER DARLINGTON LIMITING lation is 0.1% per volt. Hum and noise voltage is less than
OUTPUT
ADJUST
0.1 ⇒ 24V
200µV as read with a meter having a 10MHz bandwidth.
D2201 AT 1A
+30V 3 2 Figure 28 (a) shows the turn ON and turn OFF characteris-
75Ω 1kΩ 1kΩ 1 tics of both regulators. The slow turn on rise is due to the
1kΩ slow rate of rise of the reference voltage. Figure 26 (B)
3kΩ 2 shows the transient response of the regulator with the
2N2102
3 switching of a 20Ω load at 20V output.
100Ω 1kΩ
1 8
7 56pF 180kΩ
2
6 1kΩ
CA3140 82kΩ
+ 5
2.7kΩ 10µF 3
- 100kΩ
1
4
INPUT
VOLTAGE
+ ADJUST +
2.2kΩ 5µF 50kΩ 250µF
- -
100kΩ
10 11 1 2 14
12
9 3 0.01µF
8 7 5 13
6 4 CA3086
OUTPUT ⇒ 0V TO 25V
“FOLDBACK” CURRENT
LIMITER 25V AT 1A
“FOLDS BACK”
2N5294 D2201 TO 40mA
+30V 2 3
1kΩ 200Ω
1
100kΩ 3kΩ
100kΩ 2N2102
1kΩ
8
7 56pF 180kΩ
2
6 CA3140 1kΩ
82kΩ
+ 5 (B) TRANSIENT RESPONSE
2.7kΩ 10µF 3
- 100kΩ
1
4
INPUT
Top Trace: Output voltage
VOLTAGE 200mV/Div and 5µs/Div
+ ADJUST +
2.2kΩ 5µF 50kΩ 250µF
- - Bottom Trace: Collector of load switching transistor, load = 1A
100kΩ
10 11 1 2 14 5V/Div and 5µs/Div
12
FIGURE 26. WAVEFORMS OF DYNAMIC CHARACTERISTICS
9 3 0.01µF OF POWER SUPPLY CURRENTS SHOWN IN FIG-
8 7 5 13 URES 24 AND 25
2-138
CA3140, CA3140A
The first circuit, shown in Figure 28, is the Baxandall tone Figure 27 shows another tone control circuit with similar
control circuit which provides unity gain at midband and uses boost and cut specifications. The wideband gain of this cir-
standard linear potentiometers. The high input impedance of cuit is equal to the ultimate boost or cut plus one, which in
the CA3140 makes possible the use of low-cost, low-value, this case is a gain of eleven. For 20dB boost and cut, the
small size capacitors, as well as reduced load of the driving input loading of this circuit is essentially equal to the value of
stage. the resistance from terminal No. 3 to ground. A detailed
analysis of this circuit is given in “An IC Operational
Bass treble boost and cut are ±15dB at 100Hz and 10kHz,
TransconductanceAmplifier (OTA) With Power Capability” by
respectively. Full peak-to-peak output is available up to at
L. Kaplan and H. Wittlinger, IEEE Transactions on Broadcast
least 20kHz due to the high slew rate of the CA3140. The
and Television Receivers, Vol. BTR-18, No. 3, August, 1972.
amplifier gain is 3dB down from its “flat” position at 70kHz.
FIGURE 27. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)
51kΩ 5MΩ 51kΩ ±15dB Bass and Treble Boost and Cut at
(LINEAR) 100Hz and 10kHz, respectively
BOOST TREBLE CUT 25VP-P output at 20kHz
TONE CONTROL NETWORK -3dB at 70kHz from 1kHz reference
0dB Flat Position Gain
2-139
CA3140, CA3140A
2-140
CA3140, CA3140A
represents the typical leakage current of the CA3080A when Current Amplifier
strobed off. If C1 were increased to 2000 pF, the “hold-droop”
rate will decrease to 0.085µV/µs, but the slew rate would The low input terminal current needed to drive the CA3140
decrease to 0.25V/µs. The parallel diode network connected makes it ideal for use in current amplifier applications such
between terminal 3 of the CA3080A and terminal 6 of the as the one shown in Figure 33.* In this circuit, low current is
CA3140 prevents large input signal feedthrough across the supplied at the input potential as the power supply to load
input terminals of the CA3080A to the 200pF storage capacitor resistor RL. This load current is increased by the multiplica-
when the CA3080A is strobed off. Figure 32 shows dynamic tion factor R2/R1, when the load current is monitored by the
characteristic waveforms of this sample-and-hold system. power supply meter M. Thus, if the load current is 100nA,
with values shown, the load current presented to the supply
will be 100µA; a much easier current to measure in many
systems.
R1
10kΩ
+15V
R2
IL 0.1µF
R1
7
3 + R2
M CA3140 6
0.1µF 10MΩ IL
2 -
4
POWER 1
Top Trace: Output; 50mV/Div and 200ns/Div SUPPLY 5 RL
Bottom Trace: Input; 50mV/Div and 200ns/Div 100kΩ
4.3kΩ
-15V
Note that the input and output voltages are transferred at the
same potential and only the output current is multiplied by
the scale factor.
2-141
CA3140, CA3140A
R2 +15V
5kΩ +15V
0.1µF
100kΩ 7 SIMULATED
R1 0.1µF 3 LOAD
7 +
2 -
10kΩ CA3140 6
CA3140 6
2 -
3 + 1N914 100pF 2kΩ
4 4
5 10kΩ
1
8 R3
PEAK 0.1µF
ADJUST
100kΩ -15V
10kΩ BW (-3dB) = 4.5MHz
OFFSET
SR = 9V/µs
ADJUST 2kΩ
R2 R3
GAIN = ------- = X = ----------------------------------
R1 R1 + R2 + R3 0.05µF
2
R3 = ---------------- R1
X+X
1–X
5kΩ R2
FORX = 0.5 ------------- = -------
10kΩ R1
0.75
R3 = 10kΩ ---------- = 15kΩ
0.5
20Vp-p Input BW(-3dB) = 290kHz, DCOutput (Avg) = 3.2V
+15V
0.01µF
RS 7
3 +
1MΩ NOISE VOLTAGE
CA3140 6
OUTPUT
2 -
4 (B) INPUT-OUTPUT DIFFERENCE SIGNAL
0.01µF
30.1kΩ SHOWING SETTLING TIME
(measurement made with Tektronix 7A13 differential amplifier)
-15V
Top Trace: Output Signal; 5V/Div and 5µs/Div
BW (-3dB) = 140kHz
1kΩ Center Trace: Difference Signal; 5mV/Div and 5µs/Div
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT ) = 48µV TYP. Bottom Trace: Input Signal; 5V/Div and 5µs/Div
FIGURE 35. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR FIGURE 36. SPLIT SUPPLY VOLTAGE FOLLOWER TEST CIR-
WIDEBAND NOISE MEASUREMENT CUIT AND ASSOCIATED WAVEFORMS
2-142