1.

Norton’s theorem states that a complex network connected to a load can be replaced with an
equivalent impedance
(A) in series with a current source (B) in parallel with a voltage source
(C) in series with a voltage source (D) in parallel with a current source

15 3
2. A silicon bar is doped with donor impurities ND = 2.25 x 10 atoms / cm . Given the intrinsic
10 -3
carrier concentration of silicon at T = 300 K is ni = 1.5 x 10 cm . Assuming complete
impurity ionization, the equilibrium electron and hole concentrations are
16 -3 5 -3
(A) n0 = 1.5 x 10 cm , p0 = 1.5 x 10 cm
10 -3 15 -3
(B) n0 = 1.5 x 10 cm , p0= 1.5 x 10 cm
15 -3 10 -3
(C) n0 = 2.25 x 10 cm , p0 = 1.5 x 10 cm
15 -3 5 -3
(D) n0 = 2.25 x 10 cm , p0 = 1 x 10 cm
3. In CMOS technology, shallow P-well or N-well regions can be formed using
(A) low pressure chemical vapour deposition
(B) low energy sputtering
(C) low temperature dry oxidation
(D) low energy ion-implantation

4. Let x[n] = x[-n]. Let X(z) be the z-transform of x[n]. If 0.5 + j 0.25 is a zero o X(z), which one of
the following must also be a zero of X(z).
(A) 0.5 - j0.25 (B) 1/(0.5 + j0.25)
(C) 1/(0.5 - j0.25) (D) 2 + j4
5. The natural frequency of an undamped second-order system is 40 rad/s. If the system is
damped with a damping ratio 0.3, the damped natural frequency in rad/s is .
(A) 38.15 rad/sec (B) 32.25 rad/sec
(C) 35.28 rad/sec (D) 30.50 rad/sec

6. An LTI system with unit sample response h(n) = 5δ[n] − 7δ[n − 1] + 7δ[n − 3] − 5δ[n − 4] is a
(A) low pass filter (B) high pass filter (C) band pass filter (D) band stop filter

7. An n-channel enhancement mode MOSFET is biased at VGS > VTH and VDS > (VGS − VTH),
where VGS is the gate to source voltage, VDS is the drain to source voltage and VTH is the
threshold voltage. Considering channel length modulation effect to be significant, the MOSFET
behaves as a ______
(A) Voltage source with zero output impedance
(B) Voltage source with non-zero output impedance
(C) Current source with finite output impedance
(D) Current source with infinite output impedance
8.In the figure, D1 is a real silicon pn junction diode with a drop of 0.7V under forward bias condition
and D2 is a zener diode with breakdown voltage of −6.8V. The input Vin(t) is a periodic square
wave of period T, whose one period is shown in the figure.

Assuming 10 τ ≪ T. Where τ is the time constant of the circuit, the maximum and minimum values of
the output waveform are respectively?
(A) 7.5V and −20.5V
(B) 6.1V and −21.9V
(C) 7.5 V and −21.2V
(D) 6.1V and −22.6V

9.For the circuit shown in figure, P and Q are the inputs and Y is the output.

The logic implemented by the circuit is

(A) XNOR
(B) XOR
(C) NOR
(D) OR

10.An npn bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across
the base-collector junction is increased. Then
(A) the effective base width increases and common-emitter current gain increases
(B) the effective base width increases and common emitter current gain decreases
(C) the effective base width decreases and common-emitter current gain increases
(D) the effective base width decreases and common-emitter current gain decreases

11. Assuming that transistors M1 and M2 are identical and have a threshold voltage of 1V, the state of
transistors M1 and M2 are respectively

(A) Saturation, Saturation

(B) Linear, Linear
(C) Linear, Saturation
(D) Saturation, Linear

12. A programmable logic array (PLA) is shown in the figure.

The Boolean function F implemented is

(A) PPQPR + PPQR + PQPRP
(B) (PP + QP + R)(PP + Q + R) + (P + QP + RP)
(C) PPQPR + PPQR + PQPRP
(D) (PP + QP + R)(PP + Q + R) + (P + QP + R)

13. Which of the following statement is incorrect?

(A) Lead compensator is used to reduce the settling time.
(B) Lag compensator is used to reduce the steady state error.
(C) Lead compensator may increase the order of a system
(D) Lag compensator always stabilizes an unstable system.

14.In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The
present input condition is: P = Q = ‘0’, If the input condition is changed simultaneously to P = Q
= ‘1’, the outputs X and Y are

(A) X = ‘1’, Y = ‘1’

(B) either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’
(C) either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’
(D) X = ‘0’, Y = ‘0’

15.The Miller effect in the context of a Common Emitter amplifier explains

(A) an increase in the low-frequency cutoff frequency
(B) an increase in the high-frequency cutoff frequency
(C) a decrease in the low-frequency cutoff frequency
(D) a decrease in the high-frequency cutoff frequency

16.For the operational amplifier circuit shown, the output saturation voltages are ± 15V. The upper and
lower threshold voltages for the circuit are, respectively.

(A) +5 V and − 5V
(B) +7 V and − 3V
(C) +3V and − 7V
(D) +3V and − 3V
17.The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an
instruction is 1.4 μs, then the number of T-states needed for executing the instruction is
(A) 1
(B) 6
(C) 7
(D) 8

18. A half wavelength dipole is kept in the x-y plane and oriented along 45° from the x-axis. Determine
the direction of null in the radiation pattern for 0 ≤ ϕ ≤ π. Here the angle θ(0 ≤ θ ≤ π) is
measured from the z-axis, and the angle ϕ(0 ≤ ϕ ≤ 2π) is measured from the x-axis in the x-y
plane.
(A) θ=90°, ϕ=45°
(B) θ=45°, ϕ=90°
(C) θ=90°, ϕ=135°
 (D) θ=45°, ϕ=135°
19. In binary frequency shift keying (FSK), the given signal wave forms are u0(t) = 5 cos(20000πt) ; 0 ≤
t ≤ T, and u1 (t) = 5 cos(22000πt) ; 0 ≤ t ≤ T, where T is the bit-duration interval and t is in
seconds. Both u0(t) and u1(t) are zero outside the interval 0 ≤ t ≤ T. With a matched filter
(correlator) based receiver, the smallest positive value of T (in milliseconds) required to have
u0(t) and u1(t) uncorrelated is
(A) 0.25 ms
(B) 0.5 ms
(C) 0.75 ms
(D) 1.0 ms
20. Consider a wireless communication link between a transmitter and a receiver located in free space,
with finite and strictly positive capacity. If the effective areas of the transmitter and the receiver
antennas, and the distance between them are all doubled, and everything else remains
unchanged, the maximum capacity of the wireless link
(A) increases by a factor of 2
(B) decreases by a factor of 2
(C) remains unchanged
(D) decreases by a factor of √2