Front-End IC For INO ICAL Detector

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Front-end IC for INO ICAL Detector

EE6326: Integrated Circuit Design and Testing
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Nagendra Krishnapura
https://www.ee.iitm.ac.in/∼nagendra/
Department of Electrical Engineering

Indian Institute of Technology, Madras
Chennai, 600036, India
July-November 2018
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Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

. System block diagram
SCLK
Bias Gain Vcomp Rterm FRAME
gen. cal. gen. cal. SPI SDIN
SDOUT
Rterm
8x inputs
SCLK
8x LVDS gen. cal. gen. cal. SPI SDIN

SDOUT
outputs Rterm
8x inputs
8x LVDS
outputs
l Input
buffer
VGA Comparator Pulse
stretch
LVDS
driver
Input VGA Comparator Pulse LVDS 8x
buffer stretch driver 9:1

MUX
Cross Analog
analog
output
connect buffer
8x
9:1 analog
MUX output
Cross Analog
connect buffer
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. Input buffer
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
Input VGA Comparator Pulse LVDS
buffer stretch driver
8x
9:1 analog
MUX output
Cross Analog
connect buffer
Zero input common-mode voltage Gain ∼ 1

50 Ω termination from each input to ground Bandwidth > 1 GHz
Input termination trim Single-ended input
High input impedance mode Differential stage used for symmetry
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. VGA
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
Gain > 100 in the worst case Output ∼ 200 mV peak

Variable gain •
Bandwidth ∼ 500 MHz •
Digitally programmable gain (up to 100s) •
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. Comparator
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
Continuous-time comparator •
20-100 mV threshold in 10 mV steps •
Hysteresis < 10 mV •
• •
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. Pulse stretching
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
Pulse stretching to 100 ns width •

Optional; Should have a bypass •
• •
• •
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. LVDS buffer
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
LVDS outputs; ±200 mV •

Internal termination? •
• •
• •
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. Front-end processing slice
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
Front-end amplifier and comparator •

8 repeated units •
• •
• •
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. Analog output path
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
Analog output of one of the slices selected •

Diagnostic purposes •
Output impedance trim •
• •
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. Direct path and crossover
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
Direct path to de-embed buffer TF •

Cross connect to eliminate feedthrough •
• •
• •
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. Serial Peripheral Interface (SPI)
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
Digital control of all blocks •

2.5 V external I/O •
• •
• •
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. Broad specifications
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
8 channels—VGA, comparator, LVDS buffer 1.2 V for most core circuitry, LVDS buffers
Analog monitoring output 2.5 V for external digital I/O
1.2 V, 2.5 V supplies 2.5 V for switches, analog output buffer
Front-end bandwidth > 350 MHz Power dissipation: As low as possible
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. Broad specifications
SCLK
SDOUT
Rterm
8x inputs
8x LVDS
outputs
8x
9:1 analog
MUX output
Cross Analog
connect buffer
Fully differential realization All blocks should have a power down signal
Option for single-ended/differential input •
• •
• •
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. VGA: Starting point
Vdd
M7 M8
VGA M5 M6
Vbpc
ip op RL RL
vip vop om op
vim im om vom
Vbnc
M3 M4
as many stages as required
ip M1 M2
im
M0
Vss
Multi-stage open loop amplifier Lmin for M1−8 , 2Lmin for M0

Choose # stages for gain, bandwidth ∼ 25µA/µm for nMOS, 1/3× for pMOS
Differential pair with active load 200µA tail current
Cascodes for both Set Vbpc and Vbnc externally
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. VGA: Starting point
Vdd
M7 M8
VGA M5 M6
Vbpc
ip op RL RL
vip vop om op
vim im om vom
Vbnc
M3 M4
as many stages as required
ip M1 M2
im
M0
Vss
Simulate a cascade of large number of stages

Adjust RL , # stages for desired gain, bandwidth
Use triple-well (BPW) nMOS devices in the VGA for greater isolation from the substrate
•
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. VGA: Generating the input common mode and feeding the input
Vdd Vdd
M7r M7 M8
M5 M6
Vbpc
RL RL
Vicm om op
Vbnc
M3 M4
vip vim
M1r + v + –v ip M1 M2
− i − i
im
Vbn0 M0r + V Vbn0 M0
− icm
Vss Vss Vss
Cascade of identical stages: Input common mode = Output common mode

Generate input common mode using a replica circuit (approximate)
Output common mode = Vdd − VSG7
M0r , M1r , M7r : Replicas of M0 , M1 , M7 ⇒ Same current density
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. Generating Vbn0
Vdd Vdd
I0 M7r M7 M8
M5 M6
Vbpc
RL RL
Vicm om op
Vbnc
M3 M4
M10 M1r ip M1 M2
im
M0r
M00 Vbn0 Vbn0 M0
Vss Vss
Single ideal reference current I0 (Will be removed later)

M10 used to set identical VDS for M00 and M0r
M10 may not be in saturation if VGS of M00 is too small
•
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. Generating Vbn0
Vdd Vdd
I0 M7r M7 M8
M5 M6
Vbpc
RL RL
Vicm om op
Vbnc
M3 M4
M1r ip M1 M2
+
im
M0r
M00 Vbn0 Vbn0 M0
Vss Vss
Single ideal reference current I0 (Will be removed later)

Opamp used to set identical VDS for M00 and M0r
More precise setting; But needs an opamp
•
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. Generating Vbpc and Vbnc
Vdd Vdd
I0 M7r M7 M8
Vbnc
Rx M5 M6
Vbpc
RL RL
Vicm om op
Ry Vbnc
M3 M4
Vbpc
M10 M1r ip M1 M2
im
M0r
M00 Vbn0 Vbn0 M0
Vss Vss
Vbpc < Vicm and Vbnc > Vicm for keeping M7 and M1 in saturation respectively
Use Rx and Ry to generate required offsets
Will have to made robust over process and temperature
•
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. Increasing Vocm
Vdd Vdd
I0 M7r M7 M8
Vbnc
Rx M5 M6
Vbpc
RL RL
Vicm om op
Ry Vbnc
M3 M4
Vbpc
M10 M1r ip M1 M2
im
M0r
M00 Vbn0 Vbn0 M0
Vss Vss
Common mode current Icm through RL

Vocm changes from Vdd − VSG7 to Vdd − VSG7 + Icm RL /2
•
•
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. Other tweaks
Vdd Vdd
I0 M7r M7 M8
Vbnc
Rx M5 M6
Vbpc
RL RL
Vicm om op
Ry Vbnc
M3 M4
Vbpc
M10 M1r ip M1 M2
im
M0r
M00 Vbn0 Vbn0 M0
Vss Vss
Low VT device for M3,4 to reduce constraints on Vbnc , M1,2

Low VT device for M5,6 to reduce constraints on Vbpc , M7,8
Low VT device for M1,2 to increase VDS of M0
But, low VT device ⇒ slightly lower bandwidth
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. Input buffer
I0 I0 I0
op om op
ip M11 M12 im ip M11
Rterm Rterm Rterm
pMOS source follower

Allows 0 V input common mode voltage
Pseudo-differential structure
Start with same size/current as in VGA cells
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. Input buffer
Vdd Vdd Vdd

I0 I0 I0
op op op
+ ∆V = V – V Rx
− icm SG11
ip M11 ip M11 ip M11
Vss Vss Vss

Rterm Rterm Rterm
Output common mode = VSG11 ; Has to be Vicm

Introduce a voltage drop Vicm − VSG11
Realize using a variable resistor
Structure of Rx needs some optimization
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. Input buffer
Vdd Vdd Vdd

I0 I0 I0
op op op
Rx Rx Rx
ip M11 ip ip
M11 M11
Vss Vss Vss
Rterm Rterm Rterm
Bulk can be tied to source or output node

Analyze/simulate both alternatives and choose the better one
•
•
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. Input termination
ip
fixed
R0
R1
variable fixed
variable
RN R1 R0
ip
ip M11
RN
Vss Vss Vss
Rterm
Polysilicon resistor with switches

Rmin to Rmax in 8 or 16 equal steps
Biased near ground ⇒ nMOS switches
Should be able to realize 50 Ω over all process and temperature corners
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. Analog output buffer
High voltage device Vddh

M0
Vddh
M0
ip
VGA cells, progressively scaled up M1 M2
ip
M1 M2 im
Rcm
M3 M4
im
om op om op
25Ω 25Ω 25Ω 25Ω
Vss Vss
Gain ∼ 1; Should accept ∼ 200 mV peak signal

25 Ω load (Doubly terminated transmission line)
Driven from VGA output ⇒ Needs a predriver
Predriver: Progressively scaled up VGA cells
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. Analog output buffer
High voltage device Vddh

M0
Vddh
M0
ip
VGA cells, progressively scaled up M1 M2
ip
M1 M2 im
Rcm
M3 M4
im
om op om op
25Ω 25Ω 25Ω 25Ω
Vss Vss
Input common mode = Vicm ; Use HV pMOS diff. pair; LV for cascode
Bias current: Large enough to support 200 mV swing across 25 Ω
Devices: Sized to accommodate 200 mV input swing
Initial design: Use a simple current mirror for biasing
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. Comparator
Vdd
M5 M6 M9 M10
op
om
RL RL
ip M1 M2 refp refm M3 M4 im M7 M8
Vbn0 M01 Vbn0 M02

Vss
differential difference amplifier latch
Differential difference structure

Latch for some hysteresis
Initial design: Use same sizes/currents as in VGA cells
Start without the latch; Set RL for high gain; Add the latch and tweak
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. LVDS buffer
Vdd
Vbp0
4mA
progressively scaled
inverters
op 100Ω om
ip im
4mA
Vbn0
Vss
LVDS: ±400 mV across a 100 Ω differentially connected load

Current sources on top and bottom steered into the load
Initial design: Differential pairs sized to switch ∼ 4 mA into the load
•
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. Analog MUX
s1
ip
1 VGA cells, progressively analog
im scaled up buffer
s2 s1
ip ip
2
im im
s1
CL
s9
ip
9
im
Switches to connect LVDS output to a common node

LV pMOS switches / HV nMOS switches operating from 2.5 V supply
May have to switch in dummy capacitors to keep all slices identical when MUX is used
Cross connect may be implemented similarly in one of the pre-driver stages
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. Bias generator
Vdd
M7r
Vbnc
Rx Vbpc
more sources
Vref/R0
−
as required
V’icm
more current sources

Vicm
Vref
Ry Vbnc
modified
VGA cell Vbpc
as required
for opamp M10 M1r Vicm
R0
M0r Vbn0
M00
Vss
master bias generator VGA/local bias generator more precise
(1 per chip) (1 per slice) replica for Vicm
Single external reference Vref ; external reference resistor Rref

Hierarchical bias generation; Mostly based on replicas
Internal resistor trimmed to external resistor
Bias for HV stages generated using HV devices
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. Threshold generator
Vdd
M7 M8
M5 M6
Vbpc
RL RL
refm refp
Vss
digitally controlled
current sources
Top part same as the VGA ⇒ same common mode voltage

Digitally controlled current sources from the bottom to generate differential threshold
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•
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Front-End IC For INO ICAL Detector

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Front-End IC For INO ICAL Detector

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Front-end IC for INO ICAL Detector

Department of Electrical Engineering

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

8x LVDS gen. cal. gen. cal. SPI SDIN

buffer stretch driver 9:1

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Zero input common-mode voltage Gain ∼ 1

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Gain > 100 in the worst case Output ∼ 200 mV peak

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Pulse stretching to 100 ns width •

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

LVDS outputs; ±200 mV •

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Front-end amplifier and comparator •

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Analog output of one of the slices selected •

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Direct path to de-embed buffer TF •

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Digital control of all blocks •

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Multi-stage open loop amplifier Lmin for M1−8 , 2Lmin for M0

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Simulate a cascade of large number of stages

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Cascade of identical stages: Input common mode = Output common mode

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Single ideal reference current I0 (Will be removed later)

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Single ideal reference current I0 (Will be removed later)

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Common mode current Icm through RL

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Low VT device for M3,4 to reduce constraints on Vbnc , M1,2

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

ip M11 M12 im ip M11

Rterm Rterm Rterm

pMOS source follower

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Vdd Vdd Vdd

ip M11 ip M11 ip M11

Vss Vss Vss

Output common mode = VSG11 ; Has to be Vicm

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Vdd Vdd Vdd

Bulk can be tied to source or output node

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Polysilicon resistor with switches

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

High voltage device Vddh

Gain ∼ 1; Should accept ∼ 200 mV peak signal

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

High voltage device Vddh

Nagendra Krishnapura https://www.ee.iitm.ac.in/∼nagendra/ Front-end IC for INO ICAL Detector

Vbn0 M01 Vbn0 M02

Differential difference structure