MMIC Processing

Dr. R. E. Lehmann
EERF6396
University of Texas at Dallas
 MMIC Foundry
• Capabilities
– Do they have the technologies you need?
• SiGe, SiC, CMOS, LDMOS, etc.
• GaAs, GaN, InP, pHEMT, mHEMT, PIN diode
– Do they have the required test capabilities?
• On-wafer DC test (100% or sample (coupon) testing)
• On-wafer RF test (100% or sample)
– Do they offer packaging capability, singulated bare die
or just completed full wafers?
– What reliability testing is available or has been done?
• Mil-spec
• Space qualified
 MMIC Foundry (cont’d)
• Design support
– Do they offer foundry service training?
– What type of design support do they offer?
• Foundry support engineers (applications engineers)
• Full custom design services (ASIC design – Application Specific
Integrated Circuit design)
• Types of Foundry Engagements & Cost
– Prototype designs
• “Pizza” mask – where you share part of a wafer with other foundry
customers using the same technology. (least expensive; receive
small sample of MMICs)
• Full foundry design – where you buy one or more wafers from the
beginning. (moderate cost; receive more MMICs)
• Full custom design (ASIC) – Experienced foundry engineers design
MMIC to your custom specifications. (most expensive)
 PDKs
• PDK = Product Design Kit
– Provides information to the designer to perform
MMIC design
• Transistor models (with statistics)
• Layout design rules
• Interfaces directly with major CAD software (AWR, ADS,
Mentor Graphics, for example)
• Tools to perform layout verification and design rule
checking (DRC)
 Technologies
• Materials
– Diffused
• Si, SiGe
– Implanted
• GaAs MESFET (n-type, p-type, E-D combination)
– Epitaxy
• GaAs, GaN, Inp
• MBE = Molecular Beam Epitaxy (pHEMT, mHEMT, HBT)
• MOCVD = Metal Organic Chemical Vapor Deposition
(GaAs PIN diodes)
 MBE Machine
Depositing one atomic layer at a time
Transistor Scaling for RF Output Power
• Optimum power-added efficiency (PAE) is
achieved by scaling device sizes on a MMIC
– For FET-type transistors (pHEMTs, etc.) gatewidth is
scaled up for increasing RF output power.
– For HBTs total emitter periphery is scaled up for
increasing RF output power.
• Total RF output power is proportional to DC input
power.
– Gatewidth or emitter periphery is added in parallel to
achieve higher DC current capability
– Device equivalent circuit models can then be
proportionately scaled to the optimum size required.
 Power Amp Design Example
PDC1 PDC2

RF Pin RF Pout

Summary
Power (dBm) 15 27 37 37
Power (W) (0.03) (0.5) (5.0) (5.0)
Gain (dB) 12 10 22
VD (V) 8 8 8
ID (mA) 300 1200 1500
PDC (mW) 2400 9600 12000
PAE (%) 19.5 47.0 41.5
Power Density (W/mm) 0.5 0.5
Gatewidth (mm) 1.0 10.0 11.0
 Transistor Layout
S

S
G G D

One-finger transistor Multi-finger transistor

Wf = 200 µm W = N x Wf = 4 x 200 µm = 800 µm
 S
1-cell  Multi-cell Transistor

S
G D

G D

G D
S

S
W = 800 µm W = 1600 µm = 1.6 mm
 0.5μm HFET Family TGF4260
9.6 mm
Performance/Features
• RF Performance DC to 12GHz
• Pout from 700 mW to 5 W
• PAE to 55%, 8V Bias
• 12mm-24mm devices also available
Applications
• High Efficiency Power Amplifiers for Cellular Base Stations TGF4250
• High Dynamic Range LNA/Post Amplifiers for Base Station 4.8 mm

2.362 mm
Frequency Converters
TGF4240
2.4 mm

1.372 mm
TGF4230-EEU
1.2 mm
1.016 mm
0.737 mm

0.609 mm 0.609 mm 0.609 mm 0.609 mm

Courtesy of TriQuint Semiconductor

TriQuint Output Power (W/mm)
 MMIC Yield
• Total MMIC yield is comprised of many yields:
– Processing yield, yproc
– DC yield, ydc
– RF yield, yrf
– Saw/scribe yield, ys
– Visual yield, yv
– Packaging yield, ypkg
• Total yield = yproc x ydc x yrf x ys x yv x ypkg
– Ex: Total yield = (0.99)6 = 94.1%
– = (0.95)6 = 73.5%
– = (0.90)6 = 53.1%
 Saw/Scribe
• Required space must be included between all edges of all MMICs on a
wafer (dimensions are foundry dependent)
• All saw/scribe lines must be aligned.
Allowed Not Allowed
 Layout Checking
• DRC = Design Rule Checking
– Checks to ensure all structures conform to the specified design rules.
Specifically it checks minimum feature size. (e.g., distance between
adjacent structures in the layout)
– DRC cannot detect errors that are electrical in nature if they do not
break a processing (fabrication) rule.
– Example:
DRC will catch this error DRC will not catch this
because it is smaller than error because no
the allowable spacing processing rule is broken.
(say 4 μm)

2 μm 6 μm
 Layout Checking (cont’d)
• ERC = Electrical Rule Checking
– Examines the layout for electrical connectivity.
– Will check for unconnected inputs, shorted outputs and typical ground
and power connections.
• LVS = Layout versus Schematic
– Checks for consistency between the sizes and connectivity of the
components on the layout compared to the electrical schematic.
• Visual Checking
– MMIC layouts can also be inspected manually using over-size plots
which can be magnified up to 1000x their actual size.
– Multiple people can review the plots simultaneously.
 MMIC Power Amplifier

Courtesy of TriQuint Semiconductor

 MMIC Power Amplifier

Courtesy of TriQuint Semiconductor

 Typical MMIC Fabrication Steps
• Epitaxy, mesa etch or ion implantation
• Ohmic metal (source & drain contacts)
• Gate recess
– Single or dual recess
– Transistor DC parameters (Idss, Vpo) are controlled with this
step
• Gate formation
– Optical
– E-beam defined
• First-level metal (thin layer, typically < 2μm)
• Resistors
• Passivation (nitride)
– MIM Capacitors
– Passivation to protect transistors
• Second-level metal (thicker, typically > 4μm)
• DC front-side test

Photo ref: Electrical and structural characterization of AlGaN/GaN field-effect transistors

with recessed gate
M. Mikulics a, A. Foxa, M. Marso b, D. Grützmacher a, D. Donoval c, P. Kordos c,d,*
 MMIC Fabrication Steps (cont’d)
• Backside processing
– Vias through substrate are produced with
reactive ion etching (RIE)
– Metal is evaporated and plated on the
backside to achieve electrical contact
through the via to the top side and to
provide back-side RF (and DC) ground.
• RF probe
– RF auto-probe uses Ground-Signal-
Ground (GSG) probes.
– Chips that pass RF specs are called
“known-good die” (KGD)
• Die separation (saw/scribe)
• Visual inspection
• Package
 Power Handling Capability
• How much current can a microstrip
transmission line handle?
• Consider cross-section and conductivity of
metal layers.
– Use a maximum current of 10mA/μm of
microstrip line width for this project. (25μm wide
line can handle 250mA of current).
– Ex: for a high-power amp which requires 1A of DC
current, the on-chip DC bias line needs to be
100μm wide (minimum)
 Cost
• Standard Products
– COTS (Commercial Off-the-Shelf) available MMICs
– Priced to what the market will bear
• Foundry Service
– Partial wafer
– Several wafers
– Production
– The more you buy, the cheaper
per MMIC (or wafer) will be.
– The smaller the chip, the more chips
you will get on each wafer.