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Timer IC 555
Syllabus
CONTENTS :
The Fig 9.1.1 shows the part of the R-S flip-flop circuit.
It can be observed that output remains high for the time which is
required by the capacitor to charge upto control voltage, through
R. Thus by varying R or C, the output pulse width can be varied.
This is the working principle of timer IC 555.
The Fig 9.2.1 (a) and (b) show the pin diagram and the
block diagram of the IC NE 555 timer.
Pin 2 : Trigger
Pin 3 : Output
PM 4 : Reset
Pin 6 : Threshold
• In short,
EQ
Pin 7 : Discharge
Review Questions
9.3.1 Operation
Key Point Here, timing interoal ‘t’ is kept slightly larger than the
time period T of the trigger input signal.
The output will remain high for the period equal to timing
interval.
As timing interval is greater than time period of the trigger
input, output will still be high when the second negative
going pulse occurs.
Key Point
Key Point : It may be noted from the output waveform that the
pulse duration varies according to the modulating signal level, but
the frequency of the output pulses is same as that of the trigger
input signal.
If input signal again goes low before the 555 completes its
timing cycle, the voltage across C is reset to 0.7V.
9.4.1 Operation
This resets the flip-flop hence Q goes low and Q goes high.
EQ
9.4.4. Application of Astable Multivibrator
EQ
EQ
But if duty cycle less than 50% is required, the circuit can
be modified as shown in the Fig. 9.4.11.