ASIC Backend Flow using Synopsys Astro

Seong Chew, Lim

Integrated Circuit Design Services Sdn. Bhd.

seongchew.lim@icdsgroup.com

ABSTRACT

Using Synopsys Astro place n route tool for ASIC physical design flow is presented in this
paper. The paper will introduce the Astro methodology flow from synthesized netlist to gds. The
paper will cover Design database setup, floorplan, power pre-route, placement, clock tree
synthesis, and route phases. This paper will also cover some of the physical design sharing like
power pre-route pattern and scripts that being used for physical design and also some
introductions on the clock timing. The paper will not cover topics like IR drop, Power Leakage
and Cross Talk issues that are critical to the UDSM design.
1.0 Introduction
While there are various commercial Place n Route tools available in the market, each tool might
be having different tool flow varies from the algorism they are using. Physical designer is
eagerly hoped for One-stop design platform in order to save the time and effort during design
cycle. Synopsys IC Compiler is one of the choices that can provide the one-stop solution. By
using IC Compiler, Astro will be able to workout together with Physical Compiler to meet
timing for high complexity of modern ASIC design. In this paper, I will purely discuss the Astro
Methodology backend flow.

The flow used in this paper has made several ASIC designs success. However, the flow may
vary according to various complexities of the design and analysis required on the ASIC. To
identify the Place n Route constraints and issues upfront, one can run additional ‘prototyping
flow’ that give fast result analysis. For some complexity design that difficult to meet timing, one
can run more optimization cycles to meet timing. Synopsys RCMD Flow is also a good reference
on Astro script-based methodology flow for the user to refer.

Some physical design sharing and useful scripts will be introduced here. The power structure for
the Hard Macros that used in SoC could affect the Top Level power planning. Example: How the
power ports in Hard Macros are being connected in Top level. (Ring, horizontal stripes or
vertical stripes) Also, in solvnet, you might be able to find some useful scripts that can help
improve design efficiency like ‘schAddTextToPads’ scheme code & perl script.

The Astro methodology flow will cover the topics below (as shown in figure 1):
a) Design Input Preparation: IO information to create TDF file, Estimate Die Size &
Power required for the design.
b) Design Database Setup: Setup the Design Library (including reference libraries)
and read-in netlist & design constraints, expand & bind netlist, reserve
hierarchical information and timing setup.
c) Floor planning: Create floor plan based on result from die size estimation, read in
the tdf file that created accordingly with the IO information, and also Macros
placement.
d) Power Pre-route: For those designs with high consuming of time on power pre-
route, it is recommended to put the power pre-route process after clock tree
synthesis (CTS). That is because the macro placement (floorplan) may change
frequently before that, in order to get better timing result. However, if the
floorplan has been finalized, the physical designer can start doing power pre-route
here.
e) Placement: this include Pre-place optimization, In-place optimization, and Post-
place optimization phase1.
f) Clock Tree Synthesis: This will include Clock Tree Synthesis & Optimization; it
will also cover Post-place optimization phase 2 (Post-CTS optimization).
g) Route: This includes clock route, signals route and antenna.
h) Post-route CTO and optimization: workout together with Star-RCXT to ensure
the timing result is correlating with Primetime.
i) Chip finishing: Fill Notch & Gap, Filler Cells, Metal Slots and Pad Text.

SNUG Singapore 2005 2 ASIC Backend Flow using Synopsys Astro

 Gate level Verilog netlist Design Constraints

Floorplanning
Define Die Size
IO placement
Macro placement
Power planning or Pre-route

Disconnect Scan Chain

Pre Placement Optimization

Custom WLMs for DC
N optimization
Timing OK Or
Floorplanning

In-Place / Post Placement Optimization

Clock Tree Synthesis / CT Optimization
Scan Reconnect/Optimize
Post CTS Optimization Post Placement
Optimization
Or
N
Timing OK Post CTS Optimization
Or
Floorplanning
Route Clock Nets
Detail Route
Optimize Routing
Post Route CTO
Star-RCXT Extraction Verify Timing
Post Route Optimization
N Or
Timing OK
Floorplanning

Fill Gap/Notch

Star-RCXT Extraction

Static Timing Analysis

N Post Route Optimization
Chip Finishing Tasks Or
Timing OK ECO
Metal Slotting
Metal Fill
Verify DRC/LVS in gate level Chip Finishing Tasks

GDS Routed Parasitic File

Netlist 1
Figure (from Star-RCXT)

2.0 ASIC physical design flow using Synopsys Astro

SNUG Singapore 2005 3 ASIC Backend Flow using Synopsys Astro

 2.1) Place n Route Designer will first collect all the inputs needed for physical
design from front-end designer, system designer, library provider, and FAB.

a) Getting design related data – Chip / IP Information and special requirement

(E.g. clock requirement, pads/pins location requirement, and feature outline),
process technology, packaging information, target Die size and test
methodology information such as Scan Chain information and etc.

b) Getting Process Data files – make sure the technology file, TLU+ model
(Table Look Up), Star-RCXT nxtgrd and mapping file are corrects.

c) Getting Place n Route Design Input Data – Gate Level Netlist, Design
Constraint File, macros design models (such as lib / db, lef, gds and Milkyway
DB), and also the standard/IO cells design models. It will be good to have LM
view (Timing view in Milkyway database that created using .lib or .db format)
in order to have better correlation with Primetime.

2.2) Place n Route Process for ASIC Design (This will include Design
Planning, Design Implementation, Route & Chip Finishing, Astro top
level physical verifications and design output).

a) Design Planning Process

i. Design Database Setup – Import all the Place n Route design inputs
data to Astro.
The steps shall include:
1) Create Design Library
2) Add reference libraries
3) Read Gate level netlists
4) Expand netlist
5) Bind the netlist
6) Reserve and Mark hierarchical information
7) Read design constraint files
8) Timing environment setup & Place n Route option setup

ii. Floor-planning the physical design by define the die size, power
scheme, Pads/Pins locations and Macros placement. For die size, you
can refer to the result from die size estimation. The die size estimation
basically will calculate in both Core Limited and Pad Limited and see
which one the design is belongs to. For Power planning, you may need
to refer to power analysis tool result (E.g. Power compiler), and decide
the Ring width, Block ring width, and also Stripes number, width and
spacing in between. Once you have those numbers, you can do “Setup
floorplan” in Astro. For Pads/Pins locations definition, if you don’t
have tdf file, you can dump out the preliminary ‘tdf’ file from Astro
and then edit the ‘tdf’ file with desired location and sequence, and read
back into Astro database. The ‘tdf’ file consists of the boundary and

SNUG Singapore 2005 4 ASIC Backend Flow using Synopsys Astro

 pads/pins information. For Macro placement, if the design is
hierarchical, the place n route designer can group the hard-macros
according to the module, and place them near to the edge of the core
boundary, so it will not block the routing, and the length of the power
connections between hard-macros and Core Power Ring can be shorten
as well. Also, it will be good to place the hard macros in such a way
that the IO pins/ports are facing towards the CORE.

iii. After the Hard-macros placed, if the power pre-route is very time
consuming, the physical designer have the optional to perform this step
after clock tree synthesis phase. This is because the floor-plan may
have major changes if the timing margin given is very less and cause
difficulty to achieve timing target. If this is the case, we would not have
to spend extra time to redo the power pre-route. However, the physical
designer will need to do power planning upfront to reserve enough
room for power pre-route later.
If you need to do power analysis like Astro Rail, you will need to do
power pre-route earlier. Route the power rings, stripes, and follow-pins.
The width of the power bus must be big enough to give sufficient
power to the design. The power planning must be also aware of the IR
Drop and Electro-migration issues in the design.

b) Design Implementation Process: This part will cover Placement

Optimizations and Clock Tree Synthesis. It is a good practice to verify
timing within each stage so that the designer can predict and solve the
design issues upfront.
i. Physical Designer shall ensure timing setup within Astro is correct and
successfully read-in Design Constraint files.

ii. Disconnecting scan chain

Connections between scan inputs and outputs within a scan chain might
not be optimal for routing after placement. However, scan circuitry
might have timing violations, so Astro needs to optimize them as well.
Additionally, hold times need to be fixed after the scan flip-flops are
placed and the chain connections are optimized.
The preferred method is to disconnect the scan chain prior to pre-
placement optimization. This prevents pre-placement optimization from
touching or optimizing any elements in the scan chain during
optimization, because it must not disturb the disconnected elements if it
is to be able to retrace them later.
Disconnect the scan chain from the design with the following
information:
a. Number of scan chains in the chip design.
b. Type of scan flip flop used.
c. Input and Output ports of the scan chains.

SNUG Singapore 2005 5 ASIC Backend Flow using Synopsys Astro

 iii. Perform Pre-placement Optimization that do quick placement, high fan
out net synthesis, gate sizing and insertion, gate duplication, net
splitting, moving cells, max transition and max capacitance
optimization.

iv. Perform In-Placement Optimization, one can trade off between routing
& timing ratio in this process. You have the option of weighting cell
placement to optimize various factors of your design (Congestion,
Timing, Power, IR Drop, and Heat). In-Placement optimization
performs cell sizing, cell moving, cell bypassing, buffer/inverter
insertion, gate duplication, and net splitting optimization techniques.

v. Perform Post Placement Optimization, to fix the setup time and max
violations. (Hold time will be fixed after Clock Tree Synthesis is
completed and propagated clock being set)
During this step you achieve the most significant change to the placed
design (in terms of the number of inserted buffers and inverters, and
moved cells). You employ topology-based optimization methodology,
high fan-out net optimization algorithms, and different cell moving
techniques—as well as fast cell sizing—to achieve fast layout
optimization results

vi. Physical Designer shall ensure clock requirement information is

sufficient such as target clock skew and target insertion delay and the
designer shall understand the clock structure of the ASIC. Some
designs are required to set the sync pins in order to get good results
(E.g. set sync pin to prevent CTS engine perform clock balancing on
path that beyond register cell). The timing information for clock tree
synthesis is obtained from the SDC file. Some timing information can
be changed by set at the command line or by using Astro.
Perform Clock Tree Synthesis.

vii. Perform Clock Tree Optimization (CTO) for improve timing and skew.
Clock tree optimization is an important procedure in Astro clock tree
synthesis. It improves both clock skew and clock insertion delay by
performing buffer sizing, buffer relocation, gate sizing, gate relocation,
level adjustment, reconfiguration, delay insertion, dummy load
insertion, and balancing inter-clock delays. Set clocks propagated and
mark clock tree after CTS done.

viii. Perform Reconnect/Optimize Scan.

The preferred method of scan reconnecting and optimizing is to do so
after placement, when the clocks are inserted, and prior to post-CTS
optimization. This allows post-CTS optimization to optimize the chain
for timing as necessary.

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 ix. Perform Post CTS optimization to fix the timing violations. The
optimization targets are Setup, Hold, Max transition, Max capacitance
and Area Recovery.

x. Optional: More iteration of post placement optimizations shall improve

the design result further, if the timing result not good, performs Post-
placement optimization & Post CTS optimization again to fix timing
violations if necessary.

xi. Perform power pre-route on the design if you have not done so.

Note: In later released of binary versions, the Pre-place optimization, In-

place optimization, Post Placement Optimization Phase 1 and Post Placement
Optimization (Post-CTS optimization) are being combined into ‘Autoplace’
(astAutoplace).

c) Route Process and Chip Finishing

Before route, it is recommended to clean up all the timing violations upfront
and try to improve the slack by giving more margins. (Post route timing may
become worse)
The designer shall route clock nets and other critical nets prior to detail route
so that they can have better route quality.

In this paper, the detail route flow used is shown as below:

1) Global Route
2) astPostRouteOpt (GR)
3) Track Assignment
4) astPostRouteOpt (TA)
5) Detailed Route
6) astPostRouteOpt (DR)

It is better to have subsequence optimization after each Global Route, Track

Assignment, and Detail Route to help meeting the timing more easily after
detail route.
The physical designer will need to select the proper Routing Phase option at
the top of the astPostRouteOpt dialog box to specify which phase of the
routing flow you are in (Global Route, Track Assign, or Detail Route).

While perform ‘Optimize Routing’ can improve the timing significantly

sometimes, the physical designer is recommended to do so.

SNUG Singapore 2005 7 ASIC Backend Flow using Synopsys Astro

 You will need to run Post Route CTO in order to improve the clock skew and
insertion delay after route.

While the route flow has completed, the designer can extract the RC by using
Star-RCXT, and create Parasitic View for the Milkyway Database. By doing
this, Astro timing engine shall be able to calculate the timing more accurately
and give proper fix later. If there are still timing violations after the route
flow, you may try to do post route optimizations to fix them. In later released
of the binary versions, the post route optimizations (Post Route Optimization
and Advance Route Optimization) have been combined into one called
‘Detail Route Placement / Route Optimization’ (astPostRouteOpt “DR”).

Once the timings are met, the designer can do ‘Search & Repair’ with
Antenna fix option selected. If some antenna violations cannot be fixed, the
designer can add diode on the violation nets. Finally the designer can finish
all the tasks remaining like Add Filler Cells (Pad and Standard Cells), Metal
Slotting, Add Dummy Metals, and fill Notch & Gap.

d) Astro physical verification

Before doing physical verification sign-off (using Hercules or other physical
verification sign-off tools), the Place n Route designer shall do Astro Top
level DRC / LVS verification to clean up all the top level violations (E.g.
metals spacing, width, pin/port open and signals shorts). You may need to do
‘Verify PG Connectivity’ as well to detect those floating polygons if any.

e) Output from Astro

Finally, the designer can start generate the routed netlist, parasitic file (Using
Star-RCXT), and GDS database for final verification that include Static
Timing Analysis, Simulation, Logic Equivalence Check, and Physical
Verification.

2.3) Design ECO (Engineering Change Order) Flow – The user can use
either ECO-by-Change-File or ECO-by-Net-Compare to do ECO for
your design. For the detail ECO flow in Astro, please refer to Astro User
guides in SOLD.
The ECO should apply to the following:
a) After Design Verification, if there are design / timing issues, the netlist
will be changed in order to solve the issues, the Place n Route Designer
shall perform ECO for these changes.

b) During the Back-end Design Process, if the design needs to be changed,

the Place n Route Designer shall also perform ECO.

SNUG Singapore 2005 8 ASIC Backend Flow using Synopsys Astro

 The user has to do ‘ECO route’ after ECO-by-Net-Compare or ECO-by-
Change-File. After the ECO, timing maybe affected. But you can minimize
the effect by select ‘route modified nets only’ option during ECO route and
then run ‘search and repair’.

3.0) Physical Design sharing and useful scripts

3.1) Power strategic for hard-macro cells (e.g. memory cells)

During Hard-macro IP Design, or during generate memory cells from
memory compiler, you may have to decide what kind of power structure you
will implement in the ASIC. Some of the memory compilers offer power
stripes as optional power ports besides internal power ring to let the users
make power connections directly to the power stripes and yet to core. By
doing this, the user can give minimum width to the power ring and can save
the rooms being used for the internal power ring. For some of the big
memory cells, the power ring could cost a lot of spaces. Indeed, if the
memory cells have power stripe ports direct connect to the core; the designer
may not need to add the power ring. You can give the flexibility to Top level
designer for adding the Hard-macro block ring and define the width of the
block ring depends on the layout constraint. Sometimes, some designers will
use Top-level power stripes connect directly to the hard-macro stripe ports
without any Block ring.

Some of the memory compiler may design the power stripes in very high
congested structure (as shown in figure 2), meaning that the gap between
power stripes (or power ports) are pretty small, that may cause routing issues
when the Place n Route tools trying to connect all the memory power ports to
the Top level. Example like there may not have enough rooms for the
memory signals to route out; also, the top level routing may have problems
due to high-congested power connections. By solving these, the user can
choose to drop some of the extra power connections that connected from top
level to the power stripe ports in the memory cells.

SNUG Singapore 2005 9 ASIC Backend Flow using Synopsys Astro

 All the power ports in the
memory cell being
connected in top level

Figure 2

3.2) Scripts that can be a good reference to Astro users

The scripts can be written in scheme code, perl script, TCL and etc…
Some of the scripts that are proven to effectively cut down design cycle time
in the physical design flow.

a) One can be introduced here is “Astro Recommended Script-based

Methodology”, it is a sequence of the physical implementation steps, starting
with an existing floor-plan, that you can run with a command wrapper
interface. The methodology is a set of scripts that provide an automatic path
for successfully completing a physical implementation for most designs. For
detailed information, including how to set up the scripting environment,

SNUG Singapore 2005 10 ASIC Backend Flow using Synopsys Astro

 make edits, and run the methodology, see the “Astro Recommended Script-
based Methodology application note” in SolvNet.

b) Another script to be introduced here is Scheme script to add net name text to
I/O pads using combined scripts from scheme code
“scmAddTextToPads.scm” and perl script “scmAddTextToPads.pl” that
can be found in SolvNet. (Attached into this paper as well)

Below is how you can implement these scripts to your design:

Load the scheme file in Astro with the perl script in the local directory.
load "scmAddTextToPads.scm"
then you can run the scheme function from the Astro command line
scmAddTextToPads

Usage:
scmAddTextToPads "portName" "layerName" "textHeight" edgeOffset

portName = name of the port inside of the I/O pad to which the top
level net is assigned in the netlist.
layerName = name of layer text is to be added on
textHeight = height of text to be added, in microns
edgeOffset = Desired offset from the outside edge of the I/O pad.
(positive value puts it closer to the center, negative value
puts it outside the I/O pad boundary)

Example:
scmAddTextToPads "PAD" "METAL6" "10" 40

Notes:
1) This routine assumes that the I/O pad default orientation is vertical
with the bond opening connection at the bottom. If yours is different
than that, you need to modify the scheme. Look for the section where
the variable transcode is being tested. Change the value for the transcode
test to correspond to the correct pad orientation.

2) The scheme script assumes the perl script is in the local directory and
named scmAddTextToPads.pl. In the scheme script it is called with the line
(system "perl scmAddTextToPads.pl").
If the perl is not in the local directory, edit this line in the scheme to give it
the correct path to the perl script.

;-------------- scmAddTextToPads.scm -------------------------

(define scmAddTextToPads (lambda (portname layername txtheight edgeOffset)

(batchMode #t)
(setDisplayMode "QueryBoxes" #f )
(define layernum (dbGetLayerNumberFromName (dbGetCurrentLibId) layername))
(axgDumpFloorPlan)
(setFormField "Dump Floor Plan" "Output Filename" "pads.dump")
(setToggleField "Dump Floor Plan" "Type" "std cell placement" 0)

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 (setToggleField "Dump Floor Plan" "Type" "macro cell placement" 0)
(setToggleField "Dump Floor Plan" "Type" "row" 0)
(setToggleField "Dump Floor Plan" "Type" "track" 0)
(setToggleField "Dump Floor Plan" "Type" "region" 0)
(setToggleField "Dump Floor Plan" "Type" "Floor Plan group" 0)
(setToggleField "Dump Floor Plan" "Type" "Blockage/Density" 0)
(formOK "Dump Floor Plan")

(system "perl scmAddTextToPads.pl")

(define rfile (open-input-file "pads.txt"))

(define listp '())

(let (
(tmplist '())
(firstSpace 0) (mac 0) (pin 0)
)
(do (
(c (read-char rfile) (read-char rfile))
)
((eof-object? c)) ;Break loop at EOF
(cond
((and (not(char-whitespace? c)) (not(eqv? c #\newline)))
(cond
( (zero? firstSpace)
(set! tmplist (append tmplist (list c)))
)
(else
(set! tmplist (append tmplist (list c)))
)
)
)
((eqv? c #\newline)
(set! firstSpace 0)
(set! pin (list->string tmplist))
(set! listp (cons pin listp))
(set! tmplist '() )
)
)
)
(set! listp (reverse listp))
)
(define port portname)
(define cellId (geGetEditCell))
(for-each
(lambda (instanceName)
(let*
(
(cellInstId (dbGetCellInstByName cellId instanceName))
)
(db-foreach cellId cellInstId "portInst" portInstId
(let*
(
(netId (dbFetchObjectField cellId portInstId "netId"))
(netName (dbFetchObjectField cellId netId "netName"))

SNUG Singapore 2005 12 ASIC Backend Flow using Synopsys Astro

 )
(define portName (dbFetchObjectField cellId portInstId
"portInstMasterId"))
(define Name (dbFetchObjectField cellId portName "name"))
(if (equal? Name port)
(begin
(define net netName)
(define Bbox (dbFetchObjectField cellId cellInstId "bbox"))
(define transcode (dbFetchObjectField cellId cellInstId "transformCode"))
(define x2 (car(car (cdr Bbox))))
(define x1 (car (car Bbox)))
(define y2 (car(cdr(car(cdr Bbox)))))
(define y1 (car(cdr(car Bbox))))

; transcode 0 = no rotation
; transcode 2 = rotate 90 ccw
; transcode 4 = rotate 180
; transcode 6 = rotate 270 ccw

(if ( = transcode 0)
; Vertical pad with bond opening at the bottom
(begin
(define width (- x2 x1))
(define offset (/ width 2))
(define xl (+ offset x1))
(define yl (+ edgeOffset y1))
(define txtorient "rotate 90")
(define txtjustify "left-bottom")
)
)

(if ( = transcode 2)
; Horizontal pad with bond opening at right
(begin
(define width (- y2 y1))
(define offset (/ width 2))
(define xl (- x2 edgeOffset))
(define yl (+ offset y1))
(define txtorient "rotate 0")
(define txtjustify "right-bottom")
)
)

(if ( = transcode 4)
; Vertical pad with bond openeing at top
(begin
(define width (- x2 x1))
(define offset (/ width 2))
(define xl (+ offset x1))
(define yl (- y2 edgeOffset))
(define txtorient "rotate 90")
(define txtjustify "right-bottom")
)
)

SNUG Singapore 2005 13 ASIC Backend Flow using Synopsys Astro

 (if ( = transcode 6)
; Horizontal pad with bond opening at left
(begin
(define width (- y2 y1))
(define offset (/ width 2))
(define xl (+ edgeOffset x1))
(define yl (+ offset y1))
(define txtorient "rotate 0")
(define txtjustify "left-bottom")
)
)

(display "texting net ") (display "\"") (display net) (display "\"")
(display " of pad instance ") (display "\"") (display instanceName) (display "\"")
(newline)

(geAddText)
(setFormField "Add Text" "Layer" layernum)
(setFormField "Add Text" "Height" txtheight)
(setFormField "Add Text" "Text" net)
(setFormField "Add Text" "Transform" txtorient)
(setFormField "Add Text" "Justify" txtjustify)

(hiAddPoint (hiGetCurrentWindow) (list xl yl))

(formCancel "Add Text")
)
)
#t
)
)
)
) listp
)
(system "rm -rf pads.out")
(system "rm -rf pads.dump")
(system "rm -rf pads.txt")
(batchMode #f)
(setDisplayMode "QueryBoxes" #t )
)
)
;-------------end of scmAddTextToPads.scm------------------

#----------------scmAddTextToPads.pl-----------------------
open (fhandle, "< pads.dump") || die ("cant open the file \n");
open (fhandle1, "> pads.out") || die ("cant open the file \n");
while (<fhandle>) {

if ($_ =~ /\"/) {

print fhandle1 $';

print fhandle1 "\n";

SNUG Singapore 2005 14 ASIC Backend Flow using Synopsys Astro

 }
}
close fhandle;
close fhandle1;

open (fhandle, "< pads.out") || die ("cant open the file \n");
open (fhandle1, "> pads.txt") || die ("cant open the file \n");
while (<fhandle>) {

if ($_ =~ /\"/) {

print fhandle1 $`;

print fhandle1 "\n";
}
}
close fhandle;
close fhandle1;

#------------------end of scmAddTextToPads.pl------------------

3.3) Introduction on the clock timing

In this section I will give some introduction on Timing and Clock Tree
Synthesis and how both of them are relating to each other

a) What is setup time and hold time? How are they affecting the timing?
Setup time is the minimum time that a data input pin of a sequential device
must be stable before the clock transition.
Hold time is minimum time that a data input pin of a sequential device must
be stable after the clock transition.

Setup time is frequency dependent, unlike Hold time that is frequency

independent that the violations cannot be fixed by changing the frequency of
clock. (See from Equation (2) and Equation (3) on next page)

b) Clock tree synthesis and how is it affecting the timing

The relationship between clock skew and timing can be shown in equation
below:
Equation 1: t period >= t delay + t skew + t set up + t prop. delay

t period is the minimum clock period for the design.

t delay is the time taken by the clock to propagate from the root point, though
the longest path of the distribution network and reach the leaf node.

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 t skew is the clock skew that defined as the time from the arrival of the clock
to one leaf node until the arrival of the clock to the last leaf node.
t set up is the set up time for the leaf node that has the largest set up time
(assuming that the leaf node is edge triggered).
t prop delay is the propagation delay through the leaf node.

From the Equation (1), we can minimize t delay and t skew in order to achieve
target t period that is actually the target of the Clock Tree Synthesis. t set up and
t prop. delay can be minimized by tools for logic synthesis and also depends on
the manufacturing process in use.

The clock skew can affect the timing as shown in the 2 equations below:
Worst case – Setup
Equation 2: Clock skew + Tsetup + Datapath max <= clock period
Tsetup is the setup time of the endpoint
Datapath max is the maximum delay requirement between 2 sequential
elements plus clock-to-out time of the start-point.

Best case – Hold

Equation 3: Clock skew – Thold + Datapath min >= 0
Thold is the hold time of endpoint
Datapath min is the minimum delay requirement between 2 sequential
elements plus clock-to-out time of the start-point.

4.0 Conclusions and Recommendations

There are few discussions in this paper such as Astro Methodology Flow, physical design scripts
and some sharing on Place n Route design. Nevertheless, The flow and methodology may be
different based on the complexity and various design analysis required for the ASIC.
This paper may not be able to cover all the steps and commands in Astro Place n Route flow, for
detail information, please refer to Astro User Guide.

In this physical design flow, Synopsys Star-RCXT is being used to extract the RC values from
the Design Cell and Astro will take these values (create PARA view for the design cell) to
calculate the timing path. By doing this, Astro will be able to report the timing more accurately
and have better correlation with Primetime. Creating the Milkyway Parasitic view will also give
advantageous on next post route optimization since Astro will be able to catch up real timing
violations and fix them properly.

5.0 Acknowledgements

SNUG Singapore 2005 16 ASIC Backend Flow using Synopsys Astro

Credits:
1) Vasant Mallya, Director of Design Engineering Department from Integrated Circuit Design
Service Sdn Bhd;
2) Eric Lai Siaw Kang, Senior Project Engineer from Integrated Circuit Design Service Sdn Bhd;

6.0 References
[1] “Astro User Guide”, Synopsys, Version W- 2004.12
[2] “SolvNet (https://solvnet.synopsys.com)”, Synopsys
[3] “Astro Recommended Script-based Methodology”, Synopsys

SNUG Singapore 2005 17 ASIC Backend Flow using Synopsys Astro