IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO.
7, JULY 2010 1135
methods, the hardware except the storage elements requires
simple logic circuits as compared to previous method.
VI. Conclusion
The EOF algorithm can reduce the analysis time in two
ways. Using early termination with the number of the orthog-
onal faulty cells, EOF significantly reduces the search space
for the exhaustive search. Furthermore, the fault classification
of the EOF algorithm can eliminate unnecessary branches in
the search procedure. Since the fault classification can also
reduce the number of backtracks for the first solution, the
EOFSF algorithm is very useful for a BIRA solution targeting
the optimal repair rate. Experimental results show that the
EOF algorithm can achieve an optimal rate within a very
short analysis time and that it can be implemented with less
hardware overhead than previous methods.
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On Clustering of Undetectable Single Stuck-At Faults
and Test Quality in Full-Scan Circuits
Irith Pomeranz and Sudhakar M. Reddy
Abstract—We demonstrate that undetectable single stuck-at faults
in full-scan benchmark circuits tend to cluster in certain ar-
the set of target faults aimed at providing a better coverage of the circuit
in the presence of undetectable single stuck-at faults. The extended set of
target faults consists of double stuck-at faults that include an undetectable
fault as one of their components. The other component is a detectable
fault adjacent to the undetectable fault. We present experimental results
of fault simulation and test generation for the extended set of target
faults.
Index Terms—Full-scan, stuck-at faults, test generation, test quality,
undetectable faults.
I. Introduction
Fault models used as targets for test generation are ex-
in detecting defects. Thus, a test set generated for single
stuck-at faults in a full-scan circuit [1]–[7] is expected to
detect defects associated with the sites of stuck-at faults.
Test sets that contain several different tests for each fault
(n-detection test sets) are expected to increase the likelihood
of detecting defects associated with the sites of target faults
[8]–[16].
When a single stuck-at fault is undetectable, it leaves an
uncovered site in the circuit. As we demonstrate later, in
benchmark circuits, undetectable single stuck-at faults tend to
cluster in certain areas. This implies that certain areas of the
Manuscript received November 13, 2009; revised January 28, 2010. Date of
current version June 18, 2010. The work of I. Pomeranz and S. M. Reddy was
supported in part by the Semiconductor Research Corporation, under Grants
2007-TJ-1643 and 2007-TJ-1642, respectively. This paper was recommended
by Associate Editor, F. Lombardi.
I. Pomeranz is with the School of Electrical and Computer
Engineering, Purdue University, West Lafayette, IN 47907 USA
(e-mail: pomeranz@ecn.purdue.edu).
S. M. Reddy is with the Department of Electrical and Computer
Engineering, University of Iowa, Iowa City, IA 52242 USA (e-mail:
reddy@engineering.uiowa.edu).
Digital Object Identifier 10.1109/TCAD.2010.2046448
1136 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 7, JULY 2010
circuit remain uncovered, or less covered than other areas,
by a test set for single stuck-at faults. This phenomenon is
discerned from the gate level description of the circuit, and it
is independent of layout parameters. Specifically, undetectable
single stuck-at faults are introduced by logic synthesis. In
addition, our definition of clustering is based on the gate level,
and remains valid for any layout of the circuit.
To obtain a better estimate of coverage for the circuit in
the presence of undetectable faults, and provide a target for
improving this coverage, we propose to consider double stuck-
at faults that include an undetectable fault as one of their com-
ponents. The other component is a detectable fault adjacent to
the undetectable fault. The motivation for considering such
double faults is twofold.
1) The detection of a double stuck-at fault, which in-
cludes an undetectable stuck-at fault fi and an adjacent
detectable fault fj , provides indirect coverage for the
site of fi . Although fi is not detected when it is present
alone (since it is undetectable), it is detected when an-
other, adjacent fault is present. This improves the defect
coverage around the site of fi . For example, bridging
faults are often not targeted directly by tests used for
manufacturing testing due to the difficulty in extracting
and generating tests for potential bridges and the larger
test set sizes needed. In such cases, one depends on
accidental detection of bridges by tests generated for
single stuck-at faults. For bridges occurring in parts
of the circuit with undetectable faults, the probability
of accidental detection can be improved by adding
tests for double stuck-at faults as suggested in this
paper.
2) Based on [1], if an undetectable fault fi occurs in the
circuit without being detected and a second fault fj
occurs, a test set that detects fj when it is present alone
may not detect the double fault that consists of fi and
fj . Considering the double fault explicitly it is possible
to ensure that fj will be detected when fi is present.
Test sets that detect single stuck-at faults are known to
detect large percentages of multiple stuck-at faults [17]–[19].
Consequently, the requirement to detect double stuck-at faults
based on undetectable single stuck-at faults need not add a
significant number of tests to a test set for single stuck-
at faults. Nevertheless, the added tests can be important in
covering defects in the parts of the circuit with undetectable
single stuck-at faults. It should be noted in this regard that even
if a test set detects a fault fj , it is not guaranteed to detect a
double fault that consists of fj and a second fault, fi . Such
double faults will be targeted here when fi is an undetectable
fault and fj is an adjacent detectable fault.
This paper is organized as follows. In Section II, we
demonstrate that undetectable single stuck-at faults tend to
cluster in certain areas of benchmark circuits. In Section III,
we define the extended set of target faults that includes double
stuck-at faults based on undetectable single stuck-at faults. We
also describe a fault simulation and test generation experiment
targeting the extended set of faults. In Section IV, we present
experimental results of fault simulation and test generation. In
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Fig. 1. Example subcircuit 1.
Section V, we discuss the case where complete information
about detectable and undetectable faults is not available, and
present additional experimental results.
II. Clustering of Undetectable Faults
In this section, we demonstrate that undetectable single
stuck-at faults in full-scan benchmark circuits tend to cluster
in certain areas of the circuit. We consider the set F1 of
uncollapsed single stuck-at faults. This allows us to define
clustering, based on structural adjacencies between faults in
the circuit, without the need to account for undetectable faults
that are missing due to fault collapsing.
Let T1 be a given test set that detects all the detectable
faults in F1 . Suppose that T1 detects a subset D1 of F1 . The
set U1 = F1 − D1 consists of the undetectable faults in F1 .
We say that two faults fi and fj are adjacent, if one of the
following conditions is satisfied. Let gi be the site of fi and
let gj be the site of fj .
1) For a gate G, gi is the input of G and gj is the output
of G, or vice versa.
2) For a gate G, gi and gj are inputs of G.
3) gi is a fanout stem and gj is one of its fanout branches,
or vice versa.
4) For a fanout stem g, gi and gj are fanout branches of g.
We apply the adjacency relation to pairs of faults in U1
in order to partition U1 into subsets S0 , S1 , ... as follows. Let
U1 = {f0 , f1 , ..., fm−1 }. Initially, we set Si = {fi } for 0 ≤ i <
m. We then repeat the following process in order to merge
pairs of subsets that contain adjacent faults until no additional
merging is possible.
For every pair of subsets, Si1 and Si2 such that i1 < i2,
we check whether Si1 and Si2 contain faults fi1 and fi2 ,
respectively, such that fi1 and fi2 are adjacent. If so, we add
the faults from Si2 to Si1 , and remove Si2 .
For illustration, we show in Fig. 1 part of International
Symposium on Circuits and Systems (ISCAS)-89 benchmark
s5378. A value a above a line g indicates that the fault g stuck-
at a is undetectable. For some lines, both the stuck-at 0 and the
stuck-at 1 faults are undetectable. This is indicated by the val-
ues 0, 1 above the line. All the undetectable faults in Fig. 1 are
included in a single subset Si of adjacent undetectable faults.
We computed subsets of adjacent undetectable faults for
full-scan ISCAS-89 benchmark circuits. The results are shown
in Table I. Under column “Faults” we show the number of
uncollapsed single stuck-at faults. Under column “Undet” we
show the number of undetectable faults. Under column “Sub-
sets” we show the number of subsets of adjacent undetectable
POMERANZ AND REDDY: ON CLUSTERING OF UNDETECTABLE SINGLE STUCK-AT FAULTS AND TEST QUALITY IN FULL-SCAN CIRCUITS 1137

TABLE I
Clustering of Undetectable Faults

Subset Size
Circuit Faults Undet Subsets Ave Max
s1423 2820 26 11 2.36 6 Fig. 2. Example subcircuit 2.
s5378 10 590 120 16 7.50 30
s9234 18 468 1118 52 21.50 496
s13207 26 358 298 46 6.48 42
s15850 31 694 789 76 10.38 73
s38417 76 678 245 108 2.27 20
s35932 71 864 7344 1 7344.00 7344
s38584 76 864 3407 136 25.05 1568
Fig. 3. Example subcircuit 3.
faults. Under column “Subset Size” we show the average and
maximum size of a subset of adjacent undetectable faults. every line gj such that adj(gj ) = 0, if gj is adjacent to a line
From Table I, it can be seen that benchmark circuits have gk such that adj(gk ) = 1, we set adj2(gj ) = 1. We obtain a
large subsets of adjacent undetectable faults, similar to the one new set of lines with adj2(gj ) = 1, based on which we add
shown in Fig. 1 based on s5378. This is the motivation for double faults to F2 . We repeat this process until the number
attempting to increase the coverage of subcircuits that contain of faults added to F2 based on fi reaches N.
undetectable faults by considering double faults. For illustration, we show in Fig. 2 part of a circuit. An
undetectable fault gi stuck-at ai is marked with the value ai
III. Extended Set of Target Faults next to the line name. Our goal is to add N = 5 faults based on
In this section, we define an extended set of target stuck-at the undetectable fault g1 stuck-at 1. The first pass of marking
faults that consists of double stuck-at faults. The goal of the adjacent lines results in adj2(gj ) = 1 for j = 2 and 3. Based on
extension is to provide a target for improving the coverage these lines we add to F2 the faults (g1 /1, g2 /0), (g1 /1, g3 /0)
for sites of undetectable single stuck-at faults. We describe a and (g1 /1, g3 /1), where g/a is the fault g stuck-at a. We do
particular way of selecting the double faults. Other approaches not add the fault (g1 /1, g2 /1) since both g1 stuck-at 1 and g2
can be used instead to define a larger or smaller subset of stuck-at 1 are undetectable. Since the number of faults added
double faults. to F2 is smaller than N = 5, we set adj(gj ) = 1 for j = 2
As before, we consider the set F1 of uncollapsed single and 3, and mark lines that are adjacent to them. We obtain
stuck-at faults, and a test set T1 that detects all the detectable adj2(gj ) = 1 for j = 4 and 5. Based on these lines we can add
faults in F1 . We denote by D1 the subset of F1 that T1 detects. to F2 the faults (g1 /1, g4 /0), (g1 /1, g4 /1), and (g1 /1, g5 /1).
The set U1 = F1 − D1 consists of the undetectable faults in When the number of faults added to F2 reaches N = 5, we
F1 . We provide a target for additional coverage for the sites stop adding faults based on g1 stuck-at 1.
of the faults in U1 by using a set of double stuck-at faults, To avoid adding undetectable faults to F2 , we extend the
denoted by F2 . process as follows. Before starting to add faults based on
To define the set of double faults F2 , we use pairs of single fi ∈ U1 , we find the forward implications of setting gi to
stuck-at faults consisting of undetectable faults and detectable the value ai . In the circuit with these implications, we trace
faults that are adjacent to them. By using detectable faults that the circuit backward from the outputs, and mark the lines
are adjacent to undetectable faults we improve the coverage of that have x-paths to the outputs. An x-path is a path that has
areas of the circuit that contain undetectable faults. We avoid unspecified (x) values on all its lines. For illustration we show
undetectable double faults as described later. We consider the the implications for the fault g1 stuck-at 0 in the subcircuit
faults in U1 one at a time. For every fi ∈ U1 , we add double of Fig. 3. The lines with x values do not have x-paths to the
faults to F2 as follows. outputs in this example. We use the following two rules to
Let fi ∈ U1 be the fault gi stuck-at ai . We first mark gi and identify undetectable faults.
the lines that are adjacent to gi . We use two variables, adj(gj ) 1) Suppose that the implications of gi = ai include a value
and adj2(gj ) for every line gj . Initially, we set adj(gj ) = 0 aj on a line gj . Let fj be the fault gj stuck-at aj . The
and adj2(gj ) = 0 for every line gj . We set adj(gi ) = 1. For double fault that consists of fi and fj is undetectable,
every line gj , if gj is adjacent to gi , we set adj2(gj ) = 1. since fj does not affect the value of line gj in the
We use fi and the lines with adj2(gj ) = 1 to add faults faulty circuit that contains fi , and fi is undetectable.
to F2 as follows. For every fault fj ∈ D1 , if fj is the fault We do not add the fault with components fi and fj
gj stuck-at aj and adj2(gj ) = 1, we add the fault (fi , fj ) or to F2 . For example, in the circuit of Fig. 3, if g1
(fj , fi ) to F2 . We use (fi , fj ) if i < j, or (fj , fi ) if j < i. stuck-at 0 is undetectable, the double faults (g1 /0, g5 /0),
If the number of faults added to F2 based on fi is smaller (g1 /0, g6 /0), and (g1 /0, g7 /0) are undetectable.
than a constant N, we mark additional lines that are adjacent to 2) Suppose that line gj carries an unspecified value when
the lines already marked. We then add additional faults based gi = ai is implied, but gj does not have an x-path
on fi using the newly marked lines. This is done as follows. to an output. This implies that the value of line gj
For every line gj , if adj2(gj ) = 1, we set adj(gj ) = 1 and cannot affect the output values in the presence of fi .
adj2(gj ) = 0. This causes all the lines that were already used Since fi is undetectable, the double fault consisting of
to define double faults based on fi to have adj(gj ) = 1. For fi and fj is undetectable. We do not add the fault to

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1138 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 7, JULY 2010

TABLE II
Results for Extended Sets of Target Faults (ISCAS-89)
Double
Single Sim Test Gen
Circuit Faults1 Tests1 Undet1 p Faults2 Undet2 Tests2 Undet2 Det2
s1423 2846 26 26 1 2860 17 30 0 17
s5378 10 590 100 120 1 10 680 21 101 20 1
s9234 18 468 111 1118 1 19 006 401 113 399 2
2 38 012 603 115 601 2
4 74 906 957 132 935 22
8 148 694 1329 143 1312 17
s13207 26 358 235 298 1 25 757 157 236 156 1
s15850 31 694 97 789 1 32 349 208 103 180 28
4 127 029 396 104 395 1
8 254 058 548 105 546 2
s38417 76 678 87 245 1 76 685 53 88 47 6
s38584 76 864 142 3407 1 78 361 489 155 461 28
2 156 722 738 158 723 15
4 310 037 1228 160 1226 2
8 616 667 2049 162 2047 2

F2 . For example, in the circuit of Fig. 3, if g1 stuck- TABLE III

at 0 is undetectable, the double faults (g1 /0, g2 /0), Bridging Fault Simulation
(g1 /0, g2 /1), (g1 /0, g3 /0), (g1 /0, g3 /1), (g1 /0, g4 /0), Circuit Test Set Tests Bridg
and (g1 /0, g4 /1) are undetectable. s1423 T1 26 83.53
After F2 is defined, we perform fault simulation of F2 s1423 T 2, p = 1 30 85.68
under T1 . Suppose that T1 detects a subset of faults D2 ⊆ F2 s5378 T1 100 89.76
s5378 T 2, p = 2 101 89.90
and leaves the subset U2 ⊆ F2 undetected. We perform test s9234 T1 111 81.09
generation for U2 . Through this process, we extend T1 into a s9234 T 2, p = 1 113 81.53
test set T2 for F1 and F2 . s9234 T 2, p = 2 115 81.88
s9234 T 2, p = 4 132 83.33
IV. Experimental Results s9234 T 2, p = 8 143 83.59
s13207 T1 235 87.97
We applied the fault simulation and test generation experi- s13207 T 2, p = 1 236 89.08
ment described in Section III to full-scan ISCAS-89 bench- s15850 T1 97 86.39
s15850 T 2, p = 1 103 89.52
mark circuits. We defined sets of double faults such that s15850 T 2, p = 2 104 89.72
|F2 | ≈ p|F1 |, for p = 1, 2, 4, and 8. The variable p was s15850 T 2, p = 3 105 89.74
used for keeping the number of double faults manageable. s38417 T1 87 92.20
Since we include in F2 approximately N double faults for s38417 T 2, p = 1 88 92.41
s38584 T1 142 84.64
every single fault in U1 , we obtain |F2 | ≈ N|U1 |. To obtain s38584 T 2, p = 1 155 85.15
|F2 | ≈ N|U1 | ≈ p|F1 |, we used N = p·|F1 |/|U1 |. We increase s38584 T 2, p = 2 158 85.23
the number of faults in F2 in steps by increasing p, and use s38584 T 2, p = 4 160 85.27
s38584 T 2, p = 8 162 85.29
the test set T2 computed for the previous value as a starting
point for the generation of additional tests.
We used a simulation-based test generation process for dou- accept the complemented value of input k. Otherwise, input k
ble stuck-at faults. The test generation process is outlined next. retains its previous value in t.
Test generation is carried out for every fault (fi , fj ) ∈ U2 . If If (fi , fj ) is detected by t, we stop the modification of t and
a test t is obtained for (fi , fj ), t is added to the test set T2 . All accept the test. Otherwise, we continue until I = ∅. We start
the faults in U2 are then simulated under t with fault dropping. a new iteration by setting I = {0, 1, ..., n − 1} and repeating
A test t for a fault (fi , fj ) ∈ U2 is computed as follows. the process. This is done up to three times.
We note that one of the components of (fi , fj ) is an The results of fault simulation and test generation are re-
undetectable fault, and the other is a detectable fault. Let the ported in Table II. We report the results using N = p·|F1 |/|U1 |,
detectable fault be fi and let the undetectable fault be fj . For for every value of p that leads to the generation of additional
fi , the test set T1 contains a test that detects it. Let the test be tests. For most of the circuits additional tests are generated for
t. The simulation-based process we use modifies t into a test several values of p including p = 1. For s35932, no additional
for the double fault (fi , fj ) by complementing the bits of t one tests were generated for any value of p. This occurs since the
at a time. For a circuit with n inputs, let t = t(0)t(1)...t(n − 1). circuit is easily testable and double faults are detected by tests
Let I = {0, 1, ..., n−1}. In a step of the test generation process, for single faults. We omit this circuit from Table II.
we select an index k ∈ I randomly and remove it from I. We Under column “Single” of Table II, we show the number
then compute the test t̂ = t(0)...t(k − 1)t(k)t(k + 1)...t(n − 1) of single stuck-at faults in F1 (subcolumn “Faults1”), the
by complementing the value of input k. We simulate fi and number of tests in T1 (subcolumn “Tests1”), and the number
(fi , fj ) under t̂. If fi or (fi , fj ) is detected, we set t = t̂ to of undetectable faults in U1 (subcolumn “Undet1”).

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POMERANZ AND REDDY: ON CLUSTERING OF UNDETECTABLE SINGLE STUCK-AT FAULTS AND TEST QUALITY IN FULL-SCAN CIRCUITS 1139

TABLE IV
Results for Extended Sets of Target Faults (ITC-99)

Double
Single Sim Test Gen
Circuit Faults1 Tests1 Undet1 p Faults2 Undet2 Tests2 Undet1 Undet2 Det2
b12 5248 277 104 1 5304 16 281 64 4 12
2 10 496 9 282 47 6 3
b14 17 180 279 2979 1 17 874 15 284 2907 0 15
2 34 884 48 294 2794 0 48
4 69 850 108 306 2655 28 80
8 138 060 230 319 2529 78 152
b17 108 312 1683 8870 1 1 15 310 381 1693 8592 333 48
2 223 392 612 1707 8352 565 47
4 434 304 671 1728 8189 634 37
8 868 034 787 1739 8009 755 32
b20 38 494 535 4997 1 39 976 138 551 4724 6 132
2 80 308 153 565 4544 62 91
4 154 496 186 585 4366 74 112
8 309 986 410 622 4008 96 314

Under column “Double,” we show the value of p (sub-
column p) and the number of double faults included in F2
(subcolumn “Faults2”). Under subcolumn “Sim Undet2” we
show the number of double faults in F2 that are not detected
by the current test set. The current test set is T1 when p = 1,
or T2 generated for a lower value of p when p > 1.
Under column “Double” subcolumn “Test Gen,” we show
the number of tests in T2 after test generation for U2 (sub-
column “Tests2”). We then show the number of double faults
that are not detected by T2 (subcolumn “Undet2”). This is
the number of faults in U2 after test generation. We also
show the number of double faults detected by test generation
(subcolumn “Det2”). This is the difference between the size of
U2 before and after test generation. For example, for s38584,
142 tests in T1 leave 489 undetectable double faults for p = 1.
Test generation adds seven tests to T2 for a total of 155 tests,
and detects 28 double faults. With p = 2, test generation adds
three tests to T2 for a total of 158 tests, and detects 15 double
faults.
From Table II, it can be seen that, although a test set for
single stuck-at faults detects most of the double faults, it
leaves some of the double faults associated with undetectable
single stuck-at faults undetected. The number of such faults
varies with the circuit and with p. Overall, test generation for
the faults in U2 adds tests to T1 in order to detect some of
these faults. Although the number of tests is typically small,
these tests are important due to the need to provide better
coverage for areas of the circuit that may otherwise have
reduced coverage.
To illustrate that better coverage of the circuit is obtained
due to the tests added to T2 , we simulated nonfeedback four-
way bridging faults [20], [21] under T1 , and under the test sets
T2 obtained with the various values of p. Simulation of bridg-
ing faults was used earlier to demonstrate the effectiveness of
n-detection test sets for single stuck-at faults [22].
A four-way bridging fault g/a/ h is defined for a pair of
lines g and h and a value a ∈ {0, 1}. In the presence of the
fault, the value a on h dominates the value of g. The fault
is detected by a test that sets h = a and detects the stuck-at
a fault on g. The model is referred to as four-way since it
associates four faults with every pair of lines, differing in the
dominating line and value. For every line g and every value a,
we select ten four-way bridging faults randomly by selecting
h randomly ten times without repetition.
The results of bridging fault simulation are shown in Table
III. The first row for every circuit corresponds to T1 . Additional
rows correspond to T2 with various values of p. The type of
the test set is shown under column “Test Set.” Under column
“Tests” we show the number of tests in the test set. Under
column “Bridg” we show the four-way bridging fault coverage.
From Table III, it can be seen that adding tests for double
stuck-at faults increases the four-way bridging fault coverage.
Thus, the additional tests cover defects that are not covered
by the single stuck-at test set.
V. Unresolved Faults
A test generation procedure may not be able to determine
for every fault whether it is detectable or undetectable. Such a
fault is said to be unresolved. The procedures described in the
previous sections can treat unresolved faults as undetectable,
and provide additional coverage for them. A possible by-
product of obtaining additional coverage for double faults
based on an unresolved fault fi is that a test for fi would be
found.
We applied the fault simulation and test generation experi-
ment described in Section III to full-scan ITC-99 benchmark
circuits with the same parameters as in Section IV, and with the
following changes. To obtain the test set T1 , we perform fault
simulation with fault dropping of F1 under 100 000 random
tests. We include in T1 , every random test that detects a new
fault from F1 , when it is simulated. This test set does not
detect all the detectable single stuck-at faults in the benchmark
circuits considered.
After targeting double faults and extending the test set into
a new test set T2 , we perform fault simulation of T2 to check
whether any additional single faults are detected. As p is
increased, we only define double faults based on single faults
that are still undetected.
The results of this experiment are shown in Table IV.
Column “Double Test Gen Undet1” of Table IV shows the

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1140 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 7, JULY 2010
number of single faults that are not detected by the extended
test set for every value of p. The other columns of Table IV
are the same as those of Table II.
From Table IV, it can be seen that the additional tests
generated for covering sites of undetected single stuck-at faults
also help detect additional detectable single faults. This is in
addition to providing a better coverage for sites of faults that
remain undetected.
VI. Conclusion
We demonstrated that undetectable single stuck-at faults in
full-scan benchmark circuits tend to cluster in certain areas.
We introduced an extended set of target faults based on
double stuck-at faults, whose goal was to provide a target for
improving the coverage of these areas. We defined the set of
double faults based on undetectable faults and detectable faults
that are adjacent to them. We presented experimental results
of fault simulation and test generation in order to demonstrate
the extent to which the coverage of areas with undetectable
faults can be improved.
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Automated Model Generation Algorithm
for High-Level Fault Modeling
Likun Xia, Member, IEEE, Ian M. Bell, Member, IEEE, and
Antony J. Wilkinson, Member, IEEE
Abstract—High-level modeling for operational amplifiers (opamps)
has been previously carried out successfully using models generated by
published automated model generation approaches. Furthermore, high-
level fault modeling (HLFM) has been shown to work reasonably well
using manually designed fault models. However, no evidence shows that
published automated model generation approaches based on opamps
have been used in HLFM. This paper describes HLFM for analog
circuits using an adaptive self-tuning algorithm called multiple model
generation system using delta. The generation algorithms and simula-
tion models were written in MATLAB and the hardware description
language VHDL-AMS, respectively. The properties of these self-tuning
algorithms were investigated by modeling complementary metal-oxide-
semiconductor opamps, and comparing simulations using the HLFM
against those of the original simulation program with integrated circuit
emphasis circuit utilizing transient analysis. Results show that the models
can handle both linear and nonlinear fault situations with better accuracy
than previously published HLFMs.
Index Terms—Analog fault simulation, automated model generation
I. Introduction
In recent years, the complexity and performance of analog
and mixed signals integrated circuits (ICs) has increased,
resulting in higher test equipment costs due to consequent
test may mitigate these problems due to its potential efficiency
and low cost [1], and furthermore may provide additional
information on quality and reliability, unavailable from func-
tional test [2].
Manuscript received July 28, 2009; revised November 26, 2009. Date of
L. Xia is with the Department of Electrical and Electronic Engineering,
University Technology PETRONAS, Bandar Seri Iskandar, 31750, Tronoh,
Perak Darul Ridzuan, Malaysia (e-mail: xialikun@hotmail.com).
I. M. Bell and A. J. Wilkinson are with the Department of Engineer-
a.j.wilkinson@hull.ac.uk).
Digital Object Identifier 10.1109/TCAD.2010.2045556