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DESCRIPCION EN VHDL DE UN DECODIFICADOR BINARIO DE 2

ENTRADAS

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity deco2a4 is
Port ( e : in STD_LOGIC_VECTOR (1 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0));
end deco2a4;

architecture Behavioral of deco2a4 is

begin

with e select
s <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
end Behavioral;

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