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1
supplying power to the DC grid. The CFC is located in node 2.1 Linearized model of the HVDC grid and CFC
1, interconnecting it with node 4 and 5. The CFC considered
for this study is the dual H-bridge presented in [6]. It is a For control design purposes the model of the HVDC grid,
series-connected device made of 6 IGBTs and their anti- including the CFC is linearized. The average model derived in
parallel diodes. The element that is exchanging energy [8] is used to develop the linearized model of the complete
between different cables is the capacitor. This capacitor is HVDC system. The average model of the CFC consists of
inserted in one line using its current to charge it and two voltage sources applied to the lines with the following
afterwards is placed in the other line where it is discharged. expressions:
Using this power exchange the CFC is able to apply variable ଵ ൌ ሺͳ െ ሻଶ ൌ െ ሺͳሻ
voltage sources into the lines, thus, modifying the current where, E is the average voltage of the CFC capacitor and D is
flow. The CFC layout is depicted in Fig. 2. the duty cycle of the switching IGBTs of the CFC.
The current of the nodes that inject constant power and the
ones that are operating with droop control, respectively, are
described as:
୧
୧ ൌ ୧ ൌ ୧ ሺ୧ כെ ୧ ሻ ሺʹሻ
୧
The linearized equations describing the DC grid with the CFC
are:
οଵ ͳ
ൌ ሺെଵ οଵ οଶଵ οଷଵ οସଵ οହଵ ሻ (3)
ଵ
οଶ ͳ οଶ ଶ െ οଶ ଶ
ൌ ቆ ଶ െ οଶଷ െ οଶଵ ቇ (4)
ଶ ଶ
Fig. 2. Dual H-bridge CFC layout. οଷ ͳ
ൌ ሺെ ଷ οଷ οଶଷ െ οଷଵ െ οଷସ ሻ (5)
ଷ
3 Meshed HVDC grid and CFC modelling οସ ͳ οସ ସ െ οସ ସ
ൌ ቆ ଶ οଷସ െ οସଵ െ οସହ ቇ (6)
For this study, the meshed HVDC grid is modelled only as the ସ ସ
half of the symmetrical monopole. As a result, only one CFC οହ ͳ οହ ହ െ οହ ହ
is needed to be placed in the positive monopole. The cables in ൌ ቆ ଶ οସହ െ οହଵ ቇ (7)
ହ ହ
the DC grid are modelled considering the PI equivalent. The οଶଷ ͳ
resistance, inductance and capacitance are extracted from ൌ ሺοଶ െ οଷ െ ଶଷ οଶଷ ሻ (8)
ଶଷ
CIGRÉ benchmark for DC grid studies [11]. VSCs are οଶଵ ͳ
operating either injecting or absorbing constant power or as ൌ ሺοଶ െ οଵ െ ଶଵ οଶଵ ሻ (9)
voltage regulators based on droop control [12]. Nodes 2, 4 ଶଵ
οଷଵ ͳ
and 5 inject or absorb constant power and nodes 1 and 3 ൌ ሺοଷ െ οଵ െ ଷଵ οଷଵ ሻ (10)
perform droop control. The CFC is modelled as a dual H- ଷଵ
bridge made of IGBTs with the corresponding anti-parallel οଷସ ͳ
ൌ ሺοଷ െ οସ െ ଷସ οଷସ ሻ (11)
diodes removing the two redundant switches [6]. It consists of ଷସ
a single capacitor as energy exchange element. The cable, οସଵ ͳ
ൌ ሺοସ െ οଵ െ ସଵ οସଵ ሺ െ ͳሻο
VSC and CFC parameters can be seen in Table 1. ସଵ (12)
οሻ
DC cable parameters οସହ ͳ
ൌ ሺοସ െ οହ െ ସହ οସହ ሻ (13)
Lines 23 21 31 34 41 45 51 ସହ
Distance οହଵ ͳ
100 80 120 100 100 120 80 ൌ ሺοହ െ οଵ െ ହଵ οହଵ ο οሻ (14)
[km] ହଵ
VSC parameters ο ͳ
Nodes 1 2 3 4 5 ൌ ሺሺͳ െ ሻοସଵ െ οହଵ െ ሺସଵ ହଵ ሻοሻ (15)
Capacitance [F] 300 300 150 150 450
Power [MW] - 800 - -200 -1200 where, Ei, Ii, Pi are the DC voltage, current and power,
Ei* [kV] 200 - 200 - - respectively, of node i, ki is the droop constant for the VSC
Droop constant ki converter in node i, Ci is the VSC capacitance in node i, and it
0.05 - 0.05 - -
[A/V] includes also the half of cable capacitance. Iij is the current
CFC parameters from node i to j. Lij and Rij are the inductance and resistance
Nominal voltage [kV] 4 of the cable from node i to j. C is the capacitance of the CFC.
Switching frequency [kHz] 2 The variables with ¨ are the increments over the linearization
Capacitor [mF] 10 point, and the variables with a 0 subscript are the linearization
Table 1: DC cable, VSC and CFC parameters. points. Then, the linearized state-space of the DC grid
including the CFC is presented below:
2
The tuning goal is obtaining a first order time response, IJ c, as
ο ൌ ۯο ۰ο ሺͳሻ
well, without overshoot. The relation between time constants
where, ¨x is the vector of linearized state variables, ¨u is the is given by:
vector of linearized inputs: ߬ ൌ ߬ܨ௩ ሺʹͳሻ
ο ܠൌ ሺοଵ ǡ οଶ ǡ οଷ ǡ οସ ǡ οହ ǡ οଶଷ ǡ where F is a factor > 1.
οଶଵ ǡ οଷଵ ǡ οଷସ ǡ οସଵ ǡ οସହ ǡ οହଵ ǡ οሻ ሺͳሻ Before obtaining the final controllers design, there are several
ο ܝൌ ሺοଶ ǡ οସ ǡ οହ ǡ οሻ ሺͳͺሻ considerations regarding system limitations that must be
And A is a 13x13 matrix and B is a 13x4 matrix. taken into account. First, the inner loop time response must be
slower than the switching frequency of the CFC (2 kHz) due
3 Control design methodology to the modulation effect. Secondly, the control action that the
CFC is able to apply (duty cycle D) ranges from 0 to 1.
An enhanced control design methodology is presented in this Therefore, although the linearized model can impose duty
section, compared to the one introduced in [8]. In [8] a cycles higher than 1, they are not feasible in the real system.
current loop is considered to regulate line currents, but the For this reason, the control action (D) must be limited
CFC voltage is not controlled. This issue can lead the voltage between 0 and 1 during transients. In steady-state the D will
of the capacitor to achieve values over its rating and the rating be always between 0 and 1 as they mean nulling one DC
of the switches both during transients and in steady state. current or the other. Moreover, when considering the two
Therefore, here, a coordinated control design of the CFC cascaded controllers, the designed first order time response of
voltage loop and the current loop is presented. The voltage the inner controller cannot be ensured, as it will be affected
controller is designed to be operated independently or as an by the output of the outer loop, the voltage reference (E*). In
inner controller. The control scheme is depicted in Fig. 3. order to tackle these issues, the following transfer functions
are obtained from the linearized model. Tv(s) is the closed
loop transfer function of the CFC voltage relating the
reference, E*, with the measured voltage, E. KSv(s) is the
transfer function relating the reference, E*, with the duty
cycle, D. Both expressions are shown below:
୴ ୴ ୴
୴ ሺሻ ൌ ୴ ሺሻ ൌ ሺʹʹሻ
ͳ
୴ ୴ ͳ
୴ ୴
Fig. 3. Proposed control scheme. The open loop transfer function that relates the duty cycle, D,
with the current reference, I*, is Gc(s). Then, the closed loop
The defined controlled current is I41. The first step consists on transfer function relating I* with the measured current, I, is
designing the inner loop, which is the voltage loop. Tc(s), which expression is:
Consequently, the transfer function Gv(s) relating the CFC ୡ ୴ ୡ
voltage E and the duty cycle D is obtained using the ୡ ሺሻ ൌ ୡ ୴
୴ିଵ
ୡ ൌ ሺʹ͵ሻ
ͳ
୴ ୴
linearized model of the system. The transfer function of the The input of the final control system is the current reference,
voltage controller (Kv(s)) is composed of a Proportional- I*, as the voltage controller is part of the inner loop. In order
Integral (PI) controller and a Second Order Compensator to perform a proper design, the transfer functions relating I*
(SOC) to damp the system oscillations in closed loop, as with the measured voltage of the CFC (Govershoot(s)) and the
presented in [8]. The transfer function of the voltage duty cycle (Gaction(s)) must be obtained.
controller has the following expression: Fig. 4 depicts the scheme to obtain these transfer functions.
୮୴ ୧୴ ଶ ଶ ଵ
୴ ሺሻ ൌ ቆ ቇቆ ଶ ቇ ሺͳͻሻ
ଶ ଵ
Kv (s) is designed to be able to control the voltage
independently from the current loop and to achieve a closed
loop first order response of time constant IJv without
overshoot. Then, an outer controller is added in cascade to
regulate the line current I41, whose output or control action is
the reference voltage of the CFC, E*. This outer controller
must be slower than the inner voltage controller to avoid
interactions between them. A single PI controller for the outer
loop is considered for simplicity. It is designed considering
the addition of the previous inner controller into the system.
Equation (20) shows the Kc(s) controller of the current loop. Fig. 4. Block diagram of the transfer functions Govershoot(s) and
୮ୡ ୧ୡ Gaction(s).
ୡ ሺሻ ൌ ቆ ቇ ሺʹͲሻ
Govershoot(s) can be seen in (24) and Gaction(s) is presented in
(25).
3
ୡ ୴ ୡ ୴
୴
୭୴ୣ୰ୱ୦୭୭୲ ሺሻ ൌ ൌ
ୡ ୡ ୴ ͳ ୡ ୴
ୡ ୴
୴ ሺʹͶሻ
ͳ
୴
ୡ ୴
୴ିଵ ୡ ୴
ୟୡ୲୧୭୬ ሺሻ ൌ ିଵ
ൌ ሺʹͷሻ
ͳ ୡ ୴
୴
ୡ ͳ ୡ ୴
ୡ ୴
୴
4
Finally, an Anti-Windup (AW) scheme is included in the
model to avoid windup effects when the voltage reference, E *,
is saturated. The final controllers’ parameters are shown in
Table 2.
Control parameters
kpc kic kpv kiv kaw
2.7807 11.0301 0.0127 0.1625 1.1030
a2 a1 a0 b2 b1 b0
0.0094 0.0420 1.7234 1 17.5232 60.1029
Table 2. Parameters of the voltage and current controllers
4 Case studies
Fig. 8. Comparison of different CFC control schemes.
In this section, three case studies are considered to validate
the proposed control design methodology. Simulations are Finally, the dotted grey line and the solid black line depict the
carried out using the detailed model of the grid and the CFC. controllers designed in Section 3 without and with AW,
respectively. The controller presented in [8] shows a faster
4.1 Comparison of the linearized and the detailed model time response when following current references. However,
the second step implies exceeding the CFC nominal voltage
The linearized and the detailed model are compared in this which could damage the CFC device. The CFC voltage gets a
section considering the controllers designed in Section 3. Fig. value higher than 1.2 pu as it can be seen in Fig. 8b in grey
7a shows how both systems are following the I41 references solid line. The addition of the voltage loop allows to saturate
with a first order time response. The difference between them the maximum voltage reference, E*, that is sent to the voltage
is negligible, still it is increasing the further the system goes controller. Thus, the current reference cannot be followed in
from the linearization point. Fig. 7b depicts the CFC voltage this case (Fig. 8a) but the voltage is kept at 1 pu (Fig. 8b). At
E required to change the current. It can be seen that both instant t = 6 s, a new current reference is received that implies
models have a reduced overshoot. It is important to notice reducing the CFC voltage. Without using the AW scheme, the
that when the system is far from the linearization point, the system has too much error in the integrator, leading to a
voltage overshoot is slightly reduced but the steady state slower response. The addition of the anti-windup allows
value differs from one model to the other. having a faster response as it can be seen in Fig. 8b with the
black solid line.
5
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