Maharashtra Academy of Engineering, Alandi DEL Manual

EXPERIMENT No: 1
Title: T.T.L Characteristics (Study and Write up only).

Relevant Theory:

Transistor–Transistor Logic (TTL) is a class of digital circuits built from bipolar

junction transistors (BJT), and resistors. It is called transistor–transistor logic because
both the logic gating function (e.g., AND) and the amplifying function are performed by
transistors (contrast this with RTL and DTL). It is notable for being a widespread
integrated circuit (IC) family used in many applications such as computers, industrial
controls, test equipment and instrumentation, consumer electronics, synthesizers, etc.
Because of the wide use of this logic family, signal inputs and outputs of electronic
equipment may be called "TTL" inputs or outputs, signifying compatibility with the
voltage levels used.

Comparison with other logic families:

Generally, TTL devices consume more power than an equivalent CMOS device at rest,
but power consumption does not increase with clock speed as rapidly as for CMOS
devices. Compared to contemporary ECL circuits, TTL uses less power and has
easier design rules, but is typically slower; designers can combine ECL and TTL
devices in the same system to achieve best overall performance and economy. TTL
was less sensitive to damage from electrostatic discharge than early CMOS devices.

Due to the output structure of TTL devices, the output impedance is asymmetrical
between the high and low state, making them unsuitable for driving transmission lines.
This is usually solved by buffering the outputs with special line driver devices where
signals need to be sent through cables. ECL, by virtue of its symmetric output structure,
doesn't have this drawback.

Several manufacturers now supply CMOS logic equivalents with TTL compatible input
and output levels, usually bearing part numbers similar to the equivalent TTL component
and with the same pin-out diagrams.

Now-a-days digital integrated circuits are most commonly used in modern digital
systems. The most of the digital circuits are constructed in single chip, which are referred
to as Integrated Circuits (IC).

A group of compatible ICs with the same logic levels and supply voltages for performing
various logic functions have been fabricated using a specific circuit configuration, which
is referred to as a Logic Family.

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There are two types of Logic Families, which are as follows:

1) Bipolar Logic Family

2) Unipolar Logic Family

Bipolar Logic Families: The main elements of a bipolar IC are resistors, diodes
(which are also capacitors) and transistors. Basically there are two types of
operations in bipolar ICs:

1) Saturated, and

2)Non-saturated

The saturated bipolar logic families are:

 Resistor-transistor logic (RTL)
 Direct-coupled transistor logic (DCTL)
 Integrated-injection logic (I2L)
 Diode-transistor logic (DTL)
 High-threshold logic (HTL) and
 Transistor-transistor logic (TTL)

The non-saturated bipolar logic families are:

 Schottky TTL, and
 Emitter-coupled logic (ECL)

Unipolar Logic Families:

MOS devices are unipolar devices and only MOSFETs are employed in MOS logic
circuits. The MOS logic families are: PMOS NMOS, and CMOS

Characteristics of Digital ICs:

We know that there are various logic families. The selection of logical families for the
application is based on its characteristics, and hence it is necessary to study the
characteristics of digital ICs. The various parameters of digital ICs used to compare their
performance are:
1. Speed of operation
2. Power dissipation
3. Figure of merit
4. Fan-out
5. Fan-in

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6. Current and voltage parameters

7. Noise immunity
8. Operating temperature range
9. Power supply requirements
10. Propagation Delay
11. Current Sinking
12. Current Sinking
13. Loading Factor

Speed of operation:

It is one of the important parameters of digital ICs. Speed of operation of digital ICs
should be high. The speed of a digital circuit is specified in terms of the propagation
delay time. The input and output waveforms of a logic gate are shown in Fig.1.1.

50%
Input

Output
50%

TpHL TpLH

Fig.1.1 Input and Output waveforms to define propagation delay time

The propagation delay time of the logic gate is the average of propagation delay time
from high state to low state and propagation delay time from low to high state.

t PHL + t PLH
tP =
2

The delay times are measured between 50 percent voltage levels of input and output
waveforms. There are two delay times:
tPHL: It is the delay time measured, when output changes from high to low state.
tPLH: It is the delay time measured, when output changes from low to high state.

The propagation delay between input and output should be as minimum as possible so
that the operating speed of IC is high.

Power Dissipation:

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We know that every electronic circuit requires amount of electric power. Power
dissipation is the amount of power dissipated in an IC. It is determined by the current ICC,
that it draws from the VCC supply, and is given by VCC X ICC. ICC is the average value of
ICC(0) and ICC(1). This power is specified in milliwatts.

Figure of Merit:

The figure of merit of a digital IC is defined as the product of speed and power. The
speed is specified in terms of propagation delay time expressed in nanoseconds.

Figure of merit = propagation delay time (ns) X power (mW)

It is specified in pico joules (ns X mW = pJ)

A low value of speed-power product is desirable. In a digital circuit, if it is desired to
have high speed, i.e. low propagation delay, then there is a corresponding increase in the
power dissipation and vice-versa.

Fan-Out:

This is the number of similar gates, which can be driven by a gate. High fan-out is
advantageous because it reduces the need for additional drivers to drive more gates.
Consider the Fig. 1.2.

N number
of load
gates

Fig. 1.2 Diagram illustrating the concept of Fan-Out.

The driver gate drives the N gate (N is fan-out). If more than one N gates are connected
to a load, the current supply by the driver gate is not sufficient to drive the gates or the

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current sink by the driver gate is more than the rating of the driver gate and gate may be
damaged.
Using the fan-out of a logic family we can calculate the current component.

IOH IOL
Fan-out = minimum of { , }
IIH IIL

Fan-In:

Number of inputs are connected to gate, which is known as fan-in of the gate. For two
inputs gate, fan-in is two and for four inputs gate, fan-in is four.

Current and Voltage Parameters:

The following currents and voltages are specified which are very useful in the design of
digital systems.

High-level input voltage, VIH: This is the minimum input voltage, which is recognized by
the gate as logic 1.

Low-level input voltage, VIL: This is the maximum input voltage, which is recognized by
the gate as logic 0.

High-level output voltage, VOH: This is the minimum voltage available at the output
corresponding to logic 1.

Low-level output voltage, VOL: This is the maximum voltage available at the output
corresponding to logic 0.

High-level input current, IIH: This is the minimum current, which must be supplied by a
driving source corresponding to 1 level voltage.

Low-level input current, IIL: This is the minimum current, which must be supplied by a
driving source corresponding to 0 level voltage.

High-level output current, IOH: This is the maximum current, which the gate can sink in
1 level.

Low-level output current, IOL: This is the maximum current, which the gate can sink in 0
level.

High-level supply current, ICC (1): This is the supply current when the output of the gate
is at logic 1.

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Low-level supply current, ICC (0): This is the supply current when the output of the gate
is at logic 0.
The current directions are illustrated in Fig. 1.3.

IIL IoL

IIH IoH

Fig. 1.3 A gate with current directions marked

Noise Immunity:

The circuit’s ability to tolerate noise signals without causing spurious changes in the
output voltage is called as Noise Immunity.
To avoid noise problem voltage level VIH(min) is kept a few fractions of voltages
below VOH(min) and voltage level VIL(max) is kept above VOL(max) at the design time.

VOH
VNH

VIH

VIL
VNL
VOL

fig. 1.4 Voltage Levels and Noise Margins in ICs

Noise Margin: A quantitative measure of noise immunity is known as noise margin.

DC Noise Margin:

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1. Low-level noise margin (NML)- The difference between VIL and VOL i.e. VIL -
VOL is known as low-level noise margin.

NML = VIL - VOL = 0.8 - 0.4 = 400mV

2. High-level noise margin (NMH)- The difference between VOH and VIH i.e. VOH –
VIH is known as high-level noise margin.
NMH = VOH – VIH = 2.4 – 2 = 400mV

Operating Temperature:

The temperature range in which an IC functions properly must be known. The accepted
temperature ranges are: 0 to +70o C for consumer and industrial applications and -55o C
to +125o C for military purposes.

Power Supply Requirements:

The supply voltage (s) and the amount of power required by an IC are important
characteristics required to choose the proper power supply.

Propagation Delay :

It is time required by gate to give output when input is applied. Always in ns.

Current Sinking :

The current supply by driver gate to load gate is called as sinking current.

When driver gate output is low, then the EB junction of loaded gate become forward bias,
and the VCC of load gate passes current through T3 of driver gate this called as sink
current.

Current Sourcing :

Source current is a current supply by driver gate to load gate.

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When driver gate output is high the current is supplied to the load gate is a sourcing
current.

Standard TTL logic levels

Operating conditions: V CC 4.75 V min. to 5.25 V max.

74XX chips

PARAMETER CONDITIONS MIN MAX UNITS

Logic 1
VCC = min 2.0 -- V
input voltage
Logic 0
VCC = min -- 0.8 V
input voltage
Logic 1 VCC = min - - Iout = -0.4
2.4 -- V
output voltage mA
Logic 0
VCC = min - - Iout = 16 mA -- 0.4 V
output voltage
Logic 1
VCC = min - - Vin = 2.4 V -- 0.04 mA
input current
Logic 1
V CC = min - - Vin = 5.5 V -- 1 mA
input current
Logic 0
VCC = min - - V in = 0.4 V -- - 1.6 mA
input current

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VOH Min :

Output voltage high minimum with up to 0.4

mA load A good chip is guaranteed to
output a minimum of 2.4 V logic high What
up to 0.4 mA

VOL Max :

Output voltage low maximum with up to 16

mA load A good chip is guaranteed to
output a maximum of 0.4 volts up to 16 mA

VIH Min :

Input voltage high minimum 2.0 V A good

chip will recognize 2.0 V or greater as a
logic high and draw no more than 0.04 mA
input current.

VIL Min :

Input voltage low maximum 0.8 V A good

chip will recognize 0.8 V or less as a logic
low and draw no more than 1.6 mA input
current.

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7400 series TTL IC's: 7400...7449

7400
Quad 2-input NAND gates.

+---+--+---+ +---+---*---+ __
1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | 1 |
2A |4 7400 11| /4Y | 0 | 1 | 1 |
2B |5 10| 3B | 1 | 0 | 1 |
/2Y |6 9| 3A | 1 | 1 | 0 |
GND |7 8| /3Y +---+---*---+
+----------+

Positive Logic

__
Y = AB

Equivalent Chips

• SN5400 (J)
• SN54H00 (J)

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• SN54L00 (J)
• SN54LS00 (J,W)
• SN54S00 (J,W)
• SN7400 (J,N)
• SN74H00 (J,N)
• SN74L00 (J,N)
• SN74LS00 (J,N)
• SN47S00 (J,N)

7401

Quad 2-input open-collector NAND gates.

+---+--+---+ +---+---*---+ __
/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = AB
1A |2 13| /4Y +===+===*===+
1B |3 12| 4B | 0 | 0 | Z |
/2Y |4 7401 11| 4A | 0 | 1 | Z |
2A |5 10| /3Y | 1 | 0 | Z |
2B |6 9| 3B | 1 | 1 | 0 |
GND |7 8| 3A +---+---*---+
+----------+

7402

Quad 2-input NOR gates.

+---+--+---+ +---+---*---+ ___
/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = A+B
1A |2 13| /4Y +===+===*===+
1B |3 12| 4B | 0 | 0 | 1 |
/2Y |4 7402 11| 4A | 0 | 1 | 0 |
2A |5 10| /3Y | 1 | 0 | 0 |
2B |6 9| 3B | 1 | 1 | 0 |
GND |7 8| 3A +---+---*---+
+----------+

7403

Quad 2-input open-collector NAND gates.

+---+--+---+ +---+---*---+ __
1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | Z |
2A |4 7403 11| /4Y | 0 | 1 | Z |
2B |5 10| 3B | 1 | 0 | Z |
/2Y |6 9| 3A | 1 | 1 | 0 |
GND |7 8| /3Y +---+---*---+
+----------+

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7404

Hex inverters.

+---+--+---+ +---*---+ _
1A |1 +--+ 14| VCC | A |/Y | /Y = A
/1Y |2 13| 6A +===*===+
2A |3 12| /6Y | 0 | 1 |
/2Y |4 7404 11| 5A | 1 | 0 |
3A |5 10| /5Y +---*---+
/3Y |6 9| 4A
GND |7 8| /4Y
+----------+

Positive Logic

_
Y = A

Equivalent Chips

• SN5404 (J)
• SN54H04 (J)
• SN54L04 (J)
• SN54LS04 (J,W)
• SN54S04 (J,W)
• SN7404 (J,N)

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Maharashtra Academy of Engineering, Alandi DEL Manual

• SN74H04 (J,N)
• SN74L04 (J,N)
• SN74LS04 (J,N)
• SN47S04 (J,N)

7405

Hex open-collector inverters.

+---+--+---+ +---*---+ _
1A |1 +--+ 14| VCC | A |/Y | /Y = A
/1Y |2 13| 6A +===*===+
2A |3 12| /6Y | 0 | Z |
/2Y |4 7405 11| 5A | 1 | 0 |
3A |5 10| /5Y +---*---+
/3Y |6 9| 4A
GND |7 8| /4Y
+----------+

7406

Hex open-collector high-voltage inverters.

Maximum output voltage is 30V.
+---+--+---+ +---*---+ _
1A |1 +--+ 14| VCC | A |/Y | /Y = A
/1Y |2 13| 6A +===*===+
2A |3 12| /6Y | 0 | Z |
/2Y |4 7406 11| 5A | 1 | 0 |
3A |5 10| /5Y +---*---+
/3Y |6 9| 4A
GND |7 8| /4Y
+----------+

7407

Hex open-collector high-voltage buffers.

Maximum output voltage is 30V.
+---+--+---+ +---*---+
1A |1 +--+ 14| VCC | A | Y | Y = A
1Y |2 13| 6A +===*===+
2A |3 12| 6Y | 0 | 0 |
2Y |4 7407 11| 5A | 1 | Z |
3A |5 10| 5Y +---*---+
3Y |6 9| 4A
GND |7 8| 4Y
+----------+

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7408

Quad 2-input AND gates.

+---+--+---+ +---+---*---+
1A |1 +--+ 14| VCC | A | B | Y | Y = AB
1B |2 13| 4B +===+===*===+
1Y |3 12| 4A | 0 | 0 | 0 |
2A |4 7408 11| 4Y | 0 | 1 | 0 |
2B |5 10| 3B | 1 | 0 | 0 |
2Y |6 9| 3A | 1 | 1 | 1 |
GND |7 8| 3Y +---+---*---+
+----------+

Positive Logic

Y = AB

7409

Quad 2-input open-collector AND gates.

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+---+--+---+ +---+---*---+
1A |1 +--+ 14| VCC | A | B | Y | Y = AB
1B |2 13| 4B +===+===*===+
1Y |3 12| 4A | 0 | 0 | 0 |
2A |4 7409 11| 4Y | 0 | 1 | 0 |
2B |5 10| 3B | 1 | 0 | 0 |
2Y |6 9| 3A | 1 | 1 | Z |
GND |7 8| 3Y +---+---*---+
+----------+

7410

Triple 3-input NAND gates.

+---+--+---+ +---+---+---*---+ ___

1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = ABC
1B |2 13| 1C +===+===+===*===+
2A |3 12| /1Y | 0 | X | X | 1 |
2B |4 7410 11| 3C | 1 | 0 | X | 1 |
2C |5 10| 3B | 1 | 1 | 0 | 1 |
/2Y |6 9| 3A | 1 | 1 | 1 | 0 |
GND |7 8| /3Y +---+---+---*---+
+----------+

Positive Logic

___
Y = ABC

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7411

Triple 3-input AND gates.

+---+--+---+ +---+---+---*---+
1A |1 +--+ 14| VCC | A | B | C | Y | Y = ABC
1B |2 13| 1C +===+===+===*===+
2A |3 12| 1Y | 0 | X | X | 0 |
2B |4 7411 11| 3C | 1 | 0 | X | 0 |
2C |5 10| 3B | 1 | 1 | 0 | 0 |
2Y |6 9| 3A | 1 | 1 | 1 | 1 |
GND |7 8| 3Y +---+---+---*---+
+----------+

7412

Triple 3-input open-collector NAND gates.

+---+--+---+ +---+---+---*---+ ___
1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = ABC
1B |2 13| 1C +===+===+===*===+
2A |3 12| /1Y | 0 | X | X | Z |
2B |4 7410 11| 3C | 1 | 0 | X | Z |
2C |5 10| 3B | 1 | 1 | 0 | Z |
/2Y |6 9| 3A | 1 | 1 | 1 | 0 |
GND |7 8| /3Y +---+---+---*---+
+----------+

7413

Dual 4-input NAND gates with Schmitt-trigger inputs.

0.8V typical input hysteresis at VCC=+5V.
+---+--+---+ +---+---+---+---*---+ ____
1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD
1B |2 13| 2D +===+===+===+===*===+
|3 12| 2C | 0 | X | X | X | 1 |
1C |4 7413 11| | 1 | 0 | X | X | 1 |
1D |5 10| 2B | 1 | 1 | 0 | X | 1 |
/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |
GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |
+----------+ +---+---+---+---*---+

7414

Hex inverters with schmitt-trigger inputs.

0.8V typical input hysteresis at VCC=+5V.

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Maharashtra Academy of Engineering, Alandi DEL Manual

+---+--+---+ +---*---+ _
1A |1 +--+ 14| VCC | A |/Y | /Y = A
/1Y |2 13| 6A +===*===+
2A |3 12| /6Y | 0 | 1 |
/2Y |4 7414 11| 5A | 1 | 0 |
3A |5 10| /5Y +---*---+
/3Y |6 9| 4A
GND |7 8| /4Y
+----------+

7415

Triple 3-input open-collector AND gates.

+---+--+---+ +---+---+---*---+
1A |1 +--+ 14| VCC | A | B | C | Y | Y = ABC
1B |2 13| 1C +===+===+===*===+
2A |3 12| 1Y | 0 | X | X | 0 |
2B |4 7415 11| 3C | 1 | 0 | X | 0 |
2C |5 10| 3B | 1 | 1 | 0 | 0 |
2Y |6 9| 3A | 1 | 1 | 1 | Z |
GND |7 8| 3Y +---+---+---*---+
+----------+

7416

Hex open-collector high-voltage inverters.

Maximum output voltage is 15V.
+---+--+---+ +---*---+ _
1A |1 +--+ 14| VCC | A |/Y | /Y = A
/1Y |2 13| 6A +===*===+
2A |3 12| /6Y | 0 | Z |
/2Y |4 7416 11| 5A | 1 | 0 |
3A |5 10| /5Y +---*---+
/3Y |6 9| 4A
GND |7 8| /4Y
+----------+

7417

Hex open-collector high-voltage buffers. Maximum output voltage is 15V.

+---+--+---+ +---*---+
1A |1 +--+ 14| VCC | A | Y | Y = A
1Y |2 13| 6A +===*===+
2A |3 12| 6Y | 0 | 0 |
2Y |4 7417 11| 5A | 1 | Z |
3A |5 10| 5Y +---*---+
3Y |6 9| 4A
GND |7 8| 4Y

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+----------+

7418

Dual 4-input NAND gates with schmitt-trigger inputs. 0.8V typical input hysteresis at
VCC=+5V.
+---+--+---+ +---+---+---+---*---+ ____
1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD
1B |2 13| 2D +===+===+===+===*===+
|3 12| 2C | 0 | X | X | X | 1 |
1C |4 7418 11| | 1 | 0 | X | X | 1 |
1D |5 10| 2B | 1 | 1 | 0 | X | 1 |
/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |
GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |
+----------+ +---+---+---+---*---+

7419

Hex inverters with schmitt-trigger line-receiver inputs. 0.8V typical input hysteresis at
VCC=+5V.
+---+--+---+ +---*---+ _
1A |1 +--+ 14| VCC | A |/Y | /Y = A
/1Y |2 13| 6A +===*===+
2A |3 12| /6Y | 0 | 1 |
/2Y |4 7414 11| 5A | 1 | 0 |
3A |5 10| /5Y +---*---+
/3Y |6 9| 4A
GND |7 8| /4Y
+----------+

7420

Dual 4-input NAND gates.

+---+--+---+ +---+---+---+---*---+ ____
1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD
1B |2 13| 2D +===+===+===+===*===+
|3 12| 2C | 0 | X | X | X | 1 |
1C |4 7420 11| | 1 | 0 | X | X | 1 |
1D |5 10| 2B | 1 | 1 | 0 | X | 1 |
/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |
GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |
+----------+ +---+---+---+---*---+

7421

Dual 4-input AND gates.

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+---+--+---+ +---+---+---+---*---+
1A |1 +--+ 14| VCC | A | B | C | D | Y | Y = ABCD
1B |2 13| 2D +===+===+===+===*===+
|3 12| 2C | 0 | X | X | X | 0 |
1C |4 7421 11| | 1 | 0 | X | X | 0 |
1D |5 10| 2B | 1 | 1 | 0 | X | 0 |
1Y |6 9| 2A | 1 | 1 | 1 | 0 | 0 |
GND |7 8| 2Y | 1 | 1 | 1 | 1 | 1 |
+----------+ +---+---+---+---*---+

7422

Dual 4-input open-collector NAND gates.

+---+--+---+ +---+---+---+---*---+ ____
1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD
1B |2 13| 2D +===+===+===+===*===+
|3 12| 2C | 0 | X | X | X | Z |
1C |4 7422 11| | 1 | 0 | X | X | Z |
1D |5 10| 2B | 1 | 1 | 0 | X | Z |
/1Y |6 9| 2A | 1 | 1 | 1 | 0 | Z |
GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |
+----------+ +---+---+---+---*---+

7424

Quad 2-input NAND gates with schmitt-trigger line-receiver inputs. 0.8V typical input
hysteresis at VCC=+5V.
+---+--+---+ +---+---*---+ __
1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | 1 |
2A |4 7424 11| /4Y | 0 | 1 | 1 |
2B |5 10| 3B | 1 | 0 | 1 |
/2Y |6 9| 3A | 1 | 1 | 0 |
GND |7 8| /3Y +---+---*---+
+----------+

7425

Dual 4-input NOR gates with enable input.

+---+--+---+ __________
1A |1 +--+ 14| VCC Y = G(A+B+C+D)
1B |2 13| 2D
1G |3 12| 2C
1C |4 7425 11| 2G
1D |5 10| 2B
/1Y |6 9| 2A
GND |7 8| /2Y
+----------+

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7426

Quad 2-input open-collector high-voltage NAND gates.

Maximum output voltage is 15V.
+---+--+---+ +---+---*---+ __
1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | Z |
2A |4 7426 11| /4Y | 0 | 1 | Z |
2B |5 10| 3B | 1 | 0 | Z |
/2Y |6 9| 3A | 1 | 1 | 0 |
GND |7 8| /3Y +---+---*---+
+----------+

7427

Triple 3-input NOR gates.

+---+--+---+ +---+---+---*---+ _____
1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = A+B+C
1B |2 13| 1C +===+===+===*===+
2A |3 12| /1Y | 0 | 0 | 0 | 1 |
2B |4 7427 11| 3C | 0 | 0 | 1 | 0 |
2C |5 10| 3B | 0 | 1 | X | 0 |
/2Y |6 9| 3A | 1 | X | X | 0 |
GND |7 8| /3Y +---+---+---*---+
+----------+

7428

Quad 2-input NOR gates with buffered outputs.

+---+--+---+ +---+---*---+ ___
/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = A+B
1A |2 13| /4Y +===+===*===+
1B |3 12| 4B | 0 | 0 | 1 |
/2Y |4 7428 11| 4A | 0 | 1 | 0 |
2A |5 10| /3Y | 1 | 0 | 0 |
2B |6 9| 3B | 1 | 1 | 0 |
GND |7 8| 3A +---+---*---+
+----------+

7430

8-input NAND gate.

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+---+--+---+ ________
A |1 +--+ 14| VCC /Y = ABCDEFGH
B |2 13|
C |3 12| H
D |4 7430 11| G
E |5 10|
F |6 9|
GND |7 8| /Y
+----------+

Positive Logic

________
Y = ABCDEFGH

7431

Hex delay elements. Typical delays are 27.5ns (1,6), 46.5ns (2,5), 6ns (3,4). Improved
output currents IoH=-1.2mA, IoL=24mA for gates 3 and 4.
+---+--+---+ _ _____
1A |1 +--+ 16| VCC /1Y=1A /4Y=4A.4B
/1Y |2 15| 6A
2A |3 14| /6Y 2Y=2A 5Y=5A
2Y |4 13| 5A _____ _
3A |5 7431 12| 5Y /3Y=3A.3B /6Y=6A
3B |6 11| 4B
/3Y |7 10| 4A
GND |8 9| /4Y
+----------+

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7432

Quad 2-input OR gates.

+---+--+---+ +---+---*---+
1A |1 +--+ 14| VCC | A | B | Y | Y = A+B
1B |2 13| 4B +===+===*===+
1Y |3 12| 4A | 0 | 0 | 0 |
2A |4 7432 11| 4Y | 0 | 1 | 1 |
2B |5 10| 3B | 1 | 0 | 1 |
2Y |6 9| 3A | 1 | 1 | 1 |
GND |7 8| 3Y +---+---*---+
+----------+

Positive Logic

Y = A+B

7433

Quad 2-input open-collector NOR gates.

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+---+--+---+ +---+---*---+ ___

/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = A+B
1A |2 13| /4Y +===+===*===+
1B |3 12| 4B | 0 | 0 | Z |
/2Y |4 7433 11| 4A | 0 | 1 | 0 |
2A |5 10| /3Y | 1 | 0 | 0 |
2B |6 9| 3B | 1 | 1 | 0 |
GND |7 8| 3A +---+---*---+
+----------+

7437

Quad 2-input NAND gates with buffered output.

+---+--+---+ +---+---*---+ __
1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | 1 |
2A |4 7437 11| /4Y | 0 | 1 | 1 |
2B |5 10| 3B | 1 | 0 | 1 |
/2Y |6 9| 3A | 1 | 1 | 0 |
GND |7 8| /3Y +---+---*---+
+----------+

7438

Quad 2-input open-collector NAND gates with buffered output.

+---+--+---+ +---+---*---+ __
1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB
1B |2 13| 4B +===+===*===+
/1Y |3 12| 4A | 0 | 0 | Z |
2A |4 7438 11| /4Y | 0 | 1 | Z |
2B |5 10| 3B | 1 | 0 | Z |
/2Y |6 9| 3A | 1 | 1 | 0 |
GND |7 8| /3Y +---+---*---+
+----------+

7440

Dual 4-input NAND gates with buffered output.

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+---+--+---+ +---+---+---+---*---+ ____

1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD
1B |2 13| 2D +===+===+===+===*===+
|3 12| 2C | 0 | X | X | X | 1 |
1C |4 7440 11| | 1 | 0 | X | X | 1 |
1D |5 10| 2B | 1 | 1 | 0 | X | 1 |
/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |
GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |
+----------+ +---+---+---+---*---+

7442

1-of-10 inverting decoder/demultiplexer.

+---+--+---+ +---+---+---+---*---+---+---+---+
/Y0 |1 +--+ 16| VCC | S3| S2| S1| S0|/Y0|/Y1|...|/Y9|
/Y1 |2 15| S0 +===+===+===+===*===+===+===+===+
/Y2 |3 14| S1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
/Y3 |4 13| S2 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
/Y4 |5 7442 12| S3 | . | . | . | . | 1 | 1 | . | 1 |
/Y5 |6 11| /Y9 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
/Y6 |7 10| /Y8 | 1 | 0 | 1 | X | 1 | 1 | 1 | 1 |
GND |8 9| /Y7 | 1 | 1 | X | X | 1 | 1 | 1 | 1 |
+----------+ +---+---+---+---*---+---+---+---+

7446, 7447

Open-collector BCD to 7-segment decoder/common-anode LED driver with ripple blank

input and output.7446 has 30V outputs, 7447 has 15V outputs.
+---+--+---+
A1 |1 +--+ 16| VCC
A2 |2 15| /YF
/LT |3 14| /YG
/RBO |4 13| /YA
/RBI |5 7447 12| /YB
A3 |6 11| /YC
A0 |7 10| /YD
GND |8 9| /YE
+----------+

7448

BCD to 7-segment decoder/common-cathode LED driver with ripple blank input and
output.

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+---+--+---+
A1 |1 +--+ 16| VCC
A2 |2 15| YF
/LT |3 14| YG
/RBO |4 13| YA
/RBI |5 7448 12| YB
A3 |6 11| YC
A0 |7 10| YD
GND |8 9| YE
+----------+

Conclusion:
TTL logic family characteristics and ICs are thoroughly studied.

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