Overview of Chapter 6 Memory Definitions

ƒ Memory generators ƒ Memory ─ A collection of storage cells together with

ƒ Random Access Memory the necessary circuits to transfer information to and
ƒ Function from them
ƒ Operation ƒ Memory Organization ─ the basic architectural
ƒ Timing structure of a memory in terms of how data is
ƒ RAM integrated circuits accessed
ƒ RAM Cell ƒ Random Access Memory (RAM) ─ a memory
ƒ RAM Bit Slice organized such that data can be transferred to or
ƒ 3-State Buffers from any cell (or collection of cells) in a time that is
ƒ Cell Array and Coincident Selection not dependent upon the particular cell selected
ƒ Dynamic RAM ƒ Memory Address ─ A collection of binary digits that
ƒ Array of RAM integrated circuits identify a particular memory element (or collection of
ƒ Arrays of Static and Dynamic RAM elements)

Memory Definitions …Contd Memory Organization

ƒ Typical data elements are:
ƒ bit ─ a single binary digit
ƒ byte ─ a collection of eight bits accessed together
ƒ word ─ a collection of binary bits whose size is a typical unit
of access for the memory. It is typically a power of two
multiple of bytes (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.)
ƒ Memory Data ─ a bit or a collection of bits to be
stored into or accessed from memory cells
ƒ Memory Operations ─ operations on memory data
supported by the memory unit. Typically, read and
write operations over some sized data element (bit,
byte, word, etc.)
ƒ Organized as an indexed array of words. Value of the
index for each word is the memory address
ƒ Memory is organized to fit the needs of a particular
computer architecture.
ƒ Some historically significant computer architectures
and their associated memory organization:
ƒ Digital Equipment Corporation PDP-8 – used a 12-bit
address to address 4096 12-bit words
ƒ IBM 360 – used a 24-bit address to address 16,777,216 8-
bit bytes, or 4,194,304 32-bit words
ƒ Intel 8080 – (8-bit predecessor to the 8086 and the current
Intel processors) used a 16-bit address to address 65,536 8-
bit bytes

Memory Block Diagram Memory Organization (Example)

ƒ A basic memory N Data Input Lines
ƒ Example memory Memory Address Memory
system is shown here: N contents: Binary Decimal Content
ƒ K Address Lines are ƒ A memory of 3 000 0 10001111
Memory address bits, 8 data
decoded to address 2K k Address Lines
k
Unit 001 1 11111111
bits will have: 010 2 10110001
Words of memory 2k Words
1 N Bits per Word ƒ k = 3 and N = 8 so 011 3 00000000
ƒ Each Word is N bits Read 23 = 8 Addresses 100 4 10111001
1
ƒ Read and Write are Write labeled 0 to 7 101 5 10000110
single control lines N
ƒ 23 = 8 Words of 8-bit 11 0 6 00110011
defining the simplest of data 111 7 11001100

memory operations N Data Output Lines

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Basic Memory Operations Basic Memory Operations…Contd

ƒ Memory operations require the following:
ƒ Data ─ data written to, or read from, memory as required by
the operation.
ƒ Address ─ used to specify a range of indices the memory is
to operate on. The address lines carry this information to
the memory. Typically: N bits specify locations of 2N words.
ƒ An operation ─ Information sent to the memory and
interpreted as control information which specifies the type of
operation to be performed. Typical operations are READ
DATA, and WRITE DATA. Others are READ followed by
WRITE and a variety of new operations associated with
delivering block of data.
ƒ Read Memory --This operations are used to read a
data value stored in memory
ƒ This action does not change the current value of memory
ƒ Write Memory -- This operations are used to write a
data value to memory:
ƒ This action replaces current value of memory with the value
on input lines
ƒ Sometimes the read or write enable line is defined as
a clock with precise timing information (e.g. Read
Clock, Write Strobe)

Read and Write operations Memory Operation Timing

ƒ Steps for a “Read” operation ƒ The most basic memories are asynchronous
ƒ Apply binary address of the desired word to the ƒ Storage is performed by latches or storage of
address lines electrical charge
ƒ Activate the “read” input ƒ Do not use a clock
ƒ Controlled by application of control inputs and
ƒ Steps for a “Write” operation
address
ƒ Apply the binary address of the desired word to
the address lines ƒ Timing of signal application is critical to the
operation
ƒ Apply the data bits that must be stored in the
memory to the data input lines ƒ See Figure 6-4 in text
ƒ Active the “write” input ƒ Control Signals:
ƒ Relative timing of signals for Write and Read

Memory Operation Timing…Contd Random Access Memory (RAM)

ƒ Access time:
ƒ is related to memory read operation
ƒ is the maximum time from the application of
address (on address lines) to the appearance of
data (on data output lines)
ƒ Write cycle time:
ƒ is the maximum time from the application of the
address to the completion of all internal memory
operations required to store a word
ƒ The CPU must provide control signals at a
rate that does not exceed the access
frequency or write cycle frequency
ƒ RAM is used for holding data and programs being
executed.
ƒ RAM differs from ROM (Read Only Memory) in that it
can be “Read” and “Written”.
ƒ Some facts about RAM
ƒ RAM is volatile Æ contents are lost when power is turned off.
ƒ RAM is also called Read Write Memory (RWM)
ƒ RAM is much faster than ROM
ƒ Question: Is Random Access Memory completely
“Random”? What does “Random” refer to?

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Types of Memory Static RAM (SRAM) features
ƒ Types of memory ƒ SRAM consist of latches to store information
ƒ SRAM (Static Random Access Memory)
ƒ Consists of latches to store information
ƒ SRAM holds data without external refresh
ƒ DRAM (Dynamic Random Access Memory) ƒ It contrasts with DRAM which requires refresh to
ƒ Consists of a transistor and capacitor retain data
ƒ FRAM (Fast Random Access Memory) ƒ SRAMs are implemented with latches and
ƒ Same as SRAM but more compact and fast
ƒ MRAM (Magneto resistive Random Access Memory)
hence are faster than DRAMs
ƒ Advanced RAMs of the future. Use magnetic films to store ƒ SRAMs require large amount of logic for
data
implementation and hence are costly
ƒ RAM integrated circuits are built using arrays of 1-bit
RAM cells

Static RAM Cell Static RAM Bit Slice

ƒ Array of storage cells used to ƒ Represents all of the circuitry that is required
implement static RAM
ƒ Each storage cell consists of:
to store multiple 1-bit words
ƒ A latch ƒ See Figure 6-6 in text as an example
ƒ Cell write logic
ƒ Multiple RAM cells
ƒ Cell read logic
ƒ A logical representation of ƒ Control Lines:
electronic circuitry ƒ Word select i – one for each word
ƒ SR Latch for storage ƒ Bit Select
ƒ Select input for control ƒ Data Lines:
ƒ Dual Rail Data Inputs B andB
ƒ Data in
ƒ Dual Rail Data Outputs C andC
ƒ Data out

Dynamic RAM (DRAM) features Dynamic RAM cell

ƒ DRAM is implemented with transistors and capacitors ƒ Implemented with a
ƒ The capacitor holds logic 1 or 0 and the transistor MOS transistor and a
capacitor.
performs switching action
ƒ If Row Select = 1, then
ƒ Capacitor is a discharging elementÆso the logic level the logic level on Digit
on the capacitor needs to be “refreshed” In/Out Line is stored in
ƒ DRAM ICs consist of circuitry that refresh contents of the capacitor
every location hundreds of times per second Æ ƒ The contents of the
otherwise it loses its memory capacitor are refreshed
ƒ DRAM uses very less area since it consists of a by reading its contents
and loading them back
transistor and a capacitor into it.
ƒ DRAM is slower than SRAM because of capacitor ƒ How many times should
charging and discharging refresh be performed to
retain the data?

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Comparison between SRAM and DRAM RAM Integrated Circuits
SRAM DRAM ƒ RAM IC’s are specified by
Implemented with latches (6- Capacitor based storage.
Transistor / 4-Transistor) ƒ number of words and
Require more area due to Requires very small area ƒ number of bits in each word
more logic
ƒ Example: A 1K x 16 RAM is a memory with a
Fast data access Slow data access than SRAM
Low power consumption Consume large amount of
capacity of 1K words of 16bits each
power due to periodic “refresh” ƒ Total memory size is 1K( = 210 bits) x 16(=24 bits)
Not widely used due to its Used widely due to its high = 214 bits.
bulky nature density and level of integration
ƒ What is the size of the memory expressed in KB
ƒ 214/210 = 24 K bits = 2 K bytes (since 23 bits = 1 byte)
ƒ For more information on different memory types
refer to the eRAMs presentation on course
webpage

n-Word × 1-Bit RAM IC 3-state Buffers and Logic

ƒ To build a RAM IC from a RAM slice, we
need:
ƒ A decoder decodes the log2n address lines to n
word select lines
ƒ A 3-state buffer on the data output permits RAM
ICs to be combined into a RAM with c × n words
ƒ See Figure 6-7 in text as an example
ƒ Add 4-to 16 decoder with address inputs and word
select outputs
ƒ Add 3-state buffer controlled by chip select
ƒ Three-State Logic – Sometimes called tri-state logic
but tri-state is a registered trademark of National
Semiconductor – has three states for logic levels:
ƒ Active high state (output is driven high)
ƒ Active low state (output is driven low)
ƒ High impedance (Hi-Z) state (output is not driven)
ƒ Especially useful for replacing "open collector" wire-
OR or wire-AND oriented busses.
ƒ Often registers made of latches and flip-flops have
three-state outputs.
ƒ Commonly used for memory components

3-State Buffer Basics 3-State Logic Basics…Contd

ƒ The basic 3-State Buffer is ƒ Making Multiplexers with IN0
shown: Tri-state Devices:
IN OUT OL
ƒ Hi-Z: Means the output is S EN0
not "driven" EN1 EN0 IN1 IN0 OL
EN 0 0 X X Hi -Z IN1
ƒ The output "floats" to some
level which is usually neither 0 1 X 0 0 EN1
the "1" nor "0" in this state. 0 1 X 1 1
EN IN OUT
ƒ When EN = "1", the output 1 0 0 X 0
follows the input. 0 X Hi-Z
1 0 1 X 1
ƒ The buffer can also invert 1 0 0 1 1 0 0 0
data 1 1 1 1 1 1 1 1
ƒ EN can be an inverted
signal 1 1 1 0 damage
1 1 0 1 damage

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Cell Arrays and Coincident Selection RAM ICs with > 1 Bit/Word
ƒ Memory arrays can be very large ƒ Word length can be quite high.
ƒ Large decoders
ƒ To better balance the number of words and
ƒ Large fanouts for the bit lines
word length, use ICs with > 1 bit/word
ƒ The decoder size and fanouts can be reduced to
approximately n by using a coincident selection in a ƒ See Figure 6-11 for example
2-dimensional array ƒ 2 Data input bits
ƒ Uses two decoders, one for words and one for bits ƒ 2 Data output bits
ƒ Word select becomes Row select
ƒ Row select selects 4 rows
ƒ Bit select becomes Column select
ƒ Column select selects 2 pairs of columns
ƒ See Figure 6-10 for example
ƒ A3 and A2 used for Row select
ƒ A1 and A0 for Column select