Dual 160 MHz

Rail-to-Rail Amplifier
AD8042
FEATURES CONNECTION DIAGRAM
Single AD8041 and quad AD8044 also available
OUT1 1 8 +VS
Fully specified at +3 V, +5 V, and ±5 V supplies
Output swings to within 30 mV of either rail –IN1 2 7 OUT2
Input voltage range extends 200 mV below ground
+IN1 3 6 –IN2
No phase reversal with inputs 0.5 V beyond supplies

01059-001
Low power of 5.2 mA per amplifier –VS 4 5 +IN2
AD8042
High speed and fast settling on 5 V
Figure 2. 8-Lead PDIP and 8-Lead SOIC_N
160 MHz, −3 dB bandwidth (G = +1)
200 V/μs slew rate The output voltage swing extends to within 30 mV of each rail,
39 ns settling time to 0.1% providing the maximum output dynamic range. Additionally, it
Good video specifications (RL = 150 Ω, G = +2) features gain flatness of 0.1 dB to 14 MHz while offering differential
Gain flatness of 0.1 dB to 14 MHz gain and phase error of 0.04% and 0.06° on a single 5 V supply.
0.02% differential gain error This combination of features makes the AD8042 useful for
0.04° differential phase error professional video electronics, such as cameras, video switchers,
Low distortion: −64 dBc worst harmonic @ 10 MHz or any high speed portable equipment. The low distortion and
Drives 50 mA 0.5 V from supply rails fast settling of the AD8042 make it ideal for buffering single-
supply, high speed analog-to-digital converters (ADCs).
APPLICATIONS
The AD8042 offers a low power supply current of 12 mA
Video switchers
maximum and can run on a single 3.3 V power supply. These
Distribution amplifiers
features are ideally suited for portable and battery-powered
Analog-to-digital drivers
applications where size and power are critical.
Professional cameras
CCD Imaging systems The wide bandwidth of 160 MHz along with 200 V/μs of slew
Ultrasound equipment (multichannel) rate on a single 5 V supply make the AD8042 useful in many
general-purpose, high speed applications where single supplies
GENERAL DESCRIPTION from +3.3 V to +12 V and dual power supplies of up to ±6 V are
needed. The AD8042 is available in 8-lead PDIP and 8-lead
The AD8042 is a low power voltage feedback, high speed amplifier
SOIC_N packages.
designed to operate on +3 V, +5 V, or ±5 V supplies. It has true
15
single-supply capability with an input voltage range extending VS = 5V
200 mV below the negative rail and within 1 V of the positive rail. 12 G = +1
CL = 5pF
9 RL = 2kΩ TO 2.5V
CLOSED-LOOP GAIN (dB)

G = +1
RL = 2kΩ TO 2.5V 6

3
5.0V
0

–3

2.5V –6

–9
01059-003

–12
0V
–15
1 10 100 500
FREQUENCY (MHz)
01059-002

1V 1µs
Figure 3. Frequency Response
Figure 1. Output Swing: Gain = +1, VS = +5 V

Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
AD8042

TABLE OF CONTENTS
Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7

Applications....................................................................................... 1 Applications Information .............................................................. 12

General Description ......................................................................... 1 Circuit Description .................................................................... 12

Connection Diagram ....................................................................... 1 Driving Capacitive Loads.......................................................... 12

Revision History ............................................................................... 2 Overdrive Recovery ................................................................... 12

Specifications..................................................................................... 3 Layout Considerations............................................................... 15

Absolute Maximum Ratings............................................................ 6 Outline Dimensions ....................................................................... 16

Maximum Power Dissipation ..................................................... 6 Ordering Guide .......................................................................... 16

ESD Caution.................................................................................. 6

REVISION HISTORY
12/07—Rev. D to Rev. E
Changes to Figure 1 Caption........................................................... 1
Changes to Table 1............................................................................ 3
Changes to Figure 5.......................................................................... 7
Changes to Figure 20........................................................................ 9
Changes to Layout and Figure 35 ................................................. 12
Changes to Figure 38...................................................................... 13
Changes to Single-Ended-to-Differential Driver Section ......... 14
Updated Outline Dimensions ....................................................... 16

3/06—Rev. C to Rev. D
Changes to Text Prior to Table 2..................................................... 4

8/04—Rev. B to Rev. C
Changes to Ordering Guide ............................................................ 5
Changes to Outline Dimensions................................................... 15

7/02—Rev. A to Rev. B
Changes to Specifications ................................................................ 2

Rev. E | Page 2 of 16
 AD8042

SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth, VO < 0.5 V p-p G = +1 125 160 MHz
Bandwidth for 0.1 dB Flatness G = +2, RL = 150 Ω, RF = 200 Ω 14 MHz
Slew Rate G = –1, VOUT = 2 V step 130 200 V/μs
Full Power Response VO = 2 V p-p 30 MHz
Settling Time to 1% G = –1, VOUT = 2 V step 26 ns
Settling Time to 0.1% 39 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VOUT = 2 V p-p, G = +2, RL = 1 kΩ –73 dB
Input Voltage Noise f = 10 kHz 15 nV/√Hz
Input Current Noise f = 10 kHz 700 fA/√Hz
Differential Gain Error (NTSC, 100 IRE) G = +2, RL = 150 Ω to 2.5 V 0.04 0.06 %
G = +2, RL = 75 Ω to 2.5 V 0.04 %
Differential Phase Error (NTSC, 100 IRE) G = +2, RL = 150 Ω to 2.5 V 0.06 0.12 Degrees
G = +2, RL = 75 Ω to 2.5 V 0.24 Degrees
Worst-Case Crosstalk f = 5 MHz, RL = 150 Ω to 2.5 V –63 dB
DC PERFORMANCE
Input Offset Voltage 3 9 mV
TMIN to TMAX 12 mV
Offset Drift 12 μV/°C
Input Bias Current 1.2 3.2 μA
TMIN to TMAX 4.8 μA
Input Offset Current 0.2 0.5 μA
Open-Loop Gain RL = 1 kΩ 90 100 dB
TMIN to TMAX 90 dB
INPUT CHARACTERISTICS
Input Resistance 300 kΩ
Input Capacitance 1.5 pF
Input Common-Mode Voltage Range −0.2 to +4 V
Common-Mode Rejection Ratio VCM = 0 V to 3.5 V 68 74 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 10 kΩ to 2.5 V 0.03 to 4.97 V
RL = 1 kΩ to 2.5 V 0.10 to 4.9 0.05 to 4.95 V
RL = 50 Ω to 2.5 V 0.4 to 4.4 0.36 to 4.45 V
Output Current TMIN to TMAX, VOUT = 0.5 V to 4.5 V 50 mA
Short-Circuit Current Sourcing 90 mA
Sinking 100 mA
Capacitive Load Drive G = +1 20 pF
POWER SUPPLY
Operating Range 3 12 V
Quiescent Current (Per Amplifier) 5.5 6.4 mA
Power Supply Rejection Ratio VS– = 0 V to −1 V, or VS+ = 5 V to 6 V 72 80 dB
OPERATING TEMPERATURE RANGE −40 +85 °C

Rev. E | Page 3 of 16
AD8042
TA = 25°C, VS = 3 V, RL = 2 kΩ to 1.5 V, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth, VO < 0.5 V p-p G = +1 120 140 MHz
Bandwidth for 0.1 dB Flatness G = +2, RL = 150 Ω, RF = 200 Ω 11 MHz
Slew Rate G = −1, VOUT = 2 V step 120 170 V/μs
Full Power Response VO = 2 V p-p 25 MHz
Settling Time to 1% G = −1, VOUT = 1 V step 30 ns
Settling Time to 0.1% 45 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VOUT = 2 V p-p, G = −1, RL = 100 Ω –56 dB
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 500 fA/√Hz
Differential Gain Error (NTSC, 100 IRE) G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V 0.10 %
RL = 75 Ω to 1.5 V, Input VCM = 1 V 0.10 %
Differential Phase Error (NTSC, 100 IRE) G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V 0.12 Degrees
RL = 75 Ω to 1.5 V, Input VCM = 1 V 0.27 Degrees
Worst-Case Crosstalk f = 5 MHz, RL = 1 kΩ to 1.5 V –68 dB
DC PERFORMANCE
Input Offset Voltage 3 9 mV
TMIN to TMAX 12 mV
Offset Drift 12 μV/°C
Input Bias Current 1.2 3.2 μA
TMIN to TMAX 4.8 μA
Input Offset Current 0.2 0.6 μA
Open-Loop Gain RL = 1 kΩ 90 100 dB
TMIN to TMAX 90 dB
INPUT CHARACTERISTICS
Input Resistance 300 kΩ
Input Capacitance 1.5 pF
Input Common-Mode Voltage Range –0.2 to +2 V
Common-Mode Rejection Ratio VCM = 0 V to 1.5 V 66 74 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 10 kΩ to 1.5 V 0.03 to 2.97 V
RL = 1 kΩ to 1.5 V 0.1 to 2.9 0.05 to 2.95 V
RL = 50 Ω to 1.5 V 0.3 to 2.6 0.25 to 2.65 V
Output Current TMIN to TMAX, VOUT = 0.5 V to 2.5 V 50 mA
Short-Circuit Current Sourcing 50 mA
Sinking 70 mA
Capacitive Load Drive G = +1 17 pF
POWER SUPPLY
Operating Range 3 12 V
Quiescent Current (Per Amplifier) 5.5 6.4 mA
Power Supply Rejection Ratio VS– = 0 V to –1 V, or VS+ = 3 V to 4 V 68 80 dB
OPERATING TEMPERATURE RANGE 0 70 °C

Rev. E | Page 4 of 16
 AD8042
TA = 25°C, VS = ±5 V, RL = 2 kΩ to 0 V, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth, VO < 0.5 V p-p G = +1 125 170 MHz
Bandwidth for 0.1 dB Flatness G = +2, RL = 150 Ω, RF = 200 Ω 18 MHz
Slew Rate G = −1, VOUT = 2 V step 145 225 V/μs
Full Power Response VO = 2 V p-p 35 MHz
Settling Time to 1% G = −1, VOUT = 2 V step 22 ns
Settling Time to 0.1% 32 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ –78 dB
Input Voltage Noise f = 10 kHz 15 nV/√Hz
Input Current Noise f = 10 kHz 700 fA/√Hz
Differential Gain Error (NTSC, 100 IRE) G = +2, RL = 150 Ω 0.02 0.05 %
G = +2, RL = 75 Ω 0.02 %
Differential Phase Error (NTSC, 100 IRE) G = +2, RL = 150 Ω 0.04 0.10 Degrees
G = +2, RL = 75 Ω 0.12 Degrees
Worst-Case Crosstalk f = 5 MHz, RL = 150 Ω –63 dB
DC PERFORMANCE
Input Offset Voltage 3 9.8 mV
TMIN to TMAX 14 mV
Offset Drift 12 μV/°C
Input Bias Current 1.2 3.2 μA
TMIN to TMAX 4.8 μA
Input Offset Current 0.2 0.6 μA
Open-Loop Gain RL = 1 kΩ 90 94 dB
TMIN to TMAX 86 dB
INPUT CHARACTERISTICS
Input Resistance 300 kΩ
Input Capacitance 1.5 pF
Input Common-Mode Voltage Range −5.2 to +4 V
Common-Mode Rejection Ratio VCM = –5 V to +3.5 V 66 74 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 10 kΩ −4.97 to +4.97 V
RL = 1 kΩ −4.8 to +4.8 −4.9 to +4.9 V
RL = 50 Ω −4 to +3.2 −4.2 to +3.5 V
Output Current TMIN to TMAX, VOUT = −4.5 V to +4.5 V 50 mA
Short-Circuit Current Sourcing 100 mA
Sinking 100 mA
Capacitive Load Drive G = +1 25 pF
POWER SUPPLY
Operating Range 3 12 V
Quiescent Current (Per Amplifier) 6 7 mA
Power Supply Rejection Ratio VS– = −5 V to −6 V, or VS+ = 5 V to 6 V 68 80 dB
OPERATING TEMPERATURE RANGE −40 +85 °C

Rev. E | Page 5 of 16
AD8042

ABSOLUTE MAXIMUM RATINGS

Table 4. Exceeding a junction temperature of 175°C for an extended
Parameter Rating period can result in device failure.
Supply Voltage 12.6 V
Internal Power Dissipation1 While the AD8042 is internally short-circuit protected, this
8-Lead PDIP (N) 1.3 W may not be sufficient to guarantee that the maximum junction
8-Lead SOIC_N (R) 0.9 W temperature (150°C) is not exceeded under all conditions. To
Input Voltage (Common Mode) ±VS ± 0.5 V ensure proper operation, it is necessary to observe the
Differential Input Voltage ±3.4 V maximum power derating curves.
Output Short-Circuit Duration Observe Power 2.0
Derating Curves
8-LEAD PLASTIC-DIP PACKAGE
Storage Temperature Range (N, R) −65°C to +125°C

MAXIMUM POWER DISSIPATION (W)

Lead Temperature (Soldering, 10 sec) 300°C 1.5
1
Specification is for the device in free air: TJ = 150°C
8-Lead PDIP: θJA = 90°C/W
8-Lead SOIC_N: θJA = 155°C/W.
1.0

Stresses above those listed under Absolute Maximum Ratings

8-LEAD SOIC PACKAGE
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any 0.5

other conditions above those indicated in the operational

01059-004
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect 0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
device reliability. AMBIENT TEMPERATURE (°C)

Figure 4. Maximum Power Dissipation vs. Temperature

MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the ESD CAUTION
AD8042 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Exceeding this limit temporarily
can cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.

Rev. E | Page 6 of 16
 AD8042

TYPICAL PERFORMANCE CHARACTERISTICS

100 100
VS = 5V VS = 5V
90 T = 25°C T = 25°C
140 PARTS, SIDE 1 & 2 95
80 MEAN = –1.52mV
STD DEVIATION = 1.15
SAMPLE SIZE = 280

OPEN-LOOP GAIN (dB)

70
(140 AD8042s) 90
FREQUENCY

60

50 85

40
80
30

20
75

01059-005

01059-008
10

0 70
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 0 250 500 750 1000 1250 1500 1750 2000
VOS (mV) LOAD RESISTANCE (Ω)

Figure 5. Typical Distribution of VOS Figure 8. Open-Loop Gain vs. RL to 2.5 V

30
VS = 5V 100
MEAN = –12.6µV/°C VS = 5V
STD DEVIATION = 2.02µV/°C RL = 1kΩ
25
SAMPLE SIZE = 60 98

20 96
OPEN-LOOP GAIN (dB)
FREQUENCY

15 94

92
10

90
5
01059-006

88

01059-009
0
–18 –16 –14 –12 –10 –8 –6 –4 –2 0 86
VOS DRIFT (µV/°C) –40 –20 0 20 40 60 80
TEMPERATURE (°C)
Figure 6. VOS Drift Over −40°C to +85°C
Figure 9. Open-Loop Gain vs. Temperature

0
VS = 5V 100
–0.2 VCM = 0V
VS = 5V

–0.4 90
RL = 500Ω TO 2.5V
INPUT BIAS CURRENT (µA)

–0.6
OPEN-LOOP GAIN (dB)

–0.8 80

–1.0
70
RL = 50Ω TO 2.5V
–1.2

–1.4 60
–1.6

50
01059-007

–1.8
01059-010

–2.0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 40
TEMPERATURE (°C) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
Figure 7. IB vs. Temperature
Figure 10. Open-Loop Gain vs. Output Voltage

Rev. E | Page 7 of 16
AD8042
0.04
NTSC SUBCARRIER (3.579MHz) VS = +5V
0.03 G = +2

GAIN ERROR (%)

300 RL = 150Ω TO 2.5V

DIFFERENTIAL
INPUT VOLTAGE NOISE (nV/ Hz)

0.02
VS = ±5V
100 0.01 G = +2
RL = 150Ω
0
30
–0.01
0.05
10 VS = +5V

PHASE ERROR (Degrees)

0.04 G = +2
RL = 150Ω TO 2.5V

DIFFERENTIAL
3 0.03
0.02
1 0.01 VS = ±5V

01059-011

01059-014
G = +2
0 RL = 150Ω
–0.01
10 100 1k 10k 100k 1M 10M 100M 1G 0 10 20 30 40 50 60 70 80 90 100
FREQUENCY (Hz) MODULATING RAMP LEVEL (IRE)
Figure 11. Input Voltage Noise vs. Frequency Figure 14. Differential Gain and Phase Errors

–30 0.6
VS = 5V
VS = 3V, AV = –1, 0.5 G = +2
TOTAL HARMONIC DISTORTION (dBc)

–40 RL = 100Ω TO 1.5V RF = 200Ω

0.4 RL = 150Ω TO 2.5V

–50 VS = 5V, AV = +2,

NORMALIZED GAIN (dB)

RL = 100Ω TO 2.5V 0.3

–60 VS = 5V, AV = +1, 0.2

RL = 100Ω TO 2.5V
0.1
–70
0 14MHz
–80 –0.1
VS = 5V, AV = +2,
RL = 1kΩ TO 2.5V –0.2
–90
VS = 5V, AV = +1,
01059-012

01059-015
RL = 1kΩ TO 2.5V –0.3
–100 –0.4
1 2 3 4 5 6 7 8 9 10 1 10 100 500
FUNDAMENTAL FREQUENCY (MHz) FREQUENCY (MHz)
Figure 12. Total Harmonic Distortion vs. Frequency Figure 15. 0.1 dB Gain Flatness

–30 120
VS = 5V, G = +2, VS = 5V
RL = 1kΩ TO 2.5V G = +2
–40 100
RF = 200Ω
80 RL = 150Ω TO 2.5V
–50
WORST HARMONIC (dBc)

GAIN
10MHz
OPEN-LOOP GAIN (dB)

60 45

PHASE (Degrees)
–60
40 0
5MHz
–70 20 –45
PHASE
–80 0 –90

1MHz –20 –135

–90
–40 –180
–100
01059-013

01059-016

–60 –225

–110 –80 –270

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.01 0.1 1 10 100 500
OUTPUT VOLTAGE (V p-p) FREQUENCY (MHz)
Figure 13. Worst Harmonic vs. Output Voltage Figure 16. Open-Loop Gain and Phase vs. Frequency

Rev. E | Page 8 of 16
 AD8042
10 60
VS = 5V G = –1
G = +1 VS = +3V, 0.1%
8 RL = 2kΩ TO MIDPOINT
CL = 5pF 55 CL = 5pF
RL = 2kΩ TO 2.5V T = +85°C
6
50
CLOSED-LOOP GAIN (dB)

SETTLING TIME (ns)

2 T = +25°C 45
VS = +3V, 1%
0 T = –40°C 40
VS = +5V, 0.1%
–2
35 VS = ±5V, 0.1%
–4
30
–6
VS = +5V, 1%
25

01059-017

01059-020
–8
VS = ±5V, 1%
–10 20
1 10 100 500 0.5 1.0 1.5 2.0
FREQUENCY (MHz) INPUT STEP (V)

Figure 17. Closed-Loop Frequency Response vs. Temperature Figure 20. Settling Time vs. Input Voltage

12
G = +1 VS = +3V TEST CIRCUIT: 1.02kΩ
VS = 5V
10 CL = 5pF RL AND CL TO 1.5V 0 1.02kΩ
RL = 2kΩ

COMMON-MODE REJECTION (dB)

8 VS = +5V –10 INCM OUT
RL AND CL TO 2.5V
CLOSED-LOOP GAIN (dB)

6 VS = ±5V –20 1.02kΩ

1.02kΩ
4 –30

2 –40

0 –50

–2 –60

–4 –70

01059-021
01059-018

–6 –80

–8 –90
1 10 100 500 10k 100k 1M 10M 100M 500M
FREQUENCY (MHz) FREQUENCY (Hz)

Figure 18. Closed-Loop Frequency Response vs. Supply Figure 21. Common-Mode Rejection vs. Frequency

VS = 5V 0.8

100 G = +1 VS = 5V
RBT = 50Ω 0.7
OUTPUT SATURATION VOLTAGE (V)

5V – VOH (+125°C)
OUTPUT RESISTANCE (Ω)

0.6 5V – VOH (+25°C)

10
RBT = 0Ω 5V – VOH (–55°C)
RBT 0.5
VOUT
1 0.4

0.3
0.1
0.2
+VOL (+125°C)
01059-019

0.01 0.1 +VOL (+25°C)

01059-022

+VOL (–55°C)
0
0.01 0.1 1 10 100 500 0 5 10 15 20 25 30 35 40 45 50
FREQUENCY (MHz) LOAD CURRENT (mA)

Figure 19. Output Resistance vs. Frequency Figure 22. Output Saturation Voltage vs. Load Current

Rev. E | Page 9 of 16
AD8042
12.0 50
VS = ±5V VS = 5V
VOUT = 100mV STEP
11.5
40
11.0
SUPPLY CURRENT (mA)

G = +2
VS = +5V

OVERSHOOT (%)
10.5
30

10.0

VS = +3V 20
9.5
G = +3
9.0
10
8.5

01059-023

01059-026
8.0 0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 0 20 40 60 80 100 120 140 160 180 200
TEMPERATURE (°C) LOAD CAPACITANCE (pF)

Figure 23. Supply Current vs. Temperature Figure 26. Overshoot vs. Load Capacitance

10 6
VS = 5V VS = 5V
0 5 RF = 2kΩ
RL = 2kΩ to 2.5V
–10 4

NORMALIZED GAIN (dB)

–20 3
G = +2
–30 2
PSRR (dB)

–40 1
–PSRR
–50 0
+PSRR G = +2
–60 –1 RF = 200Ω
G = +10
–70 –2
G = +5
01059-024

01059-027
–80 –3

–90 –4
10k 100k 1M 10M 100M 500M 1 10 100 500
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 24. PSRR vs. Frequency Figure 27. Closed-Loop Gain vs. Frequency Response

10 –10
VS = ±5V VS = 5V
9 RL = 2kΩ –20 VIN = 0.6V p-p
G = –1 G = +2
–30 RF = 1kΩ
8
VOUT1
OUTPUT VOLTAGE (V p-p)

, RL = 1kΩ TO 2.5V
7 –40 VOUT2
CROSSTALK (dB)

VOUT1
6 –50 , RL = 150Ω TO 2.5V
VOUT2
5 –60

4 –70

3 –80 VOUT2
, RL = 150Ω TO 2.5V
VOUT1
2 –90
VOUT2
01059-028
01059-025

1 –100 , RL = 1kΩ TO 2.5V

VOUT1
0 –110
0.1 1 10 100 0.1 1 10 100 200
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 25. Output Voltage vs. Frequency Figure 28. Crosstalk (Output-to-Output) vs. Frequency

Rev. E | Page 10 of 16
 AD8042
5V
VS = 5V AV = 1
4.770V VS = 5V
G = –1 2.6V
RL = 150Ω TO 2.5V VIN = 100mV p-p
4V CL = 5pF
RL = 1kΩ TO 2.5V

3V

2.5V

2V

1V

0.160V 2.4V

01059-032
01059-029
0.5V 200µs 25mV 10ns
0V

Figure 29. Output Swing with Load Reference to Supply Midpoint Figure 32. 100 mV Pulse Response, VS = 5 V

5V
VS = 5V G = –1
G = –1 RL = 2kΩ TO 1.5V
RL = 150Ω TO GND
4V 4.59V 3.0V

3V

1.5V

2V

1V 0V
0.035V

01059-033
01059-030

0.5V 200µs 0.5V 1µs

0V

Figure 30. Output Swing with Load Reference to Negative to Supply Figure 33. Rail-to-Rail Output Swing, VS = 3 V

4.5V
AV = 2 AV = 1
VS = 5V 1.6V VS = 3V
CL = 5pF VIN = 100mV p-p
RL = 1kΩ TO 2.5V CL = 5pF
3.5V VIN = 1V p-p RL = 1kΩ TO 1.5V

2.5V 1.5V

1.5V

1.4V
01059-034
01059-031

0.5V 10ns 25mV 10ns

0.5V

Figure 31. 1 V Pulse Response, VS = 5 V Figure 34. 100 mV Pulse Response, VS = 3 V

Rev. E | Page 11 of 16
AD8042

APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION DRIVING CAPACITIVE LOADS
The AD8042 is fabricated on the Analog Devices, Inc., The capacitive load drive of the AD8042 can be increased by
proprietary eXtra-Fast Complementary Bipolar (XFCB) adding a low valued resistor in series with the load. Figure 36
process, which enables the construction of PNP and NPN shows the effects of a series resistor on capacitive drive for
transistors with similar fts in the 2 GHz to 4 GHz region. The varying voltage gains. As the closed-loop gain is increased, the
process is dielectrically isolated to eliminate the parasitic and larger phase margin allows for larger capacitive loads with less
latch-up problems caused by junction isolation. These features overshoot. Adding a series resistor with lower closed-loop gains
allow the construction of high frequency, low distortion accomplishes the same effect. For large capacitive loads, the
amplifiers with low supply currents. This design uses a frequency response of the amplifier is dominated by the roll-off
differential output input stage to maximize bandwidth and of the series resistor and capacitive load.
headroom (see Figure 35). The smaller signal swings required 1000
VS = 5V
on the first stage outputs (nodes SIP, SIN) reduce the effect of 200mV STEP WITH 90% OVERSHOOT
nonlinear currents due to junction capacitances and improve
RS RS = 5Ω
the distortion performance. With this design, harmonic distortion

CAPACITIVE LOAD (pF)

of better than −77 dB @ 1 MHz into 100 Ω with VOUT = 2 V p-p CL
(gain = +2) on a single 5 V supply is achieved.
RS = 0Ω
VCC 100
I1 I10 I2 I3 Q25 Q50 I9
R26 R39
Q36
Q4 Q5 Q51 Q39 I5
Q23 VEE
Q40 RS = 20Ω
R15 R2
VEE Q22 R23 R27

01059-037
Q7 Q31 C3
VINP Q13 Q17 VOUT
Q21 Q27 10
VINN
1 2 3 4 5
SIN C9
SIP
CLOSED-LOOP GAIN (V/V)

Q2 Q11 Q8 Figure 36. Capacitive Load Drive vs. Closed-Loop Gain

Q3 Q24 Q47 I8

I7 VCC OVERDRIVE RECOVERY

01059-036

C7 R5 R21 R3
VEE
Overdrive of an amplifier occurs when the output and/or input
Figure 35. Simplified Schematic range are exceeded. The amplifier must recover from this overdrive
condition. As shown in Figure 37, the AD8042 recovers within
The rail-to-rail output range of the AD8042 is provided by a
30 ns from negative overdrive and within 25 ns from positive
complementary common-emitter output stage. High output
overdrive.
drive capability is provided by injecting all output stage predriver
currents directly into the bases of the output devices Q8 and
Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5, along
with a common-mode feedback loop (not shown). This circuit
5.0V
topology allows the AD8042 to drive 40 mA of output current
with the outputs within 0.5 V of the supply rails.

On the input side, the device can handle voltages from 0.2 V 2.5V

below the negative rail to within 1.2 V of the positive rail.

Exceeding these values does not cause phase reversal; however,
the input ESD devices do begin to conduct if the input voltages 0V
G = +2
exceed the rails by greater than 0.5 V. VS = 5V
VIN = 5V p-p
01059-035

1V RL = 1kΩ TO 2.5V 50ns

Figure 37. Overdrive Recovery

Rev. E | Page 12 of 16

Single-Supply Composite Video Line Driver
The two op amps of an AD8042 can be configured as a single-
supply dual line driver for composite video. The wide signal
swing of the AD8042 enables this function to be performed
without using any type of clamping or dc restore circuit, which
can cause signal distortion.
AD8042
The other extreme is for a video signal that is full white
everywhere. The blanking intervals and sync tips of such a
signal have negative going excursions in compliance with
composite video specifications. The combination of horizontal
and vertical blanking intervals limit such a signal to being at its
highest level (white) for only about 75% of the time.

Figure 38 shows a schematic for a circuit that is driven by a As a result of the duty cycle variations between the two extremes
single composite video source that is ac-coupled, level-shifted presented, a 1 V p-p composite video signal that is multiplied by
and applied to both noninverting inputs of the two amplifiers. a gain of 2 requires about 3.2 V p-p of dynamic voltage swing at
Each op amp provides a separate 75 Ω composite video output. the output for an op amp to pass a composite video signal of
To obtain single-supply operation, ac coupling is used throughout. arbitrary duty cycle without distortion.
The large capacitor values are required to ensure that there is
minimal tilting of the video signals due to their low frequency Some circuits use a sync tip clamp along with ac coupling to
(30 Hz) signal content. The circuit shown was measured to have hold the sync tips at a relatively constant level, which lowers the
a differential gain of 0.06% and a differential phase of 0.06°. amount of dynamic signal swing required. However, these
circuits can have artifacts, such as sync tip compression, unless
The input is terminated in 75 Ω and ac-coupled via CIN to a they are driven by sources with very low output impedance.
voltage divider that provides the dc bias point to the input.
Setting the optimal bias point requires some understanding The AD8042 not only has ample signal swing capability to handle
of the nature of composite video signals and the video the dynamic range required without using a sync tip clamp but
performance of the AD8042. also has good video specifications such as differential gain and
differential phase when buffering these signals in an ac-coupled
+5V
configuration.
4.99kΩ
0.1µF 10µF
10µF To test the dynamic range, the differential gain and differential
4.99kΩ 75Ω
3 8 1000µF COAX
1 phase were measured for the AD8042 while the supplies were
2 VOUT
COMPOSITE RF RT RL varied. As the lower supply is raised to approach the video
VIDEO IN 1kΩ 75Ω 75Ω
75Ω
0.1µF signal, the first effect observed is that the sync tips become
RG
10kΩ
1kΩ
compressed before the differential gain and differential phase are
220µF adversely affected. Therefore, there must be adequate swing in
the negative direction to pass the sync tips without compression.
5 1000µF
7
6 VOUT As the upper supply is lowered to approach the video, the
RT RL
4
75Ω 75Ω differential gain and differential phase was not significantly
0.1µF
affected until the difference between the peak video output
RG RF
1kΩ 1kΩ and the supply reached 0.6 V. Therefore, the highest video level
01059-038

220µF should be kept at least 0.6 V below the positive supply rail.

Figure 38. Single-Supply Composite Video Line Driver Using AD8042
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capability than their peak-
to-peak amplitude after ac coupling. As a worst case, the dynamic
signal swing required approaches twice the peak-to-peak value.
The two bounding cases are for a duty cycle that is mostly low,
but occasionally goes high at a fraction of a percent duty cycle,
and vice versa.
Composite video is not quite this demanding. One bounding
extreme is for a signal that is mostly black for an entire frame
but has a white (full intensity), minimum width spike at least
once per frame.
Therefore, it was found that the optimal point to bias the
noninverting input is at 2.2 V dc. Operating at this point, the
worst-case differential gain is measured at 0.06% and the worst-
case differential phase is 0.06°.
The ac-coupling capacitors used in the circuit at first glance
appear quite large. A composite video signal has a lower frequency
band edge of 30 Hz. The resistances at the various ac coupling
points, especially at the output, are quite small. To minimize
phase shifts and baseline tilt, the large value capacitors are required.
For video system performance that is not to be of the highest
quality, the value of these capacitors can be reduced by a factor
of up to five with only a slightly observable change in the picture
quality.

Rev. E | Page 13 of 16
AD8042
Single-Ended-to-Differential Driver
Using a cross-coupled, single-ended-to-differential converter
(SEDC), the AD8042 makes a good general-purpose differential
line driver. This SEDC can be used for applications such as
driving Category-5 (CAT-5) twisted pair wires. Figure 39 shows
a configuration for a circuit that performs this function that can
be used for video transmission over a differential pair or various
data communication purposes.
+5V
The cable has a characteristic impedance of about 120 Ω. Each
driver output is back terminated with a pair of 60.4 Ω resistors
to make the source look like 120 Ω. The receive end is terminated
with 121 Ω, and the signal is measured differentially with a pair
of scope probes. One channel on the oscilloscope is inverted
and then the signals are added.
Figure 40 shows the results of the circuit in Figure 39 driving
50 meters of CAT-5 cable.

0.1µF 10µF 1V 200mV 50ns

RIN 100

1kΩ 3 RF
VIN 8 VIN 90
1kΩ 60.4Ω
1
49.9Ω 2 AMP1

RA
1kΩ 50m

RB RB VOUT
121Ω
AD8042 1kΩ 1kΩ
VOUT
RA 10

1kΩ
6 0%

7 60.4Ω

01059-040
5 AMP2 200mV
4
100Ω
01059-039

0.1µF 10µF Figure 40. Differential Driver Frequency Response

–5V

Figure 39. Single-Ended-to-Differential Twisted Pair Line Driver Single-Supply Differential A/D Driver
The single-ended-to-differential converter circuit is also useful
Each of the op amps of the AD8042 is configured as a unity gain
as a differential driver for video speed, single-ended, differential
follower by the feedback resistors (RA). Each op amp output also
input ADCs. Figure 41 is a schematic that shows such a circuit
drives the other as a unity gain inverter via RB, creating a totally
differentially driving an AD9220, a 12-bit, 10 MSPS ADC.
B

symmetrical circuit.
+5V
If the noninverting input of AMP2 is grounded and a small
+5V 0.1µF
positive signal is applied to the noninverting input of AMP1,
the output of AMP1 is driven to saturation in the positive 0.1µF 1kΩ
1kΩ 3 8
direction and the input of AMP2 is driven to saturation in the VIN 1
negative direction. This is similar to the way a conventional op 2 +5V +5V +5V

amp behaves without any feedback. 1kΩ 0.1µF 0.1µF 0.1µF

28 15 26
If a resistor (RF) is connected from the output of AMP2 to the AD8042 1kΩ 1kΩ
DVDD AVDD AVDD
noninverting input of AMP1, negative feedback is provided, which +5V 14
1kΩ VINA OTR
closes the loop. An input resistor (RIN) makes the circuit look 6
BIT 1
13
2.49kΩ 7
like a conventional inverting op amp configuration with VINB 12
5 BIT 2
11
4 BIT 3
differential outputs. 2.49kΩ 0.1µF 10
CAPT BIT 4
0.1µF AD9220 9
BIT 5
The gain of this circuit from input to either output is ±RF/RIN, or 10/16 0.1µF
BIT 6
8
CAPB
7
the single-ended-to-differential gain is 2 × RF/RIN. This gives the 0.1µF 18 BIT 7
VREF 6
circuit the advantage of being able to adjust its gain by changing 17 BIT 8
SENSE 5
BIT 9
a single resistor. 22 4
CML BIT 10
0.1µF 3
BIT 11
1 2
CLOCK CLK BIT 12

REFCOM DVSS AVSS AVSS

01059-041

19 27 25 16

Figure 41. AD8042 Differential Driver for the AD9220 12-Bit, 10 MSPS ADC

Rev. E | Page 14 of 16
 AD8042
2kΩ 3kΩ
The circuit was tested with a 1 MHz input signal and clocked
ATT
at 10 MHz. An FFT response of the digital output is shown in 6 2718AF
7 93DJ39
232Ω VOUT
Figure 42. VIN
5
1/2 1 4
AD8042
Pin 5 is biased at 2.5 V by the voltage divider and bypassed.
2kΩ 3kΩ
This biases each output at 2.5 V. VIN is ac-coupled such that 10 5
2
VIN going positive makes VINA go positive and VINB go in 1
the negative direction. The opposite happens for a negative 3
1/2 2 7
going VIN. 0.001µF AD8042

1 912Ω
9 6

0.0027µF
34Ω 2kΩ
2kΩ

2
VERTICAL SCALE (15dB/DIV)

1 249Ω
2kΩ 3 VREC
1/4
2kΩ 2kΩ AD8044

01059-043
0.001µF
3
9 2 7 6
5
8 4 Figure 43. HDSL Line Driver

LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8042 requires
01059-042

careful attention to board layout and component selection.

HARMONICS (dBc) Proper RF design techniques and low-pass parasitic component
FUND FRQ 1000977 THD –82.00 2ND –88.34 6TH –99.47
SMPL FRQ 10000000 SNR 71.13 3RD –86.74 7TH –91.16 selection are necessary.
SINAD 70.79 4TH –99.26 8TH –97.25
SFDR –86.74 5TH –90.67 9TH –91.61

Figure 42. FFT of the AD9220 Output When Driven by the AD8042
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
HDSL Line Driver impedance path. The ground plane should be removed from
High bit rate digital subscriber line (HDSL) is a popular means the area near the input pins to reduce the stray capacitance.
of providing data communication at DS1 rates (1.544 Mbps) Chip capacitors should be used for the supply bypassing. One
over moderate distances via conventional telephone twisted pair end should be connected to the ground plane and the other
wires. In these systems, the transceiver at the customer’s end is within ⅛-inch of each power pin. An additional large (0.47 μF
powered sometimes via the twisted pair from a power source at to 10 μF) tantalum electrolytic capacitor should be connected in
the central office. Sometimes, it is required to raise the dc voltage parallel, but not necessarily so close to supply current, for fast,
of the power source to compensate for IR drops in long lines or large signal changes at the output.
lines with narrow gauge wires.
The feedback resistor should be located close to the inverting
Because of the IR drop, it is highly desirable to keep the power input pin to keep the stray capacitance at this node to a
consumption of the customer’s transceiver as low as possible. minimum. Capacitance variations of less than 1 pF at the
One means to realize significant power savings is to run inverting input significantly affect high speed performance.
the transceiver from a ±5 V supply instead of the more
conventional ±12 V. Stripline design techniques should be used for long signal
traces (greater than approximately one inch). These should be
The high output swing and current drive capability of the designed with a characteristic impedance of 50 Ω or 75 Ω and
AD8042 make it ideally suited to this application. Figure 43 be properly terminated at each end.
shows a circuit for the analog portion of an HDSL transceiver
using the AD8042 as the line driver.

Rev. E | Page 15 of 16
AD8042

OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)

8 5 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
4
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC 0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)

0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

070606-A
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 44. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body (N-8)—Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4

1.27 (0.0500) 0.50 (0.0196)

BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-A A

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
012407-A

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 45. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)—Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8042AN –40°C to +85°C 8-Lead PDIP N-8
AD8042AR –40°C to +85°C 8-Lead SOIC_N R-8
AD8042AR-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Reel R-8
AD8042AR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Reel R-8
AD8042ARZ 1 –40°C to +85°C 8-Lead SOIC_N R-8
AD8042ARZ-REEL1 –40°C to +85°C 8-Lead SOIC_N, 13" Reel R-8
AD8042ARZ-REEL71 –40°C to +85°C 8-Lead SOIC_N, 7" Reel R-8
AD8042ACHIPS DIE
1
Z = RoHS Compliant Part.

©2007 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D01059-0-12/07(E)

Rev. E | Page 16 of 16