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D D

Inventec Corporation
R&D Division

C C

Board name : Mother Board Schematic


Project : S118D (Frankfrut)
Version : A03 (Pre MP)

B
Initial Date : SEP 24 , 2007 B

A A

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
C C
D-CS- 1310A22028-0-ALG
Date: Thursday, July 10, 2008 Sheet 1 of 45
5 4 3 2 1
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1. Schematic Page Description :


Santa Rosa Schematic Ver : 0.1
1. Title 22. ICH9M PCI/PCIE/DMI/USB(2/4) 43. GPU_Core Power
D D

2. Schematic Page DESCR 23. ICH9M GPIO(3/4) 44. Dual Battery


3. Block Diagram 24. ICH9M Power/GND(4/4) 45. POWER ON LATCH
4. Annotations 25. LCD CNN & CAMERA
5. Schematic Modify 26. CRT & SWITCH
6. Timing Diagram 27. BAY/SATA/G_PAD/TPM/FP
7. DDRII Layout Guideline 28. OZ77CR6 (SMART CARD)
8. Penryn Processor(1/2) 29. GL827 (CARD-READER)
9. Penryn Processor(2/2) 30. LAN (82567LM)
10. CPU Core Power 31. Audio Codec ALC262/AMP
11. CPU Thermal 32. Audio Jack
12. Cantiga Host(1/6) 33. DVI LevelShift
13. Cantiga DMI/Graph(2/6) 34. Super I/O
C
14. Cantiga DDRII(3/6) 35. USB/eSATA/Blue/3D C

15. Cantiga Power(4/6) 36. 3G/WLAN(MINI CARD)


16. Cantiga Power(5/6) 37. Docking CNN/LCM/MDC
17. Cantiga Ground(6/6) 38. KBC ITE8512F
18. Clock Generator 39. Adaptor in/Charge
19. DDR3 SDRAM SO-DIMM0 40. 5VLA/5VA/3VA
20. DDR3 SDRAM SO-DIMM1 41. 3VS/5VS/1.5V
21. ICH9M CPU/IDE/SATA(1/4) 42. 1.05VM/VGFX/1.8V
43. 1.5VS/3VM
44. Dual Battery
45. Power on latch

B B

A A

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
C AX1
Schematic Page DESCR
Date: Wednesday, July 02, 2008 Sheet 2 of 45
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

3. Block Diagram :
PLL
CPU ICS9LPRS397AGLF
Thermal Thermal uFCPGA 478pin QFN72P
FAN P.18
D EMC1402 Penryn D
P.11
P.11 P.8-9 266MHz+/- x2 (CPU, NB)
100MHz+/- x7
FSB 1.05V 48MHz x2 (ICH, SC)
667/800/1066MHz 33MHz x6
LCD LVDS DDR3 1.5V 14MHz x2 (ICH, SIO)
800/1066MHz

SODIMM0

SODIMM1
P.25 MCH 35mmx35mm 27MHz/96MHz+/-x1
9XXGM/GML
CRT RGB_CRT RGB FCBGA 1329pin DDR3 1.5V
P.26 Cantiga GM 800/1066MHz

DOCKING DVI PI3VDP411 P.12-17 P.20


P.37 Level Shift
P.19
P.33 DMI x4 RJ45
P.30
GbE SIM Slot
31mmx31mm Gigabit LAN
HDD ICH Connect Interface 82567LM/LF P.36
SATA 150
mBGA 676pin
C
P.30 MiniCard #1 C
P.27
UMTS
ICH9M/E MiniCard #2
PCI-Express x1 2.5GHz-----Port 4
ODD bay Port#4
P.36 WLAN
SATA 150
PCI-Express x1 2.5GHz-----Port 3
P.27 Port#3 P.36
PCI-Express x1 2.5GHz-----Port 2 Docking
ESATA
eSATA SATA 150 P.37
PCI-Express x1 2.5GHz-----Port 1 MiniCard #1 Port#2
P.35 NEW CARD

P.27
HDA 24MHz Port#1
USB0 USB1 USB2 USB3 AMP
Out
SPK
Port eSATA Port Smart Card IntMic Audio P.31
IN P.31
MDC1.5 RJ11 Stereo Codec Out
P.35 P.35 P.35 P.28 P.32 Docking
P.37 P.37 IN
ALC262
IN
P.37
Analog In
EHCI#1 Out Analog Out
P.32 P.31
Support P.32
B S0~S3 state B
USB 2.0/1.1 LPC 3.3V 33MHz

PMU&KBC Super I/O 80Port


ITE8512F IT8305E
USB4 USB5 USB6 USB7 P.38 P.34 P.36
Finger PS/2
3G DOCKING Card Reader Printer
P.36 P.37 P.29 P.27 Docking
P.37

KB Docking TPM
P.38 P.27
P.37
SPI

Glide Pad
P.27
USB10 USB8 USB9 USB11
P.21-24
NEW CARD WLAN BlueTooth Camera Flash
P.27 P.36 P.35 P.25 ROM
A P.38 A

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
C AX1
Block Diagram
Date: Wednesday, July 02, 2008 Sheet 3 of 45
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

4. Net name Description : Power Rail


VCC_CORE
Destination
Penryn HFM:
Voltage
1.3319V~1.4375V~1.4591V
S0 Current
36A
LFM: 0.9221V~0.9625V~0.9739V
Voltage Rails 1.05VS Penryn: AGTL+ termination 1V~1.05V~1.10V 4.5A
DCIN Primary DC system power supply Cantiga GM: Core 0.997V~1.05V~1.102V 8.7A
5VLA 5.0V always on power rail by DCIN Cantiga GM: PCIE 0.9975V~1.05V~1.1025V 1.78A
3VLA 3.3V always on power rail by DCIN Cantiga GM:Core+IMEL+HSIO 0.9975V~1.05V~1.1025V 2.898A
D EC_3VLA 3.3V always on power rail by 5VAUXON Cantiga GM:VCC_GMCH 0.997V~1.05V~1.102V 10.154A D

5VA 5.0V always on power rail by LATCH_ON Cantiga GM:VCCA_SM_CK and NCTF 0.997V~1.05V~1.102V 37.95mA
3VA 3.3V always on power rail by LATCH_ON Cantiga GM:VCC_DMI 0.997V~1.05V~1.102V 456mA
5VS 5.0V switched power rail by SUSB# Cantiga GM:VCCA_SM 0.997V~1.05V~1.102V 747.5mA
3VS 3.3V switched power rail by SUSB# Cantiga GM:VTT 0.997V~1.05V~1.102V 852mA
1.8VS 1.8V switched power rail by SUSC# ICH9M:VCC1_05 0.997V~1.05V~1.102V 1.634A
ICH9M:DMI 0.997V~1.05V~1.102V 48mA
VCC_CORE Core Voltage for CPU ICH9M:CPU_IO 0.997V~1.05V~1.102V 2mA
1.05VS 1.05V power rail for AGTL+ termination/Core for GMCH by SUSB# 1.5VS Penryn PLL 1.425V~1.5V~1.575V 130mA
1.5VS 1.5V power rail for CPU PLL/DMI;PCIE;DDR3 DLLs for GMCH/Core;PCIE Cantiga GM: QDAC 1.425V~1.5V~1.575V 0.5mA
for ICH9M by SUSB# Cantiga GM: LVDS 1.71V~1.8V~1.89V 60.31mA
VGFX_CORE Core Voltage for GMCH Cantiga GM: TVDAC 1.425V~1.5V~1.575V 35mA
Cantiga GM: Various PLLS analog supply 1.425V~1.5V~1.575V 485mA
1.5V 1.5V power rail for DDR3 by SUSC# Cantiga GM: VCC_SM_CK 1.425V~1.5V~1.575V 149.5mA
PWR_DIMM_VTT 0.75V DDR3 Termination Voltage by SUSB# Cantiga GM: VCC_SM 1.425V~1.5V~1.575V 3.1625A
ICH9M:PCIE_ICH 1.425V~1.5V~1.575V 646mA
Part Naming Conventions ICH9M:SATA_ICH 1.425V~1.5V~1.575V 1.342A
ICH9M:VCC_GLAN 1.425V~1.5V~1.575V 80mA
C = Capacitor Mini Card:
CN = Connector Express Card: 1.425V~1.5V~1.575V 650mA
C D = Diode 1.5V Cantiga GM: DDRIII System Memory 1.425V~1.5V~1.575V 3.1A(800M) 4.1A(1067M)
C

F = Fuse 0.75VDDT_DDRIII: DDRIII Terminator: 0.7125V~0.75V~0.7875V 1.0A


L = Inductor 3VS Cantiga GM: HV CMOS 3.135V~3.3V~3.465V 105.3mA
Q = Transistor Cantiga GM: VCCS_TVDAC 3.135V~3.3V~3.465V 78mA
R = Resistor ICH9M:VCC3_3 3.135V~3.3V~3.465V 308mA
RP = Resistor Pack ICH9M:VCCGLAN3_3 3.135V~3.3V~3.465V 1mA
U = Arbitrary Logic Device Thermal Sensor: 3.0V~3.3V~3.6V 5mA
Y = Crystal and Osc Mini Card: UMTS
Express Card: 3.135V~3.3V~3.465V 1.3A
Net Name Suffix CLK Generator: ICS9LPRS397BKLFT 3.135V~3.3V~3.465V 500mA
Mini Card: WirelessLan
# = Active Low signal Bluetooth:
3.0V~3.3V~3.6V

5. Board Stack up Description Super I/O: IT8305E


Azalia Codec: ALC262
Azalia MDC:

PCB Layers 1.8VS DVI 3.0V~3.3V~3.6V 120mA


Layer 1 Component Side, Microstrip signal Layer 3VA ICH9M: RTC 2V~3.3V~3.465V 6uA
B Layer 2 Ground Plane ICH9M:VCCSUS3_3 3.135V~3.3V~3.465V 212mA B

ICH9M:VCCCL3_3 3.135V~3.3V~3.465V 73mA


Layer 3 Stripline Layer ICH9M:VCCLAN3_3 3.135V~3.3V~3.465V 78mA
Layer 4 Stripline Layer LCD: 3.0V~3.3V~3.6V 2A
Lan:82567LM 1.0V and 1.8V Each 1A
Layer 5 Power Plane Azalia MDC:
Layer 6 Ground Plane Flash ROM: BIOS 3.0V~3.3V~3.6V

Layer 7 Stripline Layer 5VS Cardreader: GL827 3.0V~3.3V~3.6V


Layer 8 Stripline Layer Azalia Codec: ALC262 3.0V~3.3V~3.6V
HDD: SATA 4.75V~5.0V~5.25V Max: 1.5A ; R/W: 460mA ; STDBY: 70mA
Layer 9 Ground Plane ODD: SATA 4.75V~5.0V~5.25V Max: 1.5A ; R/W: 900mA ; STDBY: 45mA
Layer 10 Solder Side,Microstrip signal Layer Audio AMP: G1432
Inverter:
WebCam 4.75V~5.0V~5.25V 1A
5VA USB: x 2 ports 5VA 1.5A
Differential Impedance for Microstrip(5-mils) Differential Impedance for Stripline(4-mils)
USB and ESATA 5VA 2A
Host Clock 95 ohm +/- 20% 100 ohm +/- 20%
PCI-E Clock 95 ohm +/- 20% 100 ohm +/- 20% 5VLA Control Power
DDR2 CLK 70 ohm +/- 20% 70 ohm +/- 20%
A DDR2 Strobe 85 ohm +/- 20% 90 ohm +/- 20% 3VLA EC: ITE8512E 3.0V~3.3V~3.6V 300mA A

DMI Bus 95 ohm +/- 20% 100 ohm +/- 20%


PCIE Bus 95 ohm +/- 20% 100 ohm +/- 20%
SDVO
SATA
95 ohm +/- 20%
95 ohm +/- 20%
100 ohm +/- 20%
100 ohm +/- 20%
Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
USB 90 ohm +/- 20% 95 ohm +/- 20%
TEL:+886-2-2881-0721
LVDS 100 ohm +/- 20% Title
Lan 95 ohm +/- 20% 100 ohm +/- 20%
Size
S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
C AX1
ANNOTATIONS
Date: Wednesday, July 02, 2008 Sheet 4 of 45
8 7 6 5 4 3 2 1
5 4 3 2 1

6.Schematic modify Item and History :


iAMT/noniAMT Matrix

iAMT and none iAMT Difference


D
MB_ID1 MB_ID0 ICH9M --- U17 LAN PHY --- U8 D43
Frankfurt A01 change list ---- MB D

R539 -- 10K R519 -- 10K 6019B0462002 6019B0483701


For iAMT NH82801IEM 6011A0026803
R639-- NU R654 -- NU WG82567LM
1. Change U9(hall sensor) from 6019B0373901 to 6019B0491401
For none R519 -- 10K R519 -- NU 6019B0462001 6019B0528501
iAMT R639 -- NU R654 -- 10K NH82801IBM WG82567LF
NU 2. Change CN20(DC-JACK) from 6026B0057802 to 6026B0057803
3. Change CN16(BT-CN) from 6012A0136201 to 6012B0069915
iAMT and none iAMT Difference
4. Change R524 from 6013A008830S to 6013A008830P
MB_ID1 MB_ID0
5. ADD R751--60130B4730ZT
For iAMT 1 1 6. Change L12,L21 from6014B0090001 to 6014B0024003
For none
7. Change C159 from 6010B0009402 to 6010B0008501
1 0
iAMT
8. Change Q17 from 6015B0031301 to 6015B0071201
9. Change Q16 from 6015B0012901 to 6015B0071101
10.ADD R752,R753--60130B0000ZT
11.ADD C691--6010A0055601
Frankfurt AX1 change list ---- MB 12.ADD C692,C693--6010B0000501
13.Change BATT1 from 6017B0163601 to 6027B0048901
C 1. Change U45 from 6019B0383501 to 6019B0461901 C

2. Change R118 from 60130B4720ZT to 60130B4730ZT 14.ADD Q42--6015B0031901


3. Change R7, R8, R9 from60130B2210ZT to 6013A0050301 15.ADD R349--60130B20100T
4. Del R75, R76, R77 --6013A0052101 16.Del D43--6011A0026803
5. ADD C611, C612, C613--6010B0050601 17.Change R490 from 6013A0017701 to 6013A0016001
18.Change C157,C160,C179,C143,C130,C161,C152,C128,C140,C181from 6010B0009801 to 6010B0044901

Frankfurt AX2 change list ---- MB

1. ADD R749--60130B0000ZT
2. ADD D43--6011A0026803
3. For GFX VID support

B B

A A

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
C AX1
Schematic Modify
Date: Wednesday, July 02, 2008 Sheet 5 of 45
5 4 3 2 1
5 4 3 2 1

SYSTEM POWER ON/OFF SEQUENCE


Power on/off sequence AC insert(First) Battery only Power on/off sequence
Power on sequence Power off sequence Power on sequence Power off sequence
SW OFF: RTCVCC SW OFF: RTCVCC

D 5VLA,3VLA 5VLA,3VLA D

5VAUXON 5VAUXON

EC_3VLA EC_3VLA

SW ON: PWR_SWIN# SW ON: PWR_SWIN#

LATCH_ON LATCH_ON

3VA,5VA 3VA,5VA

RSMRST# /!MRST#

PWR_BTN# PWR_BTN#

SUSB# SUSB#

SUSC# SUSC#

1.5V,1.8V 1.5V,1.8V

5VS,3VS 5VS,3VS

1.5VS,1.05VS 1.5VS,1.05VS

C
0.75VS_DIMM 0.75VS_DIMM C

+VCCP 99ms +VCCP 99ms

VCCP_PWRGD VCCP_PWRGD

VR_ON VR_ON

VCORE_GD VCORE_GD

CLK_PWROK CLK_PWROK

ICH_PWROK ICH_PWROK

PLT_RST# PLT_RST#

Power on/off sequence AC insert(S4) Suspend resume sequence(S3)


Suspend sequence Resume sequence
Power on sequence Power off sequence
RTCVCC RTCVCC

3VLA,5VLA 5VLA,3VLA

5VAUXON 5VAUXON
B B
EC_3VLA EC_3VLA

PWR_SWIN# PWR_SWIN#

LATCH_ON LATCH_ON

3VA,5VA 3VA,5VA

RSMRST# RSMRST#

PWR_BTN# PWR_BTN#

SUSB# SUSB#

SUSC# SUSC#

1.5V,1.8V 1.5V,1.8V

5VS,3VS 5VS,3VS

1.5VS,1.05VS 1.5VS,1.05VS

0.75VS_DIMM 0.75VS_DIMM

+VCCP 99ms +VCCP 99ms

A A
VCCP_PWRGD VCCP_PWRGD

VR_ON VR_ON

VCORE_GD VCORE_GD Inventec Corporation


66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
CLK_PWROK CLK_PWROK
TEL:+886-2-2881-0721

ICH_PWROK ICH_PWROK Title

Size
S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
PLT_RST# PLT_RST#
Custom
Timing Diagram AX1

Date: Wednesday, July 02, 2008 Sheet 6 of 45


5 4 3 2 1
5 4 3 2 1

8. Layout Guideline :
Crestline DDRII Layout Guidelines Control group : SM_CKE[3..0],SM_CS#[3..0],SM_ODT[3..0] Data group : SA_DQ[63..0],SB_DQ[63..0],SA_DM[7..0],SB_DM[7..0]
DDRII Signal Groups
GMCH 4/4/12 7/4/16 8/5/15 GMCH 4/4 4/6
Escape Escape
Group Signal Name Length Matching and Length Formulas
P1 L0 L1 L2 L3 Vtt P1 L0 L1 L2
D Data M_A_DQ[63..0]/M_B_DQ[63..0] Signal Group Minimum Length Maximum Length Breakout SL/MS Breakout D
M_A_DM[7..0]/M_B_DM[7..0] MS SL SL/MS S1 MS SL SL S1 MS
M_A_DQS[7..0]/M_A_DQS#[7..0] Control-to-Clock Clock - 1.0" Clock - 0.0" MS
M_B_DQS[7..0]/M_B_DQS#[7..0]
Address M_A_A[13..0]/M_B_A[13..0]
Command-to-Clock Clock - 1.0" Clock + 1.0" SO-DIMM SO-DIMM
M_A_BS[2..0]/M_B_BS[2..0] Strobe-to-Clock Clock - 0.5" Clock + 1.0"
M_A_RAS#/M_B_RAS# Topology Point-to-Point with parallel termination Topology Point-to-Point
M_A_CAS#/M_B_CAS# Data-to-Strobe Strobe - 220mils Strobe - 180mils
M_A_WE#/M_B_WE# Reference Plane Ground Reference Plane Ground
Control M_CS#[3..0] Characteristic Trace Impedance 55 +/- 15% Characteristic Trace Impedance 55 +/- 15%
M_CKE[3..0]
M_ODT[3..0] Nominal Trace Width Inner Layer : 4 mils Nominal Trace Width Inner Layer : 4 mils
Outer Layer : 5 mils Outer Layer : 5 mils
Clock M_CLK_DDR[3..0]
M_CLK_DDR#[3..0] Minimum CTRL Trace Spacing Inner Layer : 8 mils Minimum DQ Bus Trace Spacing Inner Layer : 6 mils
Outer Layer : 10 mils Outer Layer : 8 mils
FeedBack SA_RCVEN#/SB_RCVEN#
Minimum Spacing to Other DDR2 Inner Layer : 12 mils Minimum Serpentine Spacing Same as DQ-to-DQ routing
Outer Layer : 15 mils
Minimum Spacing to Other DDR2 Inner Layer : 12 mils
Minimum Isolation Spacing to non-DDR2 25 mils Outer Layer : 15 mils
Package Length P1 750 mils +/- 200 mils Minimum Isolation Spacing to non-DDR2 25 mils
Trace Length Limit - L0 Max = 50 mils (Escape) Package Length P1 750 mils +/- 350 mils

CLK group : M_CLK_DDR[3..0],M_CLK_DDR#[3..0] Trace Length Limit - L1 Max = 500 mils (Breakout) Trace Length Limit - L0 Max = 50 mils (Escape)
Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin) Trace Length Limit - L1 Max = 500 mils (Breakout)
SO-DIMM
GMCH Escape
4/4/12 7/4/16 8/5/15 MB Length Limits - L0 + L1 + L2 + S1 - Min = 500 mils
Max = 4500 mils
Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin)
From GMCH ball to SO-DIMM pad MB Length Limits - L0 + L1 + L2 + S1 - Min = 500 mils
P1 L0 L1 L2 S1 Total Length - P1 + L0 + L1 + L2 + S1 - Max = 5000 mils From GMCH ball to SO-DIMM pad Max = 4500 mils
From GMCH die to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1 - Max = 5000 mils
C
P1 L0 L1 L2 S1 Trace Length L3 Max = 1500 mils From GMCH die to SO-DIMM pad C

Parallel Termination Resistor 56 +/- 5% Trace Length L3 Max = 1500 mils


Breakout Breakin
MS SL SL MS Maximim Via Count 3 Maximim Via Count 2
Topology Differential Pair Point-to-Point CTRL to SCK/SCK# Length Matching (CLK-1.0") </= CTRL </= (CLK-0.0") DQ/DM to DQS Length Matching Match DQ/DM to [SDQS - 200mils]
Reference Plane Ground (Total Length including package) (Total Length including +/- 20mils, per byte lane
Breakout Exceptions (Reduce geometries Inner Layer : 4 mils spacing allowed package)
Breakout Exceptions (Reduce geometries Inner Layer : 4 mils spacing allowed
Single Ended Trace Impedance 42 +/- 15% for GMCH break-out region) Outer Layer : 5 mils spacing allowed for GMCH break-out region) Outer Layer : 5 mils spacing allowed
Max. breakout length is 500 mils Max. breakout length is 500 mils
Differential Mode Impedance 70 +/- 20%
Minimum Serpentine Spacing Inner Layer : 12 mils
Outer Layer : 15 mils
Package Length Range - P1 350 mils ~ 625 mils Command group : Data Strobe group : SA_DQS[7..0],SA_DQS[7..0]#,SB_DQS[7..0],SB_DQS[7..0]#
Min. Serpentine Spacing 25 mils SA_MA[13..0],SB_MA[13..0],SA_BS[2..0],SB_BS[2..0],SA_RAS#,
SO-DIMM
Trace Length Limit - L0 (MS) Nominal Trace Width : 5mils, 4mils SB_RAS#,SA_CAS#,SB_CAS#,SA_WE#,SB_WE# GMCH 4/4/8 4/4/12 5/5/10
Escape
Length Limit: Max = 50 mils (Escape)
P1 L0 L1 L2 S1
Min. Trace Spacing : 5mils, 4mils GMCH Escape
4/4 4/6,5/10 4/6,5/10
Trace Length Limit - L1 (SL) Length Limit: Max = 700 mils P1 L0 L1 L2 S1
(Breakout length segment) Nominal Trace Width : 4mils
P1 L0 L1 L2 L3 Vtt
Breakout SL/MS Breakout Breakin
Min. Trace Spacng (pair) : 4mils MS SL SL/MS S1 SL SL MS
MS
Min. Trace Spacng (Other) : 12 mils Topology Differential Pair Point-to-Point
SO-DIMM
Reference Plane Ground
Topology Point-to-Point with parallel termination Single Ended Trace Impedance 55 +/- 15%
B B
Reference Plane Ground Differential Mode Impedance 85 +/- 20%
Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin)
Characteristic Trace Impedance 55 +/- 15% Nominal Trace Width Inner Layer : 4 mils
MB Length Limits - L0 + L1 + L2 + S1 Min = 500 mils Outer Layer : 5 mils
Max = 4000 mils Nominal Trace Width Inner Layer : 4 mils
Outer Layer : 5 mils Nominal DQS to DQS# Spacing Inner Layer : 4 mils
Total Length - P1 + L0 + L1 + L2 + S1 Max = 4500 mils (edge to edge) Outer Layer : 5 mils
Minimum CMD Bus Trace Spacing Inner Layer : 6 mils
Total Length for Channel A : X0 Outer Layer : 10 mils Minimum DQS to DQ Spacing Inner Layer : 12 mils
Total Length for Channel B : X1 Outer Layer : 15 mils
Minimum Spacing to Other DDR2 Inner Layer : 12 mils
Maximim Via Count 2 (Per side) Outer Layer : 15 mils Minimum Serpentine Spacing Inner Layer : 8 mils
Outer Layer : 10 mils
SCK to SCK# Length Matching Match total length to within 5 mils Minimum Isolation Spacing to non-DDR2 25 mils
Minimum Spacing to Other DDR2 Inner Layer : 12 mils
Clock to Clock Length Match Match Channel A clocks to X0 +/- 20mils Package Length P1 750 mils +/- 350 mils Outer Layer : 15 mils
(Total Length) Match Channel A clocks to X1 +/- 20mils
Trace Length Limit - L0 Max = 50 mils (Escape) Minimum Isolation Spacing to non-DDR2 25 mils
Breakout Exceptions (Reduce geometries Inner Layer : 4/12 mils to other DDR2
for GMCH break-out region) Outer Layer : 5/15 mils to other DDR2 Trace Length Limit - L1 Max = 500 mils (Breakout) Package Length Range - P1 750 mils +/- 350 mils
Max. breakout length is 500 mils Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin) Trace Length Limit - L0 Max = 50 mils (Escape)
Breakin Exceptions (Reduce geometries CK to CK# spacing rule waived at MB Length Limits - L0 + L1 + L2 + S1 - Min = 500 mils Trace Length Limit - L1 Max = 500 mils (Breakout)
for SO-DIMM break-in region) connector spacing of 15 mils to From GMCH ball to SO-DIMM pad Max = 4500 mils
Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin)
other DDR2 Total Length - P1 + L0 + L1 + L2 + S1 - Max = 5000 mils
From GMCH die to SO-DIMM pad MB Length Limits - L0 + L1 + L2 + S1 - Min = 500 mils
Max. breakin length is 200 mils From GMCH ball to SO-DIMM pad Max = 4500 mils
Trace Length L3 Max = 1500 mils
Feedback group : Parallel Termination Resistor 56 +/- 5%
Total Length - P1 + L0 + L1 + L2 + S1 - Max = 5000 mils
From GMCH die to SO-DIMM pad
SA_RCVENIN#],SA_RCVENOUT#,SB_RCVENIN#],SB_RCVENOUT#
Maximim Via Count 3 Maximim Via Count 2 (Per side)
These signals are routed internally on the GMCH package and don't require any CTRL to SCK/SCK# Length Matching (CLK-1.0") </= CMD </= (CLK+1.0") DQS to DQS# Length Matching Match total length to within 5 mils
routing on the MB. As a result, can be left as NC. (Total Length including package) Clock to Clock Length Match (CLK-0.5") </= DQS </= (CLK+1.0")
A Breakout Exceptions (Reduce geometries Inner Layer : 4 mils spacing allowed (Total Length include package) A

for GMCH break-out region) Outer Layer : 5 mils spacing allowed


Max. breakout length is 500 mils Breakout Exceptions (Reduce geometries Inner Layer : 8 mils to other DDR2
for GMCH break-out region) Outer Layer : 10 mils to other DDR2
Max. breakout length is 500 mils
Breakin Exceptions (Reduce geometries
for SO-DIMM break-in region)
DQS to DQS# spacing rule
waived at connector spacing of Inventec Corporation
10 mils to other DDR2 66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan

Max. breakin length is 200 mils TEL:+886-2-2881-0721


Title

Size
S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
C AX1
DDRII Layout Guideline
Date: Wednesday, July 02, 2008 Sheet 7 of 45
5 4 3 2 1
A B C D E

CN25A Topology : FERR#


H_A#3 J4 H1
H_A#4 A[3]# ADS# H_ADS# 12
L5
A[4]# BNR#
E2 H_BNR# 12 VCCP L1 L2 Rtt Transmission Line

ADDR GROUP 0
H_A#5 L4 G5 CPU ICH7m
A[5]# BPRI# H_BPRI# 12
H_A#6 K5 0.5" - 12" 0" - 3.0" 56 +/-5% Micro-strip
H_A#7 A[6]#
M3
A[7]# DEFER#
H5 H_DEFER# 12 Rtt
H_A#8 N2 F21 L1 L2 0.5" - 12" 0" - 3.0" 56 +/-5% Strip-line
H_A#9 A[8]# DRDY# H_DRDY# 12
J1 E1 H_DBSY# 12
H_A#10 A[9]# DBSY#
N3
H_A#11 A[10]#
P5 F1 H_BREQ#0 12
H_A#12 A[11]# BR0#
P2
A[12]# VCCP VCCP
H_A#13 L2 D20 H_IERR# R37 56-5%-1/16W-0402

CONTROL
H_A#14 A[13]# IERR# 1.05VS 9,12,13,16,18,21,24,38,42
P4
A[14]# INIT#
B3 H_INIT# 21 CPU IMVP6 L1 L2 L3 L4 Rtt Transmission Line
H_A#15 P1 Rtt Rtt
H_A#[35..3] H_A#16 A[15]#
12 H_A#[35..3] R1
A[16]# LOCK#
H4 H_LOCK# 12 0.5" - 6.5" 0.5" - 6.5" 0" - 3.0" 0" - 3.0" 70 +/-5% Micro-strip
4
12 H_ADSTB#0 M1 4
ADSTB[0]# R457 SHORT-0402-5MIL
RESET#
C1 H_CPURST# 12 L4 L2+L1 L3 0.5" - 6.5" 0.5" - 6.5" 0" - 3.0" 0" - 3.0" 70 +/-5% Strip-line
H_REQ#0 K3 F3
REQ[0]# RS[0]# H_RS#0 12
H_REQ#1 H2 F4
H_REQ#2 REQ[1]# RS[1]# H_RS#1 12
K2 G3 H_RS#2 12
H_REQ#3 REQ[2]# RS[2]#
J3 G2 H_TRDY# 12
H_REQ#[4..0] H_REQ#4 REQ[3]# TRDY#
12 H_REQ#[4..0] L1
REQ[4]# Topology : PWRGOOD Topology : CPUSLP#
G6 H_HIT# 12
H_A#17 HIT#
Y2 E4 H_HITM# 12
H_A#18 A[17]# HITM#
U5
A[18]# CPU ICH7m L1 Transmission Line CPU GMCH L1 Transmission Line
H_A#19 R3 AD4
A[19]# BPM[0]#

ADDR GROUP 1
H_A#20 W6 AD3 0.5" - 12" Micro-strip 0.5" - 12" Micro-strip
H_A#21 A[20]# BPM[1]#
U4
A[21]# BPM[2]#
AD1 L1 L1
H_A#22 Y5 AC4 0.5" - 12" Strip-line 0.5" - 12" Strip-line

XDP/ITP SIGNALS
H_A#23 A[22]# BPM[3]#
U1 AC2
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 AC1
H_A#25 A[24]# PREQ# XDP_TCK
T5
A[25]# TCK
AC5 Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# , STPCLK# Topology : RESET#
H_A#26 T3 AA6 XDP_TDI
H_A#27 A[26]# TDI XDP_TDO
W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5
A[28]# TMS
AB5 CPU ICH7m L1 Transmission Line GMCH CPU L1 Transmission Line
H_A#29 Y4 AB6 XDP_TRST# 1.05VS 9,12,13,16,18,21,24,38,42
H_A#30 A[29]# TRST# XDP_DBRESET#
U2
A[30]# DBR#
C20 0.5" - 12" Micro-strip 1" - 6" Micro-strip
H_A#31 V4 R35 L1 L1
H_A#32 A[31]# 68-1%-1/16W-0402
W3
A[32]# 0.5" - 12" Strip-line 1" - 6" Strip-line
H_A#33 AA4 THERMAL
H_A#34 A[33]#
AB2
H_A#[35..3] H_A#35 A[34]#
12 H_A#[35..3] AA3 D21 H_PROCHOT# 10
A[35]# PROCHOT#
12 H_ADSTB#1 V1
ADSTB[1]# THERMDA
A24 H_THERMDA 11 Topology : THERMTRIP#
B25 H_THERMDC 11
THERMDC
21 H_A20M# A6
A20M# VCCP L1 L2 L1+L3 L3 L4 Rss Rtt Transmission Line
21 H_FERR# A5
FERR# THERMTRIP#
C7 PM_THRMTRIP# 13,21 GMCH CPU ICH8m
21 H_IGNNE# C4
IGNNE# 1" - 12" 1" - 6" 1" - 12" 0" - 3.0" 0" - 3.0" 24 +/-5% 56 +/-5% Micro-strip
L3 Rtt
21 H_STPCLK# D5
STPCLK# L2 L1 Rtt L4 1" - 12" 1" - 6" 1" - 12" 0" - 3.0" 0" - 3.0" 24 +/-5% 56 +/-5% Strip-line
21 H_INTR C6 H CLK
LINT0

ICH
21 H_NMI B4 A22 CLK_CPU_BCLK 18
LINT1 BCLK[0]
21 H_SMI# A3 A21 CLK_CPU_BCLK# 18
SMI# BCLK[1]
M4
3 RSVD[01] 3
N5
T2
RSVD[02] Should be connect to ICH8 and Calistoga without T-ing(no stub)
RSVD[03]
V3
RSVD[04]
No stub on H_STPCLK test point B2
RSVD[05] XDP P/U & P/D
RESERVED
D2
RSVD[06]
D22
RSVD[07]
D3
RSVD[08] XDP_DBRESET# R40 1K-5%-1/16W-0402
F6 3VS 10,11,13,16,18,21,22,23,24,25,26,27,28,31,32,33,34,35,36,38,41,42
RSVD[09]
XDP_TDO R464 54.9-1%-1/16W-0402_NU
1.05VS 9,12,13,16,18,21,24,38,42
XDP_TMS R463 54.9-1%-1/16W-0402
XDP_TDI R468 54.9-1%-1/16W-0402
SCKT INTEL CPU PZ4782A-274M-41 FCPGA 478P FOXCONN for Penryn XDP_BPM#5 R466 54.9-1%-1/16W-0402
6026B0056801
XDP_TRST# R50 54.9-1%-1/16W-0402
Rout to TP via and place gnd via w/in 100mils XDP_TCK R49 54.9-1%-1/16W-0402 FSB Common Clock Signal Layout Guide :
H_ADS# , H_BNR# , H_BPRI# , H_BR0# , H_DBSY# , H_DEFER# , H_DPWR# , H_DRDY# , H_HIT# , H_HITM# , H_LOCK# ,H_
RS#[2..0] , H_TRDY# , H_CPURST#.

Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)
Strip-line(Int. Layer) W=4 & S=8 mils
A#[32-39], APM#[0-1]:Leave escape routing on for future functionality 1.0 ~ 6.5 inch 55+/-15%
Micro-strip(Ext. Layer) W=5 & S=10 mils

H_D#[63..0] CN25B H_D#[63..0]


12 H_D#[63..0]
H_D#0 E22 Y22 H_D#32
H_D#[63..0] 12 FSB Source Synchronous Data Length Variation and Strobe Matching Requirements :
H_D#1 D[0]# D[32]# H_D#33
H_D#2
F24
D[1]# D[33]#
AB24
H_D#34
Signals Name Signals Matching Strobes associated with the group Strobe-to-Strobe Complement Matching
E26 V24
H_D#3 D[2]# D[34]# H_D#35
G22
D[3]# D[35]#
V26 H_D#[15..0] , H_DINV#0 +/- 100 mils H_DSTBP#0, H_DSTBN#0 +/- 25 mils
DATA GRP 0

H_D#4 F23 V23 H_D#36


H_D#5 D[4]# D[36]# H_D#37
G25
D[5]# D[37]#
T22 H_D#[31..16] , H_DINV#1 +/- 100 mils H_DSTBP#1, H_DSTBN#1 +/- 25 mils
DATA GRP 2

H_D#6 E25 U25 H_D#38


2
H_D#7 D[6]# D[38]# H_D#39 2
E23
D[7]# D[39]#
U23 H_D#[47..32] , H_DINV#2 +/- 100 mils H_DSTBP#2, H_DSTBN#2 +/- 25 mils
H_D#8 K24 Y25 H_D#40
H_D#9 D[8]# D[40]# H_D#41
G24
D[9]# D[41]#
W22 H_D#[63..48] , H_DINV#3 +/- 100 mils H_DSTBP#3, H_DSTBN#3 +/- 25 mils
H_D#10 J24 Y23 H_D#42
H_D#11 D[10]# D[42]# H_D#43
J23 W24
H_D#12 D[11]# D[43]# H_D#44
H_D#13
H22
F26
D[12]# D[44]#
W25
AA23 H_D#45 FSB Source Synchronous Data Signal Routing Topology#1 :
H_D#14 D[13]# D[45]# H_D#46
H_D#15
K22
D[14]# D[46]#
AA24
H_D#47
Signal Name Transmission Line Type Total Trace Length Normal Impedance Width & Spacing (mils)
H23 AB25
D[15]# D[47]#
12 H_DSTBN#0 J26
DSTBN[0]# DSTBN[2]#
Y26 H_DSTBN#2 12 Data-to-Data,Strobe-to-strobe Strobe-to-Data
12 H_DSTBP#0 H26 AA26 H_DSTBP#2 12
DSTBP[0]# DSTBP[2]#
12 H_DINV#0 H25
DINV[0]# DINV[2]#
U22 H_DINV#2 12 H_DINV#[3..0] Strip-line 0.5 ~ 5.5 inch 55+/-15% W=4 & S=8 mils N/A
H_D#[63..0] H_D#[63..0]
12 H_D#[63..0] H_D#[63..0] 12 H_DATA#[63..0] Strip-line 0.5 ~ 5.5 inch 55+/-15% W=4 & S=8 mils N/A
H_D#16 N22 AE24 H_D#48
H_D#17 D[16]# D[48]# H_D#49
K25
D[17]# D[49]#
AD24 H_DSTBN#[3..0] Strip-line 0.5 ~ 5.5 inch 55+/-15% W=4 & S=4 mils W=4 & S=12 mils
H_D#18 P26 AA21 H_D#50
H_D#19 D[18]# D[50]# H_D#51
R23
D[19]# D[51]#
AB22 H_DSTBP#[3..0] Strip-line 0.5 ~ 5.5 inch 55+/-15% W=4 & S=4 mils W=4 & S=12 mils
H_D#20 L23 AB21 H_D#52
H_D#21 D[20]# D[52]# H_D#53
DATA GRP 1

M24 AC26
H_D#22 D[21]# D[53]# H_D#54
L22 AD20
D[22]# D[54]#
DATA GRP 3

H_D#23 M23 AE22 H_D#55


H_D#24 D[23]# D[55]# H_D#56
9,12,13,16,18,21,24,38,42 1.05VS H_D#25
P25
P23
D[24]# D[56]#
AF23
AC25 H_D#57
FSB Source Synchronous Address Length Variation and Strobe Matching Requirements :
H_D#26 D[25]# D[57]# H_D#58
H_D#27
P22
D[26]# D[58]#
AE21
H_D#59
Signals Name Signals Matching Strobes associated with the group Strobe to Assoc. Address Signal Matching
T24 AD21
H_D#28 D[27]# D[59]# H_D#60
R24
D[28]# D[60]#
AC22 H_A#[16..3] , H_REQ#[4..0] +/- 200 mils H_ADSTB#0 +/- 200 mils
H_D#29 L25 AD23 H_D#61
H_D#30 D[29]# D[61]# H_D#62
T25
D[30]# D[62]#
AF22 H_A#[35..17] +/- 200 mils H_ADSTB#1 +/- 200 mils
H_D#31 N25 AC23 H_D#63
R418 D[31]# D[63]#
1K-1%-1/16W-0402
12 H_DSTBN#1 L26
DSTBN[1]# DSTBN[3]#
AE25 H_DSTBN#3 12 *** No length matching requirements exist between H_ADSTB#0 and H_ADSTB#1
12 H_DSTBP#1 M26 AF24 H_DSTBP#3 12
DSTBP[1]# DSTBP[3]#
12 H_DINV#1 N24 AC20 H_DINV#3 12
DINV[1]# DINV[3]#
1K-5%-1/16W-0402_NU GTLREF AD26 R26 COMP0 R416 27.4-1%-1/16W-0402 FSB Source Synchronous Address Signal Routing :
R33 H_TEST1 GTLREF COMP[0] COMP1 R417 54.9-1%-1/16W-0402
R29 H_TEST2
C23
TEST1
MISC COMP[1]
U26
COMP2 R54 27.4-1%-1/16W-0402
Signal Name Transmission Line Type Total Trace Length Normal Impedance Width & Spacing (mils)
D25 AA1
R419 1K-5%-1/16W-0402_NU TEST2 COMP[2] COMP3 R55 54.9-1%-1/16W-0402
C24
TEST3 COMP[3]
Y1 H_A#[35..3] Strip-line 0.5 ~ 6.5 inch 55+/-15% W=4 & S=8 mils
1 2K-1%-1/16W-0402 AF26 1
TEST4
AF1
TEST5 DPRSTP#
E5 H_DPRSTP# 10,13,21 H_REQ#[4..0] Strip-line 0.5 ~ 6.5 inch 55+/-15% W=4 & S=8 mils
A26 B5 H_DPSLP# 21
TEST6 DPSLP#
C3
TEST7 DPWR#
D24 H_DPWR# 12 H_ADSTB#[1..0] Strip-line 0.5 ~ 6.5 inch 55+/-15% W=4 & S=12 mils
18 CLK_BSEL0 B22 D6 H_PWRGD 21
BSEL[0] PWRGOOD
18 CLK_BSEL1 B23 D7 H_CPUSLP# 12
BSEL[1] SLP#
Inventec Corporation
18 CLK_BSEL2 C21 AE6 PSI# 10
BSEL[2] PSI#
SCKT INTEL CPU PZ4782A-274M-41 FCPGA 478P FOXCONN for Penryn Comp0,2 connect with Zo=27.4ohm, make trace
6026B0056801
H_PWRGD rise time : length shorter than 0.5" and width is 18mils. 66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan

Zo=55ohm, 0.5" max for GTLREF, Space any other switch Max : 15ns Comp1,3 connect with Zo=55ohm, make trace TEL:+886-2-2881-0721

signals away from GTLREF with a minimum of 25mils. length shorter than 0.5" and width is 5mils Title

Don't allow the GTLREF routing to create splits or Size


S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
discontinuities in the reference planes of the FSB signals C
Penryn Processor(1/2) AX1

Date: Wednesday, July 02, 2008 Sheet 8 of 45


A B C D E
A B C D E

Place these inside socket cavity on L8 Place these inside socket cavity on
(North side secondary) L8 (South side secondary)

10 VCORE_CPU

C75

C71

C60

C56

C46
4 CN25D 4
C45 C55 C59 C70 C74 CN25C
A7 AB20
160mil A4
A8
VSS[001] VSS[082]
P6
P21
VCC[001] VCC[068] VSS[002] VSS[083]
A9 AB7 A11 P24
VCC[002] VCC[069] VSS[003] VSS[084]

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R


A10 AC7 1.05VS 8,12,13,16,18,21,24,38,42 A14 R2
VCC[003] VCC[070] VSS[004] VSS[085]
A12 AC9 A16 R5
VCC[004] VCC[071] VSS[005] VSS[086]
A13 AC12 A19 R22
VCC[005] VCC[072] VSS[006] VSS[087]

C82

C34

C83

C84

C32

C33
A15 AC13 A23 R25
VCC[006] VCC[073] VSS[007] VSS[088]
A17 AC15 + C44 AF2 T1
VCC[007] VCC[074] T220uF 2.5V 35m 20% 3528 VSS[008] VSS[089]
A18 AC17 B6 T4
VCC[008] VCC[075] VSS[009] VSS[090]
A20 AC18 B8 T23
VCC[009] VCC[076] VSS[010] VSS[091]

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R


B7 AD7 B11 T26
VCC[010] VCC[077] VSS[011] VSS[092]
B9 AD9 B13 U3
VCC[011] VCC[078] VSS[012] VSS[093]
B10 AD10 B16 U6
VCC[012] VCC[079] VSS[013] VSS[094]
B12 AD12 B19 U21
VCC[013] VCC[080] VSS[014] VSS[095]
B14 AD14 B21 U24
VCC[014] VCC[081] VSS[015] VSS[096]
B15 AD15 B24 V2
VCC[015] VCC[082] VSS[016] VSS[097]
B17 AD17 C5 V5
VCC[016] VCC[083] VSS[017] VSS[098]
B18 AD18 C8 V22
VCC[017] VCC[084] VSS[018] VSS[099]
B20
VCC[018] VCC[085]
AE9
Place these inside socket cavity on L8 C11
VSS[019] VSS[100]
V25
Place these inside socket cavity on L1 Place these inside socket cavity on L1 C9
VCC[019] VCC[086]
AE10 C14
VSS[020] VSS[101]
W1
C10
VCC[020] VCC[087]
AE12 (North side secondary) C16
VSS[021] VSS[102]
W4
(North side Primary) (South side Primary) C12
VCC[021] VCC[088]
AE13 C19
VSS[022] VSS[103]
W23
C13 AE15 C2 W26
VCC[022] VCC[089] VSS[023] VSS[104]
C15 AE17 C22 Y3
VCC[023] VCC[090] VSS[024] VSS[105]
C17 AE18 C25 Y6
VCC[024] VCC[091] VSS[025] VSS[106]
C476

C472

C464

C459

C451

C452

C460

C465

C473

C477
C18 AE20 D1 Y21
VCC[025] VCC[092] VSS[026] VSS[107]
D9 AF9 D4 Y24
VCC[026] VCC[093] VSS[027] VSS[108]
D10 AF10 D8 AA2
VCC[027] VCC[094] VSS[028] VSS[109]
D12 AF12 D11 AA5
VCC[028] VCC[095] VSS[029] VSS[110]
10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R


D14 AF14 D13 AA8
VCC[029] VCC[096] VSS[030] VSS[111]
D15 AF15 D16 AA11
VCC[030] VCC[097] VSS[031] VSS[112]
D17 AF17 D19 AA14
VCC[031] VCC[098] VSS[032] VSS[113]
D18 AF18 D23 AA16
VCC[032] VCC[099] VSS[033] VSS[114]
E7 AF20 D26 AA19
VCC[033] VCC[100] SHORT-0603-PWR VSS[034] VSS[115]
E9 E3 AA22
VCC[034] VSS[035] VSS[116]
E10 G21 E6 AA25
VCC[035] VCCP[01] VSS[036] VSS[117]
E12 V6 E8 AB1
VCC[036] VCCP[02] R52 VSS[037] VSS[118]
E13 J6 E11 AB4
3 VCC[037] VCCP[03] VSS[038] VSS[119] 3
E15 K6 E14 AB8
VCC[038] VCCP[04] VSS[039] VSS[120]
E17 M6 E16 AB11
VCC[039] VCCP[05] VSS[040] VSS[121]
E18 J21 E19 AB13
VCC[040] VCCP[06] VSS[041] VSS[122]
E20 K21 E21 AB16
VCC[041] VCCP[07] VSS[042] VSS[123]
F7 M21 E24 AB19
VCC[042] VCCP[08] VSS[043] VSS[124]
F9 N21 F5 AB23
VCC[043] VCCP[09] VSS[044] VSS[125]
F10 N6 F8 AB26
VCC[044] VCCP[10] VSS[045] VSS[126]
F12 R21 F11 AC3
VCC[045] VCCP[11] VSS[046] VSS[127]
F14 R6 F13 AC6
VCC[046] VCCP[12] 16,21,22,24,27,36,43 1.5VS VSS[047] VSS[128]
North side secondary South side secondary F15
F17
VCC[047] VCCP[13]
T21
T6
Close to CPU F16
F19
VSS[048] VSS[129]
AC8
AC11
VCC[048] VCCP[14] VSS[049] VSS[130]
F18
VCC[049] VCCP[15]
V21 pin B26 F2
VSS[050] VSS[131]
AC14
F20
AA7
VCC[050] VCCP[16]
W21
20mil F22
F25
VSS[051] VSS[132]
AC16
AC19
VCC[051] VSS[052] VSS[133]
C92

C114

C66

C463

C77

C67

AA9 B26 R438 G4 AC21


VCC[052] VCCA[01] 0 5% 1/4W 1206 VSS[053] VSS[134]
AA10 C26 G1 AC24
VCC[053] VCCA[02] VSS[054] VSS[135]
+ + + + + + AA12 G23 AD2
VCC[054] C431 C435 VSS[055] VSS[136]
AA13 AD6 H_VID0 10 G26 AD5
VCC[055] VID[0] 0.01uF 16V 10% 0402 X7R 10uF 6.3V 10% 0805 X5R VSS[056] VSS[137]
AA15 AF5 H_VID1 10 H3 AD8
VCC[056] VID[1] VSS[057] VSS[138]
T330uF 2V 9m 7343 PANASONIC

T330uF 2V 9m 7343 PANASONIC

T330uF 2V 9m 7343 PANASONIC_NU

T330uF 2V 9m 7343 PANASONIC

T330uF 2V 9m 7343 PANASONIC

T330uF 2V 9m 7343 PANASONIC_NU

AA17 AE5 H_VID2 10 H6 AD11


VCC[057] VID[2] VSS[058] VSS[139]
AA18 AF4 H_VID3 10 H21 AD13
VCC[058] VID[3] VSS[059] VSS[140]
AA20 AE3 H_VID4 10 H24 AD16
VCC[059] VID[4] VSS[060] VSS[141]
AB9 AF3 H_VID5 10 J2 AD19
VCC[060] VID[5] VSS[061] VSS[142]
AC10 AE2 H_VID6 10 J5 AD22
VCC[061] VID[6] VSS[062] VSS[143]
AB10 J22 AD25
VCC[062] VSS[063] VSS[144]
AB12 J25 AE1
VCC[063] VSS[064] VSS[145]
AB14 AF7 K1 AE4
VCC[064] VCCSENSE 10 VCORE_CPU VSS[065] VSS[146]
AB15 K4 AE8
VCC[065] VSS[066] VSS[147]
AB17 K23 AE11
VCC[066] VSS[067] VSS[148]
AB18 AE7 K26 AE14
VCC[067] VSSSENSE VSS[068] VSS[149]
L3 AE16
SCKT INTEL CPU PZ4782A-274M-41 FCPGA 478P FOXCONN for Penryn VSS[069] VSS[150]
L6 AE19
6026B0056801 R459 VSS[070] VSS[151]
L21 AE23
100-1%-1/16W-0402 VSS[071] VSS[152]
L24 AE26
VSS[072] VSS[153]
M2 A2
VSS[073] VSS[154]
M5 AF6
VSS[074] VSS[155]
VCCSENSE 10 M22 AF8
VSS[075] VSS[156]
M25 AF11
VSS[076] VSS[157]
VSSSENSE 10 N1 AF13
2 VSS[077] VSS[158] 2
N4 AF16
VSS[078] VSS[159]
R460 18mil N23
N26
VSS[079] VSS[160]
AF19
AF21
100-1%-1/16W-0402 VSS[080] VSS[161]
7mil space P3
VSS[081] VSS[162]
A25
AF25
VSS[163]
SCKT INTEL CPU PZ4782A-274M-41 FCPGA 478P FOXCONN for Penryn
6026B0056801

Route VCCSENSE and VSSSENSE traces at 27.4


ohms with 25mil spacing with others. Place
PU and PD within 1 inch of CPU

1 1

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
C AX1
Penryn Processor(2/2)
Date: Wednesday, July 02, 2008 Sheet 9 of 45
A B C D E
5 4 3 2 1

D D

5VA 24,35,37,40,41,42

10uF 6.3V 10% 0805 X5R


10-5%-1/10W-0603

C226
R160

T5.6uF 25V 100m 3528 SANYO


8770VCC

C225
DCIN 25,37,39,40,41,42,43,44,45
2.2uF 10V 10% 0805 X5R

+ C216 C599 + C598


8770GND C189 T5.6uF 25V 100m 3528 SANYO

5
6
7
8
9
0.1uF 25V 10% 0603 X5R
R209 0.1uF 25V 10% 0603 X5R
200K 1% 1/16W 0402 D Q13
8,11,13,16,18,21,22,23,24,25,26,27,28,31,32,33,34,35,36,38,41,42 3VS
4 FDMS8692 30V 28A

19

25
S 9 VCORE_CPU
U15
8 0.22uF 25V 10% 0603 X5R

VCC

VDD
TON

1
2
3
R213 R214 R163 2.2 5% 1/16 0402 C230
2.2K-5%-1/16W-0402 2.2K-5%-1/16W-0402 30 L12
BST1
C 28 C
LX1
13,23 VCORE_GD 2 0.36uH 30A PCMC104T-R36MN
PWRGD
29
DH1

5
6
7
8
9

5
6
7
8
9
1 Q10 Q8 R169
23 CLK_EN# CLKEN 2.67K 1% 1/10W 0603
26
DL1 D D

FDMS8672S 30V 35A 8P

FDMS8672S 30V 35A 8P


9 H_VID0 R159 SHORT-0402-5MIL 31 27 4 S 4 S R162 10K-5%-0603-NTC
R166 SHORT-0402-5MIL D0 PGND1
9 H_VID1 32
R171 SHORT-0402-5MIL D1
9 H_VID2 33
D2

1
2
3

1
2
3
9 H_VID3 R174 SHORT-0402-5MIL 34 100-1%-1/16W-0402 2.1K 1% 1/10W 0603 R110
D3 R201
R177 SHORT-0402-5MIL 35 R202
9 H_VID4 D4
R183 SHORT-0402-5MIL 36 12 3.9K 1% 1/10W 0603
9 H_VID5 D5 FB
9 H_VID6 R190 SHORT-0402-5MIL 37 C236
D6 0.22uF 10V 10% 0603 X7R
C243
1000pF 50V 10% 0402 X7R
8 PSI# R215 0-5%-1/16W-0402 3
PSI
38 VR_ON R195 0-5%-1/16W-0402 38 20K-1%-1/16W-0402 8770GND 8770CSP1
SHDN R221
10 VCCSENSE 9
R205 0-5%-1/16W-0402 CCI C245 8770CSN1
8,13,21 H_DPRSTP# 40
DPRSTP 470pF 50V 10% 0402 X7R
R198 499 1% 1/16W 0402 R194 25,37,39,40,41,42,43,44,45 DCIN
13,23 PM_DPRSLPVR 39 13 VSSSENSE 9
DPRSLPVR GNDS 100-1%-1/16W-0402
C244
470pF 50V 10% 0402 X7R 9 C241
CCV 1000pF 50V 10% 0402 X7R
71.5K 1% 1/10W 0603 16 8770CSN1
R218 CSN1
7
TIME 8770CSP1 8770GND
17
CSP1
C246 8770REF 11 + C256
8770GND REF
0.22uF 10V 10% 0603 X7R 14 8770CSP2 AL15uF 25V 20% 105C 6.3X4.4
CSP2

5
6
7
8
9
8770GND 18
GND 8770CSN2
41 15
R217 EP CSN2 D Q18
10K-5%-1/16W-0402 4 S FDMS8692 30V 28A
8770VCC 6 21
B THRM DH2 B

1
2
3
24 L21
0-5%-1/16W-0402 DL2
R216 22
LX2 R156 2.2 5% 1/16 0402
8 H_PROCHOT# 5 0.36uH 30A PCMC104T-R36MN
VRHOT
20
BST2

5
6
7
8
9

5
6
7
8
9
R224 10K-5%-1/16W-0402_NU 4 R184
38 PCPU POUT C227 2.67K 1% 1/10W 0603
23
PGND2 0.22uF 25V 10% 0603 X5R D Q21 D Q20 10K-5%-0603-NTC
4 S 4 S R113
C249
0.1uF 16V -20%+80% 0402_NU MAX8770GTL+ TQFN 40P MAXIM R185
1
2
3

1
2
3
6019B0130201 2.1K 1% 1/10W 0603
R152

C239
0.22uF 10V 10% 0603 X7R
8770GND SHORT-0402-40MIL
FDMS8672S 30V 35A 8P

FDMS8672S 30V 35A 8P


8770CSP2

8770CSN2

A A

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M) Rev
Document Number
C AX1
CPU Core Power
Date: Wednesday, July 02, 2008 Sheet 10 of 45
5 4 3 2 1
8 7 6 5 4 3 2 1

D D

THERMAL SENSOR
8,10,13,16,18,21,22,23,24,25,26,27,28,31,32,33,34,35,36,38,41,42 3VS

0.1uF 10V 10% 0402 X7R

10K-5%-1/16W-0402
C432

R422
U40
1 8 THRMSCK
VDD SMCLK THRMSCK 38
H_THERMDA R425 100-1%-1/16W-0402 100pF 50V 5% 0402 NPO 2 7 THRMSDA 10mil
8 H_THERMDA D+ SMDATA THRMSDA 38
C427
10mil H_THERMDC R423 100-1%-1/16W-0402 3 6
8 H_THERMDC D- ALERT
THRM# 4 5
THERM GND
EMC1402-1-ACZL-TR MSOP 8P
6019B0437701

C C

B B

Fan control

Q50
FDN338P 20V 1.6A SOT3 5VS_FAN
CN29

24,25,26,27,28,29,31,32,33,38,41 5VS S D 30mil G1


1
G1
1
2
S

38 FANCTL1 2
10uF 10V 10% 0805 X5R
C511

0.01uF 16V 10% 0402 X7R


C510

38 FAN_TACH1 3
3
G

4
4
C502
3300pF 50V 10% 0402 X7R_NU

C501
3300pF 50V 10% 0402 X7R_NU
G2
G2
G

R496
1K-5%-1/16W-0402 4P 85205-04001 ACES
6012A0081602

R497
0-5%-1/16W-0402
C

A A
38 FAN_ON B Q51
NPN PDTC144EU 50V 100mA SOT223
E

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M)
Document Number Rev
C AX1
CPU Thermal
Date: Wednesday, July 02, 2008 Sheet 11 of 45
8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

H H

H_A#[35..3]
H_D#[63..0] H_A#[35..3] 8
U45A
8 H_D#[63..0]
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 C15
G H_D#1 H_D#_0 H_A#_4 H_A#5 G
G8 F16
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H13
H_D#3 H_D#_2 H_A#_6 H_A#7
E6 C18
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 M16
H_D#5 H_D#_4 H_A#_8 H_A#9
H6 J13
8,9,13,16,18,21,24,38,42 1.05VS H_D#6 H_D#_5 H_A#_9 H_A#10
H2 P16
H_D#7 H_D#_6 H_A#_10 H_A#11
F6 R16
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 N17
H_D#9 H_D#_8 H_A#_12 H_A#13
H3 M13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 E17
R43 H_D#11 H_D#_10 H_A#_14 H_A#15
M11 P17
221-1%-1/16W-0402 H_D#12 H_D#_11 H_A#_15 H_A#16
10mil H_D#13
J1
J2
H_D#_12 H_A#_16
F17
G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 B19
H_SWING H_D#15 H_D#_14 H_A#_18 H_A#19
J6 J16
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 E20
H_D#17 H_D#_16 H_A#_20 H_A#21
L2 H16
C65 H_D#18 H_D#_17 H_A#_21 H_A#22
R2 J20
H_RCOMP 0.1uF 10V 10% 0402 X7R H_D#19 H_D#_18 H_A#_22 H_A#23
F
10mil R46 H_D#20
N9
L6
H_D#_19 H_A#_23
L17
A17 H_A#24 F
100-1%-1/16W-0402 H_D#21 H_D#_20 H_A#_24 H_A#25
M5 B17
R444 H_D#22 H_D#_21 H_A#_25 H_A#26
J3 L16
24.9-1%-1/16W-0402 H_D#23 H_D#_22 H_A#_26 H_A#27
N2 C21
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 J17
H_D#25 H_D#_24 H_A#_28 H_A#29
N5 H20
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 B18
H_D#27 H_D#_26 H_A#_30 H_A#31
P13 K17
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 B20
H_D#29 H_D#_28 H_A#_32 H_A#33
L7 F21
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 K21
H_D#31 H_D#_30 H_A#_34 H_A#35
M3 L20
H_D#32 H_D#_31 H_A#_35
Trace should be 10-mil wide with 20-mil spacing H_D#33
Y3
AD14
H_D#_32
H12
H_D#_33 H_ADS# H_ADS# 8
H_D#34 Y6 B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 8
H_D#35 Y10 G17
H_D#36 H_D#_35 H_ADSTB#_1 H_ADSTB#1 8

HOST
Y12 A9 H_BNR# 8
H_D#37 H_D#_36 H_BNR#
Y14 F11 H_BPRI# 8
H_D#38 H_D#_37 H_BPRI#
Y7 G12 H_BREQ#0 8
H_D#39 H_D#_38 H_BREQ#
E W2 E9 H_DEFER# 8 E
H_D#40 H_D#_39 H_DEFER#
AA8 B10 H_DBSY# 8
H_D#41 H_D#_40 H_DBSY#
Y9 AH7 CLK_MCH_BCLK 18
H_D#42 H_D#_41 HPLL_CLK
AA13 AH6 CLK_MCH_BCLK# 18
H_D#43 H_D#_42 HPLL_CLK#
AA9 J11 H_DPWR# 8
H_D#44 H_D#_43 H_DPWR#
AA11 F9 H_DRDY# 8
H_D#45 H_D#_44 H_DRDY#
AD11 H9 H_HIT# 8
H_D#46 H_D#_45 H_HIT#
AD10 E12 H_HITM# 8
H_D#47 H_D#_46 H_HITM#
AD13 H11 H_LOCK# 8
H_D#48 H_D#_47 H_LOCK#
AE12 C9 H_TRDY# 8
H_D#49 H_D#_48 H_TRDY#
AE9
H_D#50 H_D#_49
AA2
H_D#51 H_D#_50
AD8
H_D#52 H_D#_51
AA3
H_D#53 H_D#_52
AD3 J8 H_DINV#0 8
H_D#54 H_D#_53 H_DINV#_0
AD7 L3 H_DINV#1 8
H_D#55 H_D#_54 H_DINV#_1
AE14 Y13 H_DINV#2 8
H_D#56 H_D#_55 H_DINV#_2
AF3 Y1 H_DINV#3 8
H_D#57 H_D#_56 H_DINV#_3
AC1
H_D#58 H_D#_57
AE3 L10 H_DSTBN#0 8
D H_D#59 AC3
H_D#_58 H_DSTBN#_0
M7 D
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#1 8
AE11 AA5 H_DSTBN#2 8
H_D#61 H_D#_60 H_DSTBN#_2
AE8 AE6 H_DSTBN#3 8
H_D#62 H_D#_61 H_DSTBN#_3
AG2
H_D#63 H_D#_62
AD6 L9 H_DSTBP#0 8
H_D#_63 H_DSTBP#_0
M8 H_DSTBP#1 8
H_DSTBP#_1
AA6 H_DSTBP#2 8
H_SWING H_DSTBP#_2
C5 AE5 H_DSTBP#3 8
H_RCOMP H_SWING H_DSTBP#_3 H_REQ#[4..0]
E3 H_REQ#[4..0] 8
H_RCOMP H_REQ#0
B15
H_REQ#_0 H_REQ#1
K13
H_REQ#_1 H_REQ#2
F13
H_REQ#_2 H_REQ#3
B13
H_REQ#_3 H_REQ#4
8 H_CPURST# C12 B14
H_CPURST# H_REQ#_4
8 H_CPUSLP# E11
8,9,13,16,18,21,24,38,42 1.05VS H_CPUSLP#
B6 H_RS#0 8
H_RS#_0
F12 H_RS#1 8
H_RS#_1
C8 H_RS#2 8
H_AVREF H_RS#_2
A11
C H_AVREF C
B11
R456 H_DVREF
1K-1%-1/16W-0402 Cantiga FBGA 1329P INTEL 6019B0383501

10mil

R453 C478 R455


2K-1%-1/16W-0402 0.1uF 10V 10% 0402 X7R 0-5%-1/16W-0402

H_DVREF

B B

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
A A
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M)Rev
Document Number
C AX1
Cantiga Host(1/6)
Date: Wednesday, July 02, 2008 Sheet 12 of 45
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

15,16,19,20,41,43 1.5V
U45B

1K-1%-1/16W-0402_NU
AP24 M_CLK_DDR0 19
SA_CK_0 8,10,11,16,18,21,22,23,24,25,26,27,28,31,32,33,34,35,36,38,41,42 3VS
M36 AT21 M_CLK_DDR1 19
RSVD1 SA_CK_1
N36 AV24 M_CLK_DDR2 20
RSVD2 SB_CK_0
R33 AU20 M_CLK_DDR3 20
RSVD3 SB_CK_1 R646
T33
H AH9
RSVD4
AR24 H
RSVD5 SA_CK#_0 M_CLK_DDR#0 19
AH10 AR21 M_CLK_DDR#1 19
RSVD6 SA_CK#_1

R105

R93

R103

R104
AH12
AH13
RSVD7 SB_CK#_0
AU24
AV20
M_CLK_DDR#2 20 Route M_OCDCMOP 0&1 as short as possible
RSVD8 SB_CK#_1 M_CLK_DDR#3 20 M_VREF_NB
K12
RSVD9

RSVD
ME_JTAG_TCK AL34 BC28 M_CKE0 19
RSVD10 SA_CKE_0

1K-1%-1/16W-0402_NU
AK34 AY28 M_CKE1 19
ME_JTAG_TDI RSVD11 SA_CKE_1

2.2K-5%-1/16W-0402

2.2K-5%-1/16W-0402
AN35 AY36 R647 C168
ME_JTAG_TDO RSVD12 SB_CKE_0 M_CKE2 20

10K-5%-1/16W-0402

10K-5%-1/16W-0402
AM35 BB36 C167 0.1uF 10V 10% 0402 X7R
ME_JTAG_TMS RSVD13 SB_CKE_1 M_CKE3 20 0.1uF 10V 10% 0402 X7R
T24
RSVD14
BA17 M_CS#0 19
SA_CS#_0
B31 AY16 M_CS#1 19
RSVD15 SA_CS#_1
B2 AV16 M_CS#2 20
RSVD16 SB_CS#_0

MUXING
M1 AR13 M_CS#3 20
RSVD17 SB_CS#_1
AY21 BD17 U45C 16 VCC_PEG
RSVD20 SA_ODT_0 M_ODT0 19
AY17 M_ODT1 19 0-5%-1/16W-0402_NU
SA_ODT_1 R94
BG23 BF15 M_ODT2 20 L32
RSVD22 SB_ODT_0 25,38 INV_PWM L_BKLT_CTRL PEG_COMP
BF23 AY13 M_ODT3 20 G32 T37
G RSVD23 SB_ODT_1 25 BL_ENA L_BKLT_EN PEG_COMPI R470 G
BH18 M32 T36
RSVD24 M_RCOMP L_CTRL_CLK PEG_COMPO 49.9-1%-1/16W-0402
BF18 BG22 M33
RSVD25 SM_RCOMP M_RCOMP# L_CTRL_DATA
BH21 25 LVDS_DDCPCLK K33
1.05VM 15,16,18,42 SM_RCOMP# L_DDC_CLK
20mil 25 LVDS_DDCPDATA J33 H44

DDR
3VM 18,19,20,23,43 M_RCOMP_VOH R79 L_DDC_DATA PEG_RX#_0
BF28 M29 J46
SM_RCOMP_VOH M_RCOMP_VOL 25 LVDS_VDDEN SHORT-0402-5MIL L_VDD_EN PEG_RX#_1
BH28 L44
SM_RCOMP_VOL 0-5%-1/16W-0402 2.37K-1%-1/16W-0402 R469 PEG_RX#_2
C44 L40
M_VREF_NB R648 L_VBG LVDS_IBG PEG_RX#_3
AV42 M_VREF 19,20,41 TP1 1 B43 N41
SM_VREF LVDS_VBG PEG_RX#_4
AR36 SM_PWROK 41 E37 P48
SM_PWROK SM_REXT R59 LVDS_VREFH PEG_RX#_5
G2 BF17 E38 N44
G2 SM_REXT 499 1% 1/16W 0402 LVDS_TXCLK_LN LVDS_VREFL PEG_RX#_6
10 BC36 DDR3_DRAMRST# 19,20 C41 T43
10 SM_DRAMRST# 25 LVDS_TXCLK_LN LVDSA_CLK# PEG_RX#_7
10P 87213-1000G ACES_NU

9 LVDS_TXCLK_LP C40 U43


9 25 LVDS_TXCLK_LP LVDSA_CLK PEG_RX#_8
8 B37 Y43
8 LVDSB_CLK# PEG_RX#_9
6012A0136201_NU

LVDS
7 A37 Y48
7 LVDSB_CLK PEG_RX#_10
6 B38 DREFCLK 18 Y36
6 ME_JTAG_TCK DPLL_REF_CLK LVDS_TXOUT_L0N PEG_RX#_11
5 A38 DREFCLK# 18 H47 AA43
5 ME_JTAG_TDI DPLL_REF_CLK# 25 LVDS_TXOUT_L0N LVDS_TXOUT_L1N LVDSA_DATA#_0 PEG_RX#_12
4 ME_JTAG_TMS E41 DREFSSCLK 18 25 LVDS_TXOUT_L1N E46 AD37
4 DPLL_REF_SSCLK LVDSA_DATA#_1 PEG_RX#_13

CLK
3 F41 LVDS_TXOUT_L2N G40 AC47
3 ME_JTAG_TDO DPLL_REF_SSCLK# DREFSSCLK# 18 25 LVDS_TXOUT_L2N LVDSA_DATA#_2 PEG_RX#_14
2 A40 AD39
2 LVDSA_DATA#_3 PEG_RX#_15
F 1
1
PEG_CLK
F43 CLK_PCIE_3GPLL 18 F
G1 E43 LVDS_TXOUT_L0P H48 H43

GRAPHICS
G1 PEG_CLK# CLK_PCIE_3GPLL# 18 25 LVDS_TXOUT_L0P LVDSA_DATA_0 PEG_RX_0
LVDS_TXOUT_L1P D45 J44
CN6 25 LVDS_TXOUT_L1P LVDS_TXOUT_L2P LVDSA_DATA_1 PEG_RX_1
F40 L43
25 LVDS_TXOUT_L2P LVDSA_DATA_2 PEG_RX_2 DVI_HPD#
B40 L41 DVI_HPD# 33
DMI_TXN0 LVDSA_DATA_3 PEG_RX_3
AE41 N40
DMI_RXN_0 DMI_TXN1 PEG_RX_4
AE37 A41 P47
DMI_RXN_1 DMI_TXN2 LVDSB_DATA#_0 PEG_RX_5
AE47 H38 N43
DMI_RXN_2 DMI_TXN3 DMI_TXN[3..0] LVDSB_DATA#_1 PEG_RX_6
AH39 DMI_TXN[3..0] 22 G37 T42
DMI_RXN_3 LVDSB_DATA#_2 PEG_RX_7
J37 U42
DMI_TXP0 LVDSB_DATA#_3 PEG_RX_8
AE40 Y42
DMI_RXP_0 DMI_TXP1 PEG_RX_9
18 MCH_BSEL0 T25 AE38 B42 W47
CFG_0 DMI_RXP_1 DMI_TXP2 LVDSB_DATA_0 PEG_RX_10
18 MCH_BSEL1 R25 AE48 G38 Y37
CFG_1 DMI_RXP_2 DMI_TXP3 DMI_TXP[3..0] LVDSB_DATA_1 PEG_RX_11
18 MCH_BSEL2 P25 AH40 DMI_TXP[3..0] 22 F37 AA42
CFG_2 DMI_RXP_3 LVDSB_DATA_2 PEG_RX_12
P20 K37 AD36
CFG_3 LVDSB_DATA_3 PEG_RX_13
DMI

P24 AE35 DMI_RXN0 AC48

PCI-EXPRESS
MCH_CFG5 CFG_4 DMI_TXN_0 DMI_RXN1 PEG_RX_14
C25 AE43 AD40
MCH_CFG6 CFG_5 DMI_TXN_1 DMI_RXN2 PEG_RX_15
N24 AE46
MCH_CFG7 CFG_6 DMI_TXN_2 DMI_RXN3 DMI_RXN[3..0]
M24 AH42 DMI_RXN[3..0] 22 R68 75-5%-1/16W-0402 F25 J41 TMDSB_TXN0
CFG_7 DMI_TXN_3 TVA_DAC PEG_TX#_0
CFG

E21 R69 75-5%-1/16W-0402 H25 M46 TMDSB_TXN1


E MCH_CFG9 CFG_8 DMI_RXP0 TVB_DAC PEG_TX#_1 E
C23 AD35 R70 75-5%-1/16W-0402 K25 M47 TMDSB_TXN2
CFG_9 DMI_TXP_0 TVC_DAC PEG_TX#_2

TV
MCH_CFG10 C24 AE44 DMI_RXP1 M40 TMDSB_TXN3
CFG_10 DMI_TXP_1 DMI_RXP2 PEG_TX#_3
N21 AF46 M42
MCH_CFG12 CFG_11 DMI_TXP_2 DMI_RXP3 DMI_RXP[3..0] PEG_TX#_4
P21 AH43 DMI_RXP[3..0] 22 H24 R48
MCH_CFG13 CFG_12 DMI_TXP_3 TV_RTN PEG_TX#_5
T21 N38
CFG_13 PEG_TX#_6
R20 T40
CFG_14 C611 5pF 50V 0.25% 0402 C0G PEG_TX#_7
M20 C31 U37
MCH_CFG16 CFG_15 TV_DCONSEL_0 PEG_TX#_8
L21 E32 U40
CFG_16 C612 5pF 50V 0.25% 0402 C0G TV_DCONSEL_1 PEG_TX#_9
H21 Y40
GRAPHICS VID

CFG_17 PEG_TX#_10
P29 AA46
MCH_CFG19 CFG_18 C613 5pF 50V 0.25% 0402 C0G PEG_TX#_11
R28 AA37
MCH_CFG20 CFG_19 PEG_TX#_12
T28 B33 GFX_VID_0 42 AA40
CFG_20 GFX_VID_0 PEG_TX#_13
B32 GFX_VID_1 42 AD43
GFX_VID_1 CRT_BLUE PEG_TX#_14
G33 GFX_VID_2 42 E28 AC46
GFX_VID_2 26 CRT_BLUE CRT_BLUE PEG_TX#_15
F33 GFX_VID_3 42
GFX_VID_3 CRT_GREEN
23 PM_SYNC#
R78 SHORT-0402-5MIL R29 E33 GFX_VID_4 42 G28 J42 TMDSB_TXP0
R449 SHORT-0402-5MIL PM_BM_BUSY# GFX_VID_4 26 CRT_GREEN CRT_GREEN PEG_TX_0
8,10,21 H_DPRSTP# B7 L46 TMDSB_TXP1
PM_EXTTS#0 PM_DPRSTP# CRT_RED PEG_TX_1
PM_EXTTS#0 N33 26 CRT_RED J28 M48 TMDSB_TXP2
PM_EXTTS#1 PM_EXT_TS#_0 CRT_RED PEG_TX_2
M39 TMDSB_TXP3
PM

R101 SHORT-0402-5MIL P32 C34


D 19,20 TS#_DIMM0_1 PM_EXT_TS#_1 GFX_VR_EN GFX_VR_EN 42 PEG_TX_3 D
R100 SHORT-0402-5MIL AT40 G29 M43
10,23 VCORE_GD PWROK CRT_IRTN PEG_TX_4

VGA
R53 100-5%-1/16W-0402 AT11 R47
22 PLT_RST# RSTIN# PEG_TX_5
8,21 PM_THRMTRIP# T20 N37
R85 SHORT-0402-5MIL THERMTRIP# PEG_TX_6
10,23 PM_DPRSLPVR R32 T39
DPRSLPVR PEG_TX_7
H32 U36
26 CRT_DDC_CLK CRT_DDC_CLK PEG_TX_8
AH37 CL_CLK0 23 J32 U39
CL_CLK 0-5%-1/16W-0402 26 CRT_DDC_DATA R89 30.1-0.5%-1/16W-0402 CRT_DDC_DATA PEG_TX_9
AH36 CL_DATA0 23 J29 Y39
CL_DATA R96 26 CRT_HSYNC REFSET CRT_HSYNC PEG_TX_10
BG48 AN36 MPWROK 23,38 E29 Y46
NC_1 CL_PWROK R95 30.1-0.5%-1/16W-0402 CRT_TVO_IREF PEG_TX_11
BF48 AJ35 CL_RST#0 23 26 CRT_VSYNC L29 AA36
NC_2 CL_RST# CRT_VSYNC PEG_TX_12
ME

BD48 AH34 MCH_CLVREF AA39


NC_3 CL_VREF PEG_TX_13
BC48 AD42
NC_4 PEG_TX_14
BH47 AD46
NC_5 PEG_TX_15
BG47
NC_6
BE47
NC_7 DDPC_CTRLCLK
N28 Place 150ohm termination resistor
NC

1.02K 1% 1/16 0402


BH46 M28 Cantiga FBGA 1329P INTEL 6019B0383501
NC_8 DDPC_CTRLDATA
BF46
NC_9 SDVO_CTRL_CLK
G36 SDVO_CTRL_CLK 33 close to GMCH

R84
BG45 E36 SDVO_CTRL_DATA 33
NC_10 SDVO_CTRL_DATA
MISC

BH44 K36 CLKREQ#_GMCH 18


NC_11 CLK_REQ#
BH43 H36 MCH_ICH_SYNC# 23
C NC_12 ICH_SYNC# C
BH6
BH5
NC_13 change to 1.02K ohm As close as possible to GMCH and Minimum
NC_14 R458
BG4
BH3
NC_15
B12 1.05VS 8,9,12,16,18,21,24,38,42 spacing of 20 mils away from any toggle
NC_16 TSATN#
BF3
NC_17 signals
BH2
NC_18 56-5%-1/16W-0402
BG2
BE2
NC_19
B28
When the display is completely white , the RGB voltage is
NC_20 HDA_BCLK
BG1
NC_21 HDA_RST#
B30
1.05VM_AXD 16 between 665mV to 770mV by VESA Spec
BF1 B29
NC_22 HDA_SDI
BD1
BC1
NC_23 HDA_SDO
C29
A28
If meet , CRT_IREF resistor value is optimal
NC_24 HDA_SYNC
F1
NC_25
A47
NC_26 R88
Cantiga FBGA 1329P INTEL 6019B0383501 1K-1%-1/16W-0402
10mil
1.5V 15,16,19,20,41,43 TMDSB_TXN0 C166 0.068uF 10V 10% 0402 X5R
MCH_CLVREF TMDSB_TXP0 C165 0.068uF 10V 10% 0402 X5R TMDS_TXN0 33
TMDS_TXP0 33
B R106 PM_EXTTS#0 B
4,35,36,38,41,42 3VS
10K-5%-1/16W-0402 TMDSB_TXN1 C187 0.068uF 10V 10% 0402 X5R

R102 PM_EXTTS#1
CRESTLINE (965GM) Strapping: C144
0.1uF 10V 10% 0402 X7R
R90
511 1% 1/16W 0402
TMDSB_TXP1 C188 0.068uF 10V 10% 0402 X5R TMDS_TXN1
TMDS_TXP1
33
33
10K-5%-1/16W-0402 Low High R80 TMDSB_TXN2 C176 0.068uF 10V 10% 0402 X5R
1K-1%-1/16W-0402 TMDSB_TXP2 C175 0.068uF 10V 10% 0402 X5R TMDS_TXN2 33
TMDS_TXP2 33
MCH_CFG5 DMIx2 DMIx4 change to 511 ohm 0.01uF 16V 10% 0402 X7R
8,10,11,16,18,21,22,23,24,25,26,27,28,31,32,33,34,35,36,38,41,42 3VS M_RCOMP_VOH TMDSB_TXN3 C170 0.068uF 10V 10% 0402 X5R TMDS_CLKN 33
MCH_CFG6(iTPM Host I/F) Enable Disable(default) TMDSB_TXP3 C169 0.068uF 10V 10% 0402 X5R TMDS_CLKP 33
MCH_CFG19 R91 4.02K-1%-1/16W-0402_NU MCH_CFG7(TLS confidentiality) With With no(default) R81 C127 C123
MCH_CFG20 R92 4.02K-1%-1/16W-0402_NU 15,16,19,20,41,43 1.5V 3.01K 1% 1/16 0402 2.2uF 10V 10% 0805 X5R
MCH_CFG9 (PCIE Graphic Lane) Reverse Lane Normal Operation
MCH_CFG5 R66 2.2K-5%-1/16W-0402_NU MCH_CFG10 (PCIE loopback) Enable Disable(default)
MCH_CFG6 R72 2.2K-5%-1/16W-0402_NU R462
MCH_CFG7
MCH_CFG9
R71
R63
2.2K-5%-1/16W-0402_NU
2.2K-5%-1/16W-0402_NU
MCH_CFG12 (ALLZ) Enable Disable(default) 80.6-1%-1/10W-0603
M_RCOMP
M_RCOMP_VOL Inventec Corporation
MCH_CFG10 R65 2.2K-5%-1/16W-0402_NU 66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
A MCH_CFG12 R62 2.2K-5%-1/16W-0402_NU
MCH_CFG13(XOR) Enable Disable(default) 10mil R73
A
MCH_CFG13 R60 2.2K-5%-1/16W-0402_NU MCH_CFG16 (FSB Dynamic ODT) Dynamic ODT Disable Dynamic ODT Enable M_RCOMP# 1K-1%-1/16W-0402 C117 C135 TEL:+886-2-2881-0721
MCH_CFG16 R61 2.2K-5%-1/16W-0402_NU 2.2uF 10V 10% 0805 X5R
80.6-1%-1/10W-0603 Title
MCH_CFG19 (DMI Lane Reversal) Normal Lanes Reversed R461
MCH_CFG20 Only SDVO or PCIE x1 is Only SDVO or PCIE x1
0.01uF 16V 10% 0402 X7R Size
S118D(Penryn+Cantiga+ICH9M)Rev
Document Number
operation with PEG port C AX1
Cantiga DMI/Graph2/6)
Date: Wednesday, July 02, 2008 Sheet 13 of 45
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

H H

G G

M_A_DQ[63..0]
19 M_A_DQ[63..0] M_B_DQ[63..0]
U45D
20 M_B_DQ[63..0]
M_A_DQ0 AJ38 BD21 U45E
SA_DQ_0 SA_BS_0 M_A_BS0 19
M_A_DQ1 AJ41 BG18 M_B_DQ0 AK47 BC16
SA_DQ_1 SA_BS_1 M_A_BS1 19 SB_DQ_0 SB_BS_0 M_B_BS0 20
M_A_DQ2 AN38 AT25 M_B_DQ1 AH46 BB17
SA_DQ_2 SA_BS_2 M_A_BS2 19 SB_DQ_1 SB_BS_1 M_B_BS1 20
M_A_DQ3 AM38 M_B_DQ2 AP47 BB33
SA_DQ_3 SB_DQ_2 SB_BS_2 M_B_BS2 20
M_A_DQ4 AJ36 BB20 M_B_DQ3 AP46
M_A_DQ5 SA_DQ_4 SA_RAS# M_A_RAS# 19 M_B_DQ4 SB_DQ_3
AJ40 BD20 M_A_CAS# 19 AJ46 AU17 M_B_RAS# 20
M_A_DQ6 SA_DQ_5 SA_CAS# M_B_DQ5 SB_DQ_4 SB_RAS#
AM44 AY20 M_A_WE# 19 AJ48 BG16 M_B_CAS# 20
M_A_DQ7 SA_DQ_6 SA_WE# M_B_DQ6 SB_DQ_5 SB_CAS#
AM42 AM48 BF14 M_B_WE# 20
M_A_DQ8 SA_DQ_7 M_A_DM0 M_A_DM[7..0] M_B_DQ7 SB_DQ_6 SB_WE#
AN43 AM37 M_A_DM[7..0] 19 AP48
M_A_DQ9 SA_DQ_8 SA_DM_0 M_A_DM1 M_B_DQ8 SB_DQ_7
AN44 AT41 AU47
M_A_DQ10 SA_DQ_9 SA_DM_1 M_A_DM2 M_B_DQ9 SB_DQ_8 M_B_DM0 M_B_DM[7..0]
AU40 AY41 AU46 AM47 M_B_DM[7..0] 20
M_A_DQ11 SA_DQ_10 SA_DM_2 M_A_DM3 M_B_DQ10 SB_DQ_9 SB_DM_0 M_B_DM1
AT38 AU39 BA48 AY47
M_A_DQ12 SA_DQ_11 SA_DM_3 M_A_DM4 M_B_DQ11 SB_DQ_10 SB_DM_1 M_B_DM2
AN41 BB12 AY48 BD40
M_A_DQ13 SA_DQ_12 SA_DM_4 M_A_DM5 M_B_DQ12 SB_DQ_11 SB_DM_2 M_B_DM3
AN39 AY6 AT47 BF35
M_A_DQ14 SA_DQ_13 SA_DM_5 M_A_DM6 M_B_DQ13 SB_DQ_12 SB_DM_3 M_B_DM4
F AU44
SA_DQ_14 SA_DM_6
AT7 AR47
SB_DQ_13 SB_DM_4
BG11 F
M_A_DQ15 AU42 AJ5 M_A_DM7 M_A_DQS[7..0] M_B_DQ14 BA47 BA3 M_B_DM5
SA_DQ_15 SA_DM_7 M_A_DQS[7..0] 19 SB_DQ_14 SB_DM_5
M_A_DQ16 AV39 M_B_DQ15 BC47 AP1 M_B_DM6
M_A_DQ17 SA_DQ_16 M_A_DQS0 M_B_DQ16 SB_DQ_15 SB_DM_6 M_B_DM7 M_B_DQS[7..0]
AY44 AJ44 BC46 AK2 M_B_DQS[7..0] 20

A
M_A_DQ18 SA_DQ_17 SA_DQS_0 M_A_DQS1 M_B_DQ17 SB_DQ_16 SB_DM_7

B
BA40 AT44 BC44
M_A_DQ19 SA_DQ_18 SA_DQS_1 M_A_DQS2 M_B_DQ18 SB_DQ_17 M_B_DQS0
BD43 BA43 BG43 AL47
M_A_DQ20 SA_DQ_19 SA_DQS_2 M_A_DQS3 M_B_DQ19 SB_DQ_18 SB_DQS_0 M_B_DQS1
AV41 BC37 BF43 AV48
M_A_DQ21 SA_DQ_20 SA_DQS_3 M_A_DQS4 M_B_DQ20 SB_DQ_19 SB_DQS_1 M_B_DQS2
AY43 AW12 BE45 BG41
M_A_DQ22 SA_DQ_21 SA_DQS_4 M_A_DQS5 M_B_DQ21 SB_DQ_20 SB_DQS_2 M_B_DQS3
BB41 BC8 BC41 BG37
SA_DQ_22
MEMORY SA_DQS_5 M_A_DQS#[7..0] SB_DQ_21 SB_DQS_3

MEMORY
M_A_DQ23 BC40 AU8 M_A_DQS6 M_B_DQ22 BF40 BH9 M_B_DQS4
M_A_DQ24 SA_DQ_23 SA_DQS_6 M_A_DQS7 M_A_DQS#[7..0] 19 M_B_DQ23 SB_DQ_22 SB_DQS_4 M_B_DQS5
AY37 AM7 BF41 BB2
M_A_DQ25 SA_DQ_24 SA_DQS_7 M_A_DQS#0 M_B_DQ24 SB_DQ_23 SB_DQS_5 M_B_DQS6 M_B_DQS#[7..0]
BD38 AJ43 BG38 AU1 M_B_DQS#[7..0] 20
M_A_DQ26 SA_DQ_25 SA_DQS#_0 M_A_DQS#1 M_B_DQ25 SB_DQ_24 SB_DQS_6 M_B_DQS7
AV37 AT43 BF38 AN6
M_A_DQ27 SA_DQ_26 SA_DQS#_1 M_A_DQS#2 M_B_DQ26 SB_DQ_25 SB_DQS_7 M_B_DQS#0
AT36 BA44 BH35 AL46
M_A_DQ28 SA_DQ_27 SA_DQS#_2 M_A_DQS#3 M_B_DQ27 SB_DQ_26 SB_DQS#_0 M_B_DQS#1
AY38 BD37 BG35 AV47
M_A_DQ29 SA_DQ_28 SA_DQS#_3 M_A_DQS#4 M_B_DQ28 SB_DQ_27 SB_DQS#_1 M_B_DQS#2
BB38 AY12 BH40 BH41
M_A_DQ30 SA_DQ_29 SA_DQS#_4 M_A_DQS#5 M_B_DQ29 SB_DQ_28 SB_DQS#_2 M_B_DQS#3
AV36 BD8 BG39 BH37
M_A_DQ31 SA_DQ_30 SA_DQS#_5 M_A_DQS#6 M_B_DQ30 SB_DQ_29 SB_DQS#_3 M_B_DQS#4
AW36 AU9 BG34 BG9
M_A_DQ32 SA_DQ_31 SA_DQS#_6 M_A_DQS#7 M_A_A[14..0] M_B_DQ31 SB_DQ_30 SB_DQS#_4 M_B_DQS#5
BD13 AM8 M_A_A[14..0] 19 BH34 BC2
M_A_DQ33 SA_DQ_32 SA_DQS#_7 M_B_DQ32 SB_DQ_31 SB_DQS#_5 M_B_DQS#6
E AU11 BH14 AT2 E
M_A_DQ34 SA_DQ_33 M_A_A0 M_B_DQ33 SB_DQ_32 SB_DQS#_6 M_B_DQS#7 M_B_A[14..0]
BC11 BA21 BG12 AN5
SYSTEM

SA_DQ_34 SA_MA_0 SB_DQ_33 SB_DQS#_7 M_B_A[14..0] 20


M_A_DQ35 BA12 BC24 M_A_A1 M_B_DQ34 BH11
SA_DQ_35 SA_MA_1 SB_DQ_34

SYSTEM
M_A_DQ36 AU13 BG24 M_A_A2 M_B_DQ35 BG8 AV17 M_B_A0
M_A_DQ37 SA_DQ_36 SA_MA_2 M_A_A3 M_B_DQ36 SB_DQ_35 SB_MA_0 M_B_A1
AV13 BH24 BH12 BA25
M_A_DQ38 SA_DQ_37 SA_MA_3 M_A_A4 M_B_DQ37 SB_DQ_36 SB_MA_1 M_B_A2
BD12 BG25 BF11 BC25
M_A_DQ39 SA_DQ_38 SA_MA_4 M_A_A5 M_B_DQ38 SB_DQ_37 SB_MA_2 M_B_A3
BC12 BA24 BF8 AU25
M_A_DQ40 SA_DQ_39 SA_MA_5 M_A_A6 M_B_DQ39 SB_DQ_38 SB_MA_3 M_B_A4
BB9 BD24 BG7 AW25
M_A_DQ41 SA_DQ_40 SA_MA_6 M_A_A7 M_B_DQ40 SB_DQ_39 SB_MA_4 M_B_A5
BA9 BG27 BC5 BB28
M_A_DQ42 SA_DQ_41 SA_MA_7 M_A_A8 M_B_DQ41 SB_DQ_40 SB_MA_5 M_B_A6
AU10 BF25 BC6 AU28
M_A_DQ43 SA_DQ_42 SA_MA_8 M_A_A9 M_B_DQ42 SB_DQ_41 SB_MA_6 M_B_A7
AV9 AW24 AY3 AW28
M_A_DQ44 SA_DQ_43 SA_MA_9 M_A_A10 M_B_DQ43 SB_DQ_42 SB_MA_7 M_B_A8
BA11 BC21 AY1 AT33
M_A_DQ45 SA_DQ_44 SA_MA_10 M_A_A11 M_B_DQ44 SB_DQ_43 SB_MA_8 M_B_A9
BD9 BG26 BF6 BD33
M_A_DQ46 SA_DQ_45 SA_MA_11 M_A_A12 M_B_DQ45 SB_DQ_44 SB_MA_9 M_B_A10
AY8 BH26 BF5 BB16
SA_DQ_46 SA_MA_12 SB_DQ_45 SB_MA_10
DDR

M_A_DQ47 BA6 BH17 M_A_A13 M_B_DQ46 BA1 AW33 M_B_A11


M_A_DQ48 SA_DQ_47 SA_MA_13 M_A_A14 M_B_DQ47 SB_DQ_46 SB_MA_11 M_B_A12
AV5 AY25 BD3 AY33

DDR
M_A_DQ49 SA_DQ_48 SA_MA_14 M_B_DQ48 SB_DQ_47 SB_MA_12 M_B_A13
AV7 AV2 BH15
M_A_DQ50 SA_DQ_49 M_B_DQ49 SB_DQ_48 SB_MA_13 M_B_A14
AT9 AU3 AU33
M_A_DQ51 SA_DQ_50 M_B_DQ50 SB_DQ_49 SB_MA_14
AN8 AR3
M_A_DQ52 SA_DQ_51 M_B_DQ51 SB_DQ_50
AU5 AN2
D M_A_DQ53 AU6
SA_DQ_52 M_B_DQ52 AY2
SB_DQ_51 D
M_A_DQ54 SA_DQ_53 M_B_DQ53 SB_DQ_52
AT5 AV1
M_A_DQ55 SA_DQ_54 M_B_DQ54 SB_DQ_53
AN10 AP3
M_A_DQ56 SA_DQ_55 M_B_DQ55 SB_DQ_54
AM11 AR1
M_A_DQ57 SA_DQ_56 M_B_DQ56 SB_DQ_55
AM5 AL1
M_A_DQ58 SA_DQ_57 M_B_DQ57 SB_DQ_56
AJ9 AL2
M_A_DQ59 SA_DQ_58 M_B_DQ58 SB_DQ_57
AJ8 AJ1
M_A_DQ60 SA_DQ_59 M_B_DQ59 SB_DQ_58
AN12 AH1
M_A_DQ61 SA_DQ_60 M_B_DQ60 SB_DQ_59
AM13 AM2
M_A_DQ62 SA_DQ_61 M_B_DQ61 SB_DQ_60
AJ11 AM3
M_A_DQ63 SA_DQ_62 M_B_DQ62 SB_DQ_61
AJ12 AH3
SA_DQ_63 M_B_DQ63 SB_DQ_62
AJ3
Cantiga FBGA 1329P INTEL 6019B0383501 SB_DQ_63
Cantiga FBGA 1329P INTEL 6019B0383501

C C

B B

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
A A
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M)Rev
Document Number
C AX1
Cantiga DDR3(3/6)
Date: Wednesday, July 02, 2008 Sheet 14 of 45
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

13,16,19,20,41,43 1.5V

H 13,16,18,42 VCC_GMCH H
13,16,18,42 VCC_GMCH

U45F
42 VGFX_CORE
13,16,18,42 1.05VM AG34
VCC_1
AC34
U45G VCC_2
AB34
VCC_3
PLACE ON Cavity Capacitors

C142

C116

C137

C118
AA34 AM32
VCC_4 VCC_NCTF_1

C173
THE EDGE Y34 AL32
VCC_5 VCC_NCTF_2
W28 V34 AK32
VCC_AXG_NCTF_1 VCC_6 VCC_NCTF_3

C100
AP33 V28 + U34 AJ32
VCC_SM_1 VCC_AXG_NCTF_2 VCC_7 VCC_NCTF_4

C96

C105

C99

C97

C111

C107
AN33 W26 AM33 AH32
VCC_SM_2 VCC_AXG_NCTF_3 VCC_8 VCC_NCTF_5
BH32 V26 + AK33 AG32
VCC_SM_3 VCC_AXG_NCTF_4 VCC_9 VCC_NCTF_6

T100uF 6.3V 45m 20% 3528

10uF 6.3V 10% 0805 X5R

0.22uF 10V 10% 0603 X7R

0.22uF 10V 10% 0603 X7R

0.1uF 10V 10% 0402 X7R


BG32 W25 AJ33 AE32
VCC_SM_4 VCC_AXG_NCTF_5 VCC_10 VCC_NCTF_7
BF32 V25 AG33 AC32
VCC_SM_5 VCC_AXG_NCTF_6 VCC_11 VCC_NCTF_8
C138

C139

0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

0.47uF 16V 10% 0603 X7R

1uF 6.3V 10% 0402 X5R

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

T100uF 6.3V 45m 20% 3528


BD32 W24 AF33 AA32
VCC_SM_6 VCC_AXG_NCTF_7 VCC_12 VCC_NCTF_9

VCC NCTF
C145

BC32 V24 Y32


VCC_SM_7 VCC_AXG_NCTF_8 VCC_NCTF_10
C132

BB32 W23 AE33 W32


G VCC_SM_8 VCC_AXG_NCTF_9 VCC_13 VCC_NCTF_11 G
+ BA32 V23 AC33 U32
VCC_SM_9 VCC_AXG_NCTF_10 VCC_14 VCC_NCTF_12
AY32
VCC_SM_10 VCC_AXG_NCTF_11
AM21 308 mils from AA33
VCC_15 VCC_NCTF_13
AM30
AW32 AL21 the Edge Y33 AL30
VCC_SM_11 VCC_AXG_NCTF_12 VCC_16 VCC_NCTF_14
0.1uF 10V 10% 0402 X7R

T100uF 6.3V 45m 20% 3528

10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

AV32 AK21 W33 AK30


VCC_SM_12 VCC_AXG_NCTF_13 VCC_17 VCC_NCTF_15
AU32 W21 V33 AH30
VCC_SM_13 VCC_AXG_NCTF_14 VCC_18 VCC_NCTF_16
AT32 V21 U33 AG30
VCC_SM_14 VCC_AXG_NCTF_15 VCC_19 VCC_NCTF_17
AR32 U21 AH28 AF30
VCC_SM_15 VCC_AXG_NCTF_16 VCC_20 VCC_NCTF_18
AP32 AM20 AF28 AE30
VCC_SM_16 VCC_AXG_NCTF_17 VCC_21 VCC_NCTF_19
AN32 AK20 AC28 AC30
VCC_SM_17 VCC_AXG_NCTF_18 VCC_22 VCC_NCTF_20

VCC CORE
BH31 W20 AA28 AB30
VCC_SM_18 VCC_AXG_NCTF_19 VCC_23 VCC_NCTF_21
BG31 U20 AJ26 AA30
VCC_SM_19 VCC_AXG_NCTF_20 VCC_24 VCC_NCTF_22
BF31 AM19 AG26 Y30
VCC_SM_20 VCC_AXG_NCTF_21 VCC_25 VCC_NCTF_23

POWER
BG30 AL19 AE26 W30
VCC_SM_21 VCC_AXG_NCTF_22 VCC_26 VCC_NCTF_24
BH29 AK19 AC26 V30
VCC_SM_22 VCC_AXG_NCTF_23 VCC_27 VCC_NCTF_25
BG29
VCC_SM_23 VCC_AXG_NCTF_24
AJ19 370mils from Cavity Capacitors AH25
VCC_28 VCC_NCTF_26
U30
BF29 AH19 the Edge AG25 AL29
VCC_SM_24 VCC_AXG_NCTF_25 VCC_29 VCC_NCTF_27
BD29 AG19 AF25 AK29
VCC_SM_25 VCC_AXG_NCTF_26 VCC_30 VCC_NCTF_28
BC29 AF19 AG24 AJ29
VCC_SM_26 VCC_AXG_NCTF_27 VCC_31 VCC_NCTF_29
BB29 AE19 AJ23 AH29
VCC_SM_27 VCC_AXG_NCTF_28 VCC_32 VCC_NCTF_30
F BA29
VCC_SM_28 VCC_AXG_NCTF_29
AB19 AH23
VCC_33 VCC_NCTF_31
AG29 F
AY29 AA19 AF23 AE29
VCC SM

VCC_SM_29 VCC_AXG_NCTF_30 VCC_34 VCC_NCTF_32

POWER
AW29 Y19 AC29
VCC_SM_30 VCC_AXG_NCTF_31 VCC_NCTF_33

SHORT-0402-5MIL
R86
AV29 W19 T32 AA29
VCC_SM_31 VCC_AXG_NCTF_32 VCC_35 VCC_NCTF_34
AU29 V19 Y29
VCC_SM_32 VCC_AXG_NCTF_33 VCC_NCTF_35
AT29 U19 W29
VCC_SM_33 VCC_AXG_NCTF_34 VCC_NCTF_36
AR29 AM17 V29
VCC_SM_34 VCC_AXG_NCTF_35 VCC_NCTF_37
AP29 AK17 AL28
VCC_SM_35 VCC_AXG_NCTF_36 VCC_NCTF_38
AH17 AK28
VCC_AXG_NCTF_37 VCC_NCTF_39
BA36 AG17 AL26
VCC_SM_36/NC VCC_AXG_NCTF_38 VCC_NCTF_40
BB24 AF17 AK26
VCC_SM_37/NC VCC_AXG_NCTF_39 VCC_NCTF_41
BD16 AE17 AK25
VCC_SM_38/NC VCC_AXG_NCTF_40 VCC_NCTF_42
BB21 AC17 AK24
VCC_SM_39/NC VCC_AXG_NCTF_41 VCC_NCTF_43
AW16 AB17 AK23
VCC_SM_40/NC VCC_AXG_NCTF_42 VCC_NCTF_44
AW13 Y17
VCC_SM_41/NC VCC_AXG_NCTF_43
AT13 W17
VCC_SM_42/NC VCC_AXG_NCTF_44
VCC GFX NCTF

V17
VCC_AXG_NCTF_45
AM16
42 VGFX_CORE VCC_AXG_NCTF_46
AL16
VCC_AXG_NCTF_47
E AK16 E
VCC_AXG_NCTF_48 Cantiga FBGA 1329P INTEL 6019B0383501
AJ16
VCC_AXG_NCTF_49
Y26 AH16
VCC_AXG_1 VCC_AXG_NCTF_50
AE25 AG16
VCC_AXG_2 VCC_AXG_NCTF_51
AB25 AF16
VCC_AXG_3 VCC_AXG_NCTF_52
AA25 AE16
VCC_AXG_4 VCC_AXG_NCTF_53
AE24 AC16
VCC_AXG_5 VCC_AXG_NCTF_54
AC24 AB16
VCC_AXG_6 VCC_AXG_NCTF_55
AA24 AA16
VCC_AXG_7 VCC_AXG_NCTF_56
Y24 Y16
VCC_AXG_8 VCC_AXG_NCTF_57
AE23 W16
VCC_AXG_9 VCC_AXG_NCTF_58
AC23 V16
VCC_AXG_10 VCC_AXG_NCTF_59
AB23 U16
VCC_AXG_11 VCC_AXG_NCTF_60
AA23
VCC_AXG_12
AJ21
VCC_AXG_13
AG21
VCC_AXG_14
AE21
VCC_AXG_15
AC21
VCC_AXG_16
AA21
VCC_AXG_17
Y21
D AH20
VCC_AXG_18 D
VCC_AXG_19
AF20
VCC_AXG_20
AE20
VCC_AXG_21
AC20
VCC_AXG_22
AB20
VCC_AXG_23
AA20
VCC_AXG_24
T17
VCC_AXG_25
T16
VCC_AXG_26
AM15
VCC_AXG_27
AL15
VCC_AXG_28
AE15
VCC_AXG_29
AJ15
VCC_AXG_30
AH15
VCC_AXG_31
AG15
VCC GFX

VCC_AXG_32
AF15
VCC_AXG_33
AB15
VCC_AXG_34
AA15
VCC_AXG_35
Y15
VCC_AXG_36
V15
C VCC_AXG_37 C
U15 AV44
VCC_AXG_38 VCC_SM_LF1
AN14 BA37
VCC_AXG_39 VCC_SM_LF2
AM14 AM40
VCC_AXG_40 VCC_SM_LF3
VCC SM LF

U14 AV21
VCC_AXG_41 VCC_SM_LF4
T14 AY5
VCC_AXG_42 VCC_SM_LF5
AM10
VCC_SM_LF6
BB13
VCC_SM_LF7
0.1uF 10V 10% 0402 X7R

0.1uF 10V 10% 0402 X7R

0.22uF 10V 10% 0603 X7R

0.22uF 10V 10% 0603 X7R

0.47uF 16V 10% 0603 X7R

1uF 6.3V 10% 0402 X5R

1uF 6.3V 10% 0402 X5R


C85

C78

C72

C106

C153

C147

C163

AJ14
VCC_AXG_SENSE
AH14
VSS_AXG_SENSE

B Cantiga FBGA 1329P INTEL 6019B0383501 B

Inventec Corporation
66 Hou-Kang Street, Shih-Lin District, Taipei 111, Taiwan
A A
TEL:+886-2-2881-0721
Title

Size
S118D(Penryn+Cantiga+ICH9M)Rev
Document Number
C AX1
Cantiga Power(4/6)
Date: Wednesday, July 02, 2008 Sheet 15 of 45
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1

13,15,18,42 1.05VM
0.1uf caps in 1.5VDDM_xPLL
H H
need to be located as edge caps
within 200mils
30mil
L43
100ohm 25% 2A 0.1ohm 0603 (40mA) 10mil
1.05VM_DPLLA
0.1uF 10V 10% 0402 X7R
C488
+ C489
T100uF 6.3V 45m 20% 3528
8,9,12,13,18,21,24,38,42 1.05VS

L23
100ohm 25% 2A 0.1ohm 0603 (40mA) 10mil
1.05VM_DPLLB
R441
G G

C453

C458

C444
0.1uF 10V 10% 0402 X7R 100ohm 25% 2A 0.1ohm 0603 0-5%-1/8W-0805

C73

C81
2.2uF 10V 10% 0805 X5R

0.47uF 16V 10% 0603 X7R


C196 C186 0.1uF 10V 10% 0402 X7R
+ 20mil

4.7uF 10% 6.3V 0805 X5R

4.7uF 10% 6.3V 0805 X5R


T100uF 6.3V 45m 20% 3528 VCCS_TVDAC L10 C485 +
U45H

T100uF 6.3V 45m 20% 3528


0.022uF 16V 10% 0402 X7R U13
L41 C486 VTT_1
100ohm 25% 2A 0.1ohm 0603 (45mA) 10mil B27
VTT_2
T13
U12
VCCA_CRT_DAC_1 VTT_3
1.05VM_HPLL A26 T12
VCCA_CRT_DAC_2 VTT_4
U11
0.1uF 10V 10% 0402 X7R 1000pF 50V 10% 0402 X7R VTT_5
T11

CRT
C445 VTT_6
VCCS_TVDAC A25 U10
C450 C109 VCCA_DAC_BG VTT_7
T10
4.7uF 6.3V 10% 0603 X5R 0.022uF 16V 10% 0402 X7R C102 VTT_8
B25 U9
VSSA_DAC_BG VTT_9
T9
VTT_10
VTT_11
U8 PLACE ON
L40
(45mA) 10mil 1.05VM_DPLLA F47 T8 THE EDGE

VTT
100ohm 25% 2A 0.1ohm 0603 VCCA_DPLLA VTT_12
U7
VTT_13
1.05VM_MPLL 1.05VM_DPLLB L48 T7
VCCA_DPLLB VTT_14
F U6 F

PLL
0.1uF 10V 10% 0402 X7R VTT_15
1.05VM_HPLL AD1 T6
C441 VCCA_HPLL VTT_16
U5
C448 VTT_17
+ 1.05VM_MPLL AE1 T5
T226 20% 10V 3528 NRS226M10 VCCA_MPLL VTT_18
V3
VTT_19
U3
VTT_20
J48 V2

A PEG A LVDS
1.8V_TXLVDS VCCA_LVDS VTT_21
L45
100ohm 25% 2A 0.1ohm 0603 10mil C178 J47
VTT_22
U2
T2
1000pF 50V 10% 0402 X7R VSSA_LVDS VTT_23 13 1.05VM_AXD
1.05VM_PEGPLL V1
VTT_24
U1
0.1uF 10V 10% 0402 X7R 0-5%-1/10W-0603 VTT_25
C495 C490 R473 C492 AD48
30mil L42
9,21,22,24,27,36,43 1.5VS VCCA_PEG_BG
10uF 6.3V 10% 0805 X5R 0.1uF 10V 10% 0402 X7R 1uF 6.3V 10% 0402 X5R 1.05VM 13,15,18,42
C484 C483 100ohm 25% 2A 0.1ohm 0603
1.05VM_PEGPLL AA48
VCCA_PEG_PLL
0-5%-1/10W-0603
13,15,18,42 1.05VM R57 AR20 10uF 6.3V 10% 0805 X5R
VCCA_SM_1
E AP20 E
VCCA_SM_2
AN20

POWER
VCCA_SM_3

10uF 6.3V 10% 0805 X5R

C88

C89
4.7uF 10% 6.3V 0805 X5R

10uF 6.3V 10% 0805 X5R

C90

C91
1uF 6.3V 10% 0402 X5R
AR17
C95 VCCA_SM_4

A SM
+ AP17
9,21,22,24,27,36,43 1.5VS VCCA_SM_5 0.1uF 10V 10% 0402 X7R L8
L9 T100uF 6.3V 45m 20% 3528
AN17
VCCA_SM_6 30mil
100ohm 25% 2A 0.1ohm 0603 10mil AT16