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Analog & Mixed Signal Simulation

(NAND Gate in AMS Flow)

Schematic of NAND gate

1. VHDL Entry
We create the cellviews under “My_vhdl_designs” library
Creating a New cell View
1. In the CIW or Library manager, execute File – New – Cellview.
2. Set up the ―New File‖ window as follows:

3. Click on build database and create instance….

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4. A dialogue box will appear asking whether to create symbol for existing design. Click yes.

Automatically symbol for “myand” design will be generated.

5. Now open Library manager and check or edit the symbol (can check the behavioural code,
architecture is dataflow in the code):

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2. Schematic Entry – Inverter
In this section we will learn how to open new schematic window in the new “My_vhdl_designs”
library and build the inverter schematic design.
1. In the CIW or Library manager, execute File – New – Cellview.
2. Set up the ―New File‖ window as follows:

3. Create inverter design and place pins accordingly.

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4. Create symbol for the same inverter design :

5. Create test_banch (myinv_TB):

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6. Open ADE_L and setup for simulation.

After getting correct results, save state as Cellview instead of Directory.

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3. Schematic Entry – NAND
Creating a Schematic Cellview
In this section we will open a new schematic window under “My_vhdl_designs” library and
build the inverter schematic as shown in the figure at the start of this lab.
1. In the CIW or Library manager, execute File – New – Cellview.
2. Set up the ―New File‖ window as follows:

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4. Creating the Configuration View
In this section we will create a config view and with this config view we will run the simulation.
1. In the CIW or Library Manager, execute File – New – Cellview.
2. In the “New File‖ form, set the following:

3. Click OK in “New File” form. The “Hierarchy Editor” form opens with “New Configuration” form
in front of it.

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4. Click Use Template at the bottom of the New Configuration form and select AMS in the
cyclic field and click OK.

5. Change the Top Cell - View to schematic and remove the default entry from the Library List
field and Click OK in the New Configuration form.

6. The hierarchy editor displays the hierarchy for this design using table format.

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Note: - In the hierarchy window, if the View Found field for “myand” is not Dataflow, change to
dataflow by right click on View Found field for” myand” and choose Dataflow under Set Cell
View Dataflow.

Save the current configuration and Close the Hierarchy Editor window. Execute File – Close
Window.

7. From CIW, execute Tools – Library Manager

In the library Manager window, select the following


Library My_vhdl_designs
Cell Mynand

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Double click on config under View

The Schematic Editor and Hierarchy Editor window appears. Notice the window banner of
schematic also states Config: My_vhdl_designs Mynand config.

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5. Simulation of config View with AMS
Objective: To set up and run simulations on the Mynand design

In this section, we will run the simulation for Mynand and plot the Transient Analysis.
Starting the Simulation Environment

1. In the Mynand schematic window, execute Launch – ADE L


The Virtuoso Analog Design Environment (ADE) simulation window appears.
Choosing a Simulator
Set the environment to use the AMS tool, a high speed, highly accurate mixed signal
simulator.
1. In the simulation window (ADE), execute Setup— Simulator/Directory/Host.
2. In the Choosing Simulator form, set the Simulator field to AMS and click OK.

Setting Connect Rules


1. In the simulation window, execute Setup- Connect rules.
2. In the select connect rules window, set the Rules name field under Built-in and customized
rules to connectLib.Connrules_18V_full_fast.

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Setting the Model Libraries
(Because of some reasons, not setting the model libraries manually and instead loading them from
saved state)

Setup > Load state. Load Cellview instead of Directory. By doing so, all the required model
libraries will be added automatically.

Following is a small portion of entries in CDS.log file.

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Results :

(green and purple are signal a and b respectively, red output signal )

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