FA13842,13843,13844,13845 FA13842,Power

For Switching
CMOS IC
13843,Supply
13844,Control
13845

■ Description ■ Dimensions, mm
The FA1384X series are CMOS current mode control ICs for
off-line and DC-to-DC converters. Á SOP-8
These ICs can reduce start-up circuit loss and are optimum for
high efficiency power supplies because of the low power 8 5
dissipation achieved through changes in the CMOS fabrication
process.

6.0±0.2
3.9
These ICs can drive a power MOSFET directly.
The high-performance, compact power supply can be
designed with minimal external components .
1 4
4.9
■ Features

–0.05
+0.1
• CMOS process

1.7max
0.20
• Low-power dissipation
• Standby current 2µA (max.), start-up current 30µA (max.)
• Pulse-by-pulse current limiting

0~8°
• 5V bandgap reference 0.4±0.1 1.27±0.2
• UVLO (Undervoltage lockout) with hysteresis
• Maximum duty cycle FA13842, 13843: 96%
FA13844, 13845: 48%
• Pin-for-pin compatible with UC384X
Á DIP-8
Note: Pins are fully compatible, but characteristics are not. 8 5
When our ICs are applied to a power supply circuit
designed for other manufactures' 384X series, the
characteristics and safety features of the power supply

6.4
must be checked.

■ Types of FA1384X series 1 4

9.3
Type UVLO Maximum duty Package 1.5
Start threshold Stop threshold cycle

3.0min 4.5max
3.3
FA13842P 16.5V±1V 9V±1V 96% DIP
FA13842N SOP
+0.1
0.05
FA13843P 9.6V±1V 9V±1V 96% DIP 0.25 –
FA13843N SOP 7.62
2.54±0.25 0.46±0.1 0~15 5˚
FA13844P 16.5V±1V 9V±1V 48% DIP ˚ 0~1
FA13844N SOP
FA13845P 9.6V±1V 9V±1V 48% DIP
FA13845N SOP

1
FA13842, 13843, 13844, 13845

■ Block diagram

Á FA13842, 13843 Pin No. Symbol Function Description

1 COMP Compensating Error amplifier output, available
VCC 7
UVLO for loop compensation circuit
VCC 5V REF 8 VREF
30V 2 FB Feedback Inverting input of the error
ENB 2.5V
UVLO amplifier
OUTPUT 6 OUT 3 ISNS Current sensing Input voltage proportional to
ENB
inductor current
4 RT/CT Oscillator control Setting oscillation frequency
and maximum duty-cycle with
RT/CT 4 OSC 5 GND
ER AMP resistor RT and capacitor CT
FB 2
5 GND Ground Ground
2R
COMP 1 6 OUT Output Output for driving a power
1R 1V S Q
FF MOSFET
R QB
ISNS 3 7 VCC Power supply Power supply
5V Controlled block 8 VREF Reference voltage Reference voltage and
current source charging
capacitor C T through resistor
Á FA13844, 13845 RT

VCC 7
UVLO
VCC 5V REF 8 VREF
30V
ENB 2.5V
UVLO
OUTPUT 6 OUT
ENB

RT/CT 4 OSC 5 GND

ER AMP
FB 2 2R
COMP 1 1R 1V S Q TFFQ
FF CLK
R QB QB
ISNS 3
5V ControlIed block

■ Absolute maximum ratings (Ta=25˚C)

Item Symbol Test condition Rating Unit
Supply voltage VCC Low impedance source 28 V
Zener clamp (Icc<10mA) Self limiting V
Zener current IZ 10 mA
Output peak current IO Source current 400 mA
Sink current 1 A
FB/ISNS terminal input voltage VIN FB, ISNS –0.3 to 5.3 V
Error amplifier sink current I SINK 10 mA
Total power dissipation Pd at Ta < 50˚C DIP 800 mW
SOP 400
Thermal resistance Rθ j-a Junction-air DIP 125 ˚C/W
SOP 250
Junction temperature Tj 150 ˚C
Ambient temperature Ta –25 to 85 ˚C
Storage temperature Tstg –40 to 150 ˚C

2
 FA13842, 13843, 13844, 13845

■ Recommended operating conditions

Item Symbol Min. Max. Unit
Supply voltage VCC 10 25 V
Oscillation timing capacitor CT 0.47 10 nF
Oscillation timing resistor RT 2.0 100 kΩ
Oscillation frequency fOSC 10 500 kHz

■ Electrical characteristics (Vcc=15V, RT=10kΩ, CT=3.3nF, Ta=25˚C)

Reference voltage section
Item Symbol Test condition Min. Typ. Max. Unit
Reference voltage VREF Tj=25˚C, IL=1mA 4.75 5.00 5.25 V
Line regulation LINE Vcc=10 to 25V ±3 ±20 mV
Load current regulation LOAD IL=0 to 20mA ±3 ±25 mV
Temperature regulation VTC Ta=–25 to 85˚C ±0.3 mV/˚C
Output current at short-circuit IOS Tj=25˚C 60 mA

Oscillator section
Item Symbol Test condition Min. Typ. Max. Unit
Oscillation frequency fOSC Tj=25˚C 49 52 55 kHz
Ta=–25 to 85˚C 47 57 kHz
Voltage stability fdv Vcc=10 to 25V ±0.25 ±1 %
Temperature stability fdt Ta=–25 to 85˚C –0.07 %/˚C
Oscillation amplitude VOSC Tj=25˚C 1.6 V
Discharge current IDISCHG Tj=25˚C 8.4 mA

Error amplifier section

Item Symbol Test condition Min. Typ. Max. Unit
Input voltage VFB COMP=2.5V, Tj=25˚C 2.4 2.5 2.6 V
Input leak current IFB ±2 µA
Open-loop gain AV 65 72 dB
Unity gain bandwidth fT 0.7 1 MHz
Output source current ISOURCE FB=2.3V, COMP=0V –0.8 –1.0 mA
Output sink current ISINK FB=2.7V, COMP=1V 2 15 mA
Output voltage VH COMP FB=2.3V, RL=15kΩ to GND 4.0 4.5 V
VL COMP FB=2.7V, RL=15kΩ to VREF 80 500 mV

Current sensing section

Item Symbol Test condition Min. Typ. Max. Unit
Voltage gain AV IS Tj=25˚C 2.85 3 3.15 V/V
Maximum input signal VTH IS FB=0V 0.9 1.0 1.1 V
Input bias current IIS –1 –5 µA
Delay to output TPD Tj=25˚C, ISNS to OUT 150 300 ns

3
FA13842, 13843, 13844, 13845

Output section
Item Symbol Test condition Min. Typ. Max. Unit
High-level output VOH I source=–20mA 14.5 14.75 V
I source=–100mA 12 13.5 V
Low-level output VOL I sink=20mA 0.15 0.3 V
I sink=200mA 1.5 3 V
Rise time tr CL=1nF, Tj=25˚C 40 150 ns
Fall time tf CL=1nF, Tj=25˚C 20 150 ns

Under-voltage lockout section

Item Symbol Test condition Min. Typ. Max. Unit
Start threshold VTH ON FA13842, 13844 15.5 16.5 17.5 V
FA13843, 13845 8.6 9.6 10.6 V
Min. operating voltage VTH OFF 8 9 10 V
Hysteresis VHYS FA13842, 13844 7.5 V
FA13843, 13845 0.6 V

PWM section
Item Symbol Test condition Min. Typ. Max. Unit
Maximum duty cycle Dmax FA13842, 13843 94 96 98 %
FA13844, 13845 47 48 50 %
Minimum duty cycle Dmin FB=5V, COMP=Open 0 %

Overall device
Item Symbol Test condition Min. Typ. Max. Unit
Standby current I CCL FA13842, 13844 Vcc=14V 2 µA
FA13843, 13845 Vcc=7V 2 µA
Start-up current I CC ST Vcc=Start threshold 12 30 µA
Operating current I CC OP 3 5 mA
Zener voltage (Vcc) VZ Icc=5mA 28 30 34 V

4
 FA13842, 13843, 13844, 13845

■ Characteristic curves (Ta=25˚C)

Timing resistance vs. oscillation frequency Output dead time vs. oscillation frequency
FA13842, FA13843 FA13842, FA13843
100 100

VCC= 15V
2.2nF 470pF Ta= 25˚C

CT=10nF 470pF

Output dead time (%)

RT resistance (kΩ)

2.2nF

CT=10nF
10 10

VCC= 15V
Ta= 25˚C

1 1
1 10 100 1000 10 100 1000
Oscillation frequency (kHz) Oscillation frequency (kHz)

Timing resistance vs. oscillation frequency Output dead time vs. oscillation frequency
FA13844, FA13845 FA13844, FA13845
100 100
470pF VCC= 15V
2.2nF Ta= 25˚C
90

CT=10nF
Output dead time (%)

80
RT resistance (kΩ)

70 470pF
10 2.2nF
CT=10nF
60

50
VCC= 15V
Ta= 25˚C

40
1 10 100 1000
1 10 100 1000 Oscillation frequency (kHz)
Oscillation frequency (kHz)

RT/CT discharge current vs. temperature Output max. duty cycle vs. timing resistance
FA13842, FA13843
10 100
Output maximum duty cycle (%)

9.5 90
RT/CT discharge current (mA)

9 80

8.5 70

8
60

7.5 50

40
7
–50 0 50 100 150 1 2 5 10
Temperature (˚C) RT timing resistance (kΩ)

5
 FA13842, 13843, 13844, 13845

ISNS threshold voltage vs. COMP voltage COMP source current vs. COMP voltage

1200 0

VCC= 15V
1000 FB= 0V –200
OUT= off
ISNS threshold voltage (mV)

COMP source current (µA)

800 –400

600 –600

400 –800

200 –1000

0 –1200
0 1 2 3 4 5 0 1 2 3 4 5
COMP voltage (V) COMP voltage (V)

COMP to ISNS offset voltage vs. temperature COMP source current vs. temperature
2.5 –800
VCC= 15V
COMP= 0V
COMP to ISNS offset voltage (V)

2 –900
COMP source current (µA)

–1000
1.5

–1100
1

–1200

0.5
–1300

0
–50 0 50 100 150 –1400
–50 0 50 100 150
Temperature (˚C)
Temperature (˚C)

Error amp open loop voltage gain and phase vs. VREF short circuit current vs. temperature
frequency
100 0 80
VCC= 15V
80 VREF= 0V
70
VREF short circuit current (mA)
Open loop voltage gain (dB)

60 Phase
60
Phase ( ˚)

40
Gain 50
20

0 180 40

–20 30

–40
10 100 1.0k 10k 100k 1.0M 10M 20
Frequency (Hz) 0 50 100 150
Temperature (˚C)

6
 FA13842, 13843, 13844, 13845

VCC supply current vs. VCC supply voltage VCC startup current vs. VCC supply voltage
FA13842, FA13844
8
RT= 10kΩ 14
7 CT= 3.3nF Ta= 25˚C
OUT= No load
12

VCC startup current (µA)

6
VCC current (mA)

10
5
8
4

6
3

2 4
13842/44
13843/45

1 2

0 0
0 10 20 30 14 14.5 15 15.5 16 16.5 17
VCC voltage (V) VCC voltage (V)

Output waveform
Vcc=15V, OUT CL=1nF, Ta=25˚C Vcc=15V, OUT CL=2.2nF, Ta=25˚C

VCC= 15V VCC= 15V

OUT CL= 1nF OUT CL= 2.2nF
Ta= 25˚C Ta= 25˚C

2.50V 25.0ns 2.50V 50.0ns

7
FA13842, 13843, 13844, 13845

■ Description of each circuit Vcc Vin

1. Oscillator
The oscillation frequency is determined by timing resistance RT
and timing capacitor CT, which are connected to RT/CT
terminal. CT is charged to about 3V through RT from a 5V
VCC
reference, and discharged to about 1.4V by the built-in 7
VREF
discharge circuit. (See Fig. 1, 2, 3.) UVLO VCC 5V REF 8

MOSFET
Blanking pulses are generated in the IC during the CT ENB 2.5V
OUT
30V UVLO OUTPUT 6
discharge period. ENB

The output is fixed in the “low” state by these pulses, and a

fixed dead time is produced. See the characteristic curves on RT
RS
page 45 for the oscillation frequency, RT and CT.
In the case of FA13844/45, a flip-flop causes the output to be RT/CT 5 GND
4 OSC
blanked with every other cycle. Therefore, the switching CT ER AMP 2R
frequency of a power MOSFET is 1/2 of the oscillation FB 2
frequency determined by RT and CT . (See Fig. 3.) 1R 1V S Q
COMP 1 FF
R QB
3
ISNS
2. Error amplifier
Inverting input and output are connected to the FB terminal
and COMP terminal, respectively. A 2.5V reference is Fig. 1
connected internally to the non-inverting input.
The output voltage is offset by a diode VF voltage (=0.7V) and
divided by three. The divided voltage is connected to the input 3V
of the current sensing comparator.
CT

1.4V
3. Current sensing comparator and PWM latch
The “High” state of the OUT terminal begins at the time CT Set
starts charging. The OUT terminal turns to “Low” when the
peak inductor current reaches the threshold level controlled by
the error amplifier output (COMP terminal).
The inductor current is converted to a voltage by sensing COMP
ISENS
resistor RS inserted between GND and the source of a power
MOSFET. This voltage is monitored by the ISNS terminal. Reset

The peak current of inductor “Ipk” is expressed as follows:

Ipk=(Vcomp–0.7) / (3•RS) 0.7V VF OUT
Vcomp: a voltage on COMP terminal

The maximum value of the threshold level of the current Fig. 2 FA13842, 13843
sensing comparator is held to 1V. Therefore, the maximum
peak current “Ipk(max)” is as follows:
Ipk(max)=1.0V/RS
3V

CT
4. Undervoltage lockout (UVLO) 1.4V
In order to set the IC in the operation mode before the output
stage(OUT terminal) is enabled, two under-voltage lockout Set
comparators are incorporated to monitor the power supply
voltage (VCC) and reference voltage (VREF).
The threshold level of the VCC comparator is set at 16.5V/9V for
FA13842/44 and 9.6V/9V for FA13843/45. In the standby COMP
mode, in which the VCC is under ON threshold, the power ISENS
supply current is maintained at nearly 0 (zero). However, a
maximum current of 30µA is required to change from standby Reset
mode to operating mode .
The threshold level of the VREF comparator is set at about 3.2V/
OUT
2.0V.
A 30V zener diode is connected to VCC and GND to protect the
IC against overvoltages. Fig. 3 FA13844, 13845

8
 FA13842, 13843, 13844, 13845

DB T1
5. Output stage ~ +
An output stage of CMOS inverter composition is incorporated,
thereby making it possible to fully swing the gate voltage of a AC INPUT +
C1
power MOSFET to the VCC.
The output stage provides a source current of 400mA and a ~
sink current of 1A as the peak current capacity. (When VCC is
15V) R1
The output stage is held in the “Low” state in standby mode. D1

+
C2
6. Reference voltage 7
The 5.0V(±5%) bandgap reference(Tj=25˚C) is built-in.
It is possible to supply a current of about 10mA to an external FA13842 MOSFET
circuit in addition to supplying a charge current to the timing 6

capacitor of the oscillator. (See characteristic curve on page

46.) Rs
Connect a ceramic bypass capacitor of 0.1µF or higher to the
VREF terminal to stabilize this voltage. Fig. 4

Input:100V AC
4 C2=47µF
■ Design advice C2=22µF

Start-up time[sec]
3
1. Start-up circuit
A typical start-up circuit is shown in Fig. 4. 2
The AC INPUT voltage charges capacitor C2 and supplies C2=10µF
start-up current to the IC through start-up resistance R1. When 1
this voltage reaches the ON threshold voltage, the IC reverts to
0
the operation mode and electric power is supplied from the 0 200 400 600 800 1000 1200
bias winding of the transformer thereafter. Start-up resistance R1 (kΩ)
Using CMOS process, the start-up current is less than 30µA.
Fig. 5 Start-up time
When the start-up resistance is increased, the charging rate of
capacitor C2 decreases and start-up time increases. Select
the optimum values for R1 and C2.
The relation between the start-up resistance and start-up time R1
for the circuit indicated in Fig. 4 is shown in Fig. 5. D1 D2
Fig. 6 indicates a method to increase the start-up resistance to
reduce loss and shorten start-up time. The start-up time is + +
C2 C3
shortened by reducing the capacitance of C2. The bias current
7
is supplied from C3 after start-up.
FA13842
6
2. Synchronized operation with external signals
The circuit shown in Fig. 7 allows synchronized operation with
external signals. Fig. 6
Synchronized operation is started when the RT/CT terminal
voltage is raised to about 3V or higher. (Synchronized at
leading edge.)
The external synchronizing signal should be higher than the
free-run frequency. 8 REF
In the case of FA13844/45, the output frequency of the OUT
terminal is 1/2 that of the synchronizing signal frequency.
RT

Synchronized
4 OSC
CT
C4
+ 2R
R2
2
D3 ER AMP 1R

Fig. 7

9
FA13842, 13843, 13844, 13845

3. Latched shutdown DB T1
~ +
A typical circuit for latched shutdown is shown in Fig. 8.
The voltage of the OUT terminal is kept low if the voltage of the +
AC INPUT C1
COMP terminal is low. The voltage of the COMP terminal
must be set at 0.7V or less in the application temperature ~
range. (See characteristic curve on page 46 ”COMP to ISNS MOSFET
R1
offset voltage vs temperature”.) D1
The source current from the COMP terminal is less than about
+
1.3mA. C2

Use of a thyristor such as that shown in Fig. 9 is not effective

because the saturation voltage of the thyristor is higher than
7
0.7V. When a thyristor is used, increase the voltage of the FB
terminal to more than 3V as shown in Fig.10. In the case of a 8 REF
latched shutdown, it is necessary to supply a current larger
than the hold current of the thyristor structure circuit or of the 30V
thyristor. This current should be provided through a start-up
resistor from the AC input.
4 OSC

Latched shutdown with a thyristor using the COMP

+ 2R
terminal is not effective.
2
R4 ER AMP 1R
Latching signal Tr2 D4
1

Tr1 5

R3

Fig. 8

7 7

8 REF 8 REF

30V 30V

4 OSC 4 OSC
Latching signal

2R SCR2 2R
+ +
2 2
ER AMP 1R ER AMP 1R

Latching signal 1 R5 1
C5
5 5
SCR1

Fig. 9 Fig. 10

10
 FA13842, 13843, 13844, 13845

3-1 The method of detecting an overvoltage (detection DB T1 D6

~ +
on primary side)
+
A typical latched shutdown circuit to protect against AC INPUT + C7
C1
overvoltages detected on the primary side is shown in Fig. 11.
When the secondary voltage increases in the flyback circuit, ~
the voltage of the bias winding also increases in proportion.
R1
When this voltage increase is detected by zener diode ZD1, a D1 R9
latched shutdown is accomplished. As the secondary voltage +
is detected through a transformer, detection accuracy is low. R6 C2
7 ZD2

3-2 The method of detecting an overvoltage (detection FA13842 MOSFET

6
on secondary side) PC1
1
A typical latched shutdown circuit to protect against Rs
overvoltages detected on the secondary side is shown in
R4 R8
Fig. 12.
Tr2
The detected voltage accuracy is high compared to D5
PC1
overvoltage detection on the primary side. R7
Tr1
3-3 The method of detecting an overcurrent (detection C6
R3
of primary current) Fig. 12
A typical primary overcurrent detection circuit is shown in
Fig. 13.
DB T1
~ +
3-4 The method of detecting an overcurrent (detection +
AC INPUT
of secondary current) C1
A typical secondary overcurrent detection circuit is shown in ~
Fig. 14.
R1 D1
+
R6 C2
7
DB T1
~ + FA13842 MOSFET
6

AC INPUT + 1 3
C1 R12

~ D5
R4
R1 Rs
Tr2
R11
D1
Tr1 Tr3
+
R6 C2 R3 R10
7 C6 C8

ZD1 FA13842 MOSFET Fig. 13

6
1
Rs
DB T1 D6 R13
R4 ~ +
Tr2 D5 +
AC INPUT +
C1 C7 Tr4
Tr1
~
R3
C6 R1
Fig. 11 D1 R14

+
R6 C2 PC1
7
R15
FA13842 MOSFET
6
Tr5
1
Rs R16

R4 R8
Tr2
D5
R7 PC1
Tr1
R3
C6

Fig. 14

11
FA13842, 13843, 13844, 13845

4. Soft start
A soft-start circuit is shown in Fig. 15. 8 REF
An aproximate soft-start time is determined with the following
calculation. This soft-start time is defined as the time the ISNS
terminal threshold voltage increases from 0V to 1V.

tsoft-start [ms]=4.3•C9[µF] 4 OSC

5. Suppression of noise at the current sensing 1mA

+ 2R
terminal R17 2
As each cycle current value is monitored in the current mode D7 1MΩ ER AMP
1R
control, there is the possibility that a malfunction will occur D8
1
even with a relatively low noise level. Therefore, it is
C9 5
necessary to add a CR filter to reduce the level of noise at the
current sensing terminal. (See Fig. 16.) Fig. 15

6. ON/OFF circuit with an external signal

A typical ON/OFF circuit is shown in Fig. 17.
The output stage (OUT terminal) is enabled when the voltage DB T1
at the FB terminal is reduced to less than 2.0V and is disabled ~ +

when the FB terminal voltage increases to more than 3V. +

AC INPUT C1
Set the voltage of the FB terminal at a maximum of 5.3V in this
case.
~

MOSFET
6

FA13842 R18
3

C10 Rs

Fig. 16

8 REF

30V

4 OSC
R19

+ 2R
2
ER AMP
ON/OFF signal
Tr6 1R
1
5

Fig. 17

12
 FA13842, 13843, 13844, 13845

7. Feedback circuit T1 D6
7-1 A method that does not use an internal ER AMP
+ +
A method that does not use an internal ER AMP is shown in C1 C7
Fig. 18. Connect the FB terminal to GND and connect an
optocoupler to the COMP terminal of the ER AMP output for
MOSFET
feedback control.
It is possible to obtain a precise power supply output voltage, 1
R20
because the output voltage is monitored directly on the C11
PC2 2R R21
secondary side. 2 Rs PC2
+ R
R19
Be sure to connect the FB terminal to the GND in this case. 2.5V
There is the possibility of a malfunction occuring if the FB 3 +
R22
terminal is open.
R18 C12

7-2 A method using an internal ER AMP C10

R23
A method using an internal ER AMP is shown in Fig. 19.
In the flyback circuit, the bias winding voltages of the
transformer are proportional to the secondary winding voltage. Fig. 18
Therefore, VCC is approximately proportional to the DC output
voltage on the secondary side.
VCC is divided by resistors and monitored at the FB terminal to
D6
control the output voltage. T1
This feedback circuit consists of a minimal number of external +
C1 +
components. However, regulation of the DC output voltage is C7
poor because the output voltage is not monitored directly. R1
D1
+
8. Slope compensation R26 C2
It is well known that a current mode converter that controls C13
1
peak current can oscillate irregularly when the inductor current R25
2R
is continuous and the duty cycle is greater than 50%. 2
+
This irregular oscillation is called subharmonic oscillation. R
2.5V
The period of subharmonic oscillation is equal to the integral R24
number of the switching periods. 3 +
MOSFET
This phenomenon is shown in Fig. 20.
Lu indicates the positive slope of the inductor current. The R18
slope is determined by the input voltage and the primary
C10 Rs
inductance value of the transformer. –Ld indicates the
negative slope, which is determined by the rate of energy
discharge to the secondary side. Fig.19

Fig. 20 shows the inductor current waveform when T reveals

the oscillation period and Is reveals the control signal of the
peak inductor current. TON and TOFF vary even when having the
Is
same T, Is, Lu and –Ld.
Lu
If it is assumed in Fig. 21 that the inductor current varies ∆ iL at -Ld
t0, the variation ∆ iL’ of the inductor current at t1 is larger than
∆ iL at t0. Thereafter, this inductor current variation gradually TON TOFF

increases, and as a result, subharmonic oscillation occurs.

T T T T

Fig. 20

Diverge

∆iL ∆iL´

to t1

Fig. 21

13
FA13842, 13843, 13844, 13845

Fig. 22 illustrates a case when the inductor current variation

Converge
∆ iL’ at t1 is smaller than ∆ iL at t0. In this case, inductor current
variations gradually converges and the inductor current ∆iL ∆iL´
becomes stable.
It is necessary to apply slope compensation to the control
signals in order to prevent such subharmonic oscillations when to t1
the inductor current is continuous and the duty cycle is greater
than 50%.
Fig. 22
The waveform of the inductor current when slope
compensation is applied is shown in Fig. 23.
Slope compensation adds the negative slope of inclination
–Kc to the control signal of the inductor peak current. Is
∆ iL’ shows the variation of the inductor current at t1 when -Kc
slope compensation is not applied, and ∆ iL’ s shows the
variation of the inductor current at t1 when slope compensation ∆iL´
is applied. ∆iL Lu
Thus, ∆ iL’ can be changed by –Kc, and ∆ IL’ s becomes smaller -Ld
when –Kc is large. It is necessary to apply slope ∆iL´s
compensation to satisfy the equation ∆ iL ≥ ∆ iL’s, that is,
I –Kc I ≥ I –1/2 Ld I as the condition which achieves stable Compensated

operation. Ton
Typical circuits are shown in Fig. 24 and 25.
T
to t1

Fig. 23

Vcc Vin

VCC
7 VREF
UVLO

MOSFET
Vcc 5VREF 8
RT
ENB 2.5V OUT
Tr7 30V UVLO OUTPUT 6
ENB
R18
R27 CT
Rs
Output C10
RT/CT 5 GND
R25 4
ER AMP 2R OSC
FB
2
R24 R26 C13 1R 1V
1 S Q
COMP FF
R QB
3
ISNS

Fig. 24

Vcc Vin

VCC
7 VREF
UVLO
MOSFET

Vcc 5VREF 8
RT
30V ENB 2.5V OUT
Tr7 UVLO OUTPUT 6
ENB
R18
R27 CT
Rs
Output C10
RT/CT 5 GND
R25 4
ER AMP 2R OSC
FB
2
R24 R26 C13 1R 1V
1 S Q
COMP FF
R QB
3
ISNS

Fig. 25

14
 FA13842, 13843, 13844, 13845

■ Application circuit

YG902C L1
DB T1 D6 4700µF 2 3.3µH
~ + 16V
0~4A
C1 + C16 R27
AC80~264V 0.022µF 100kΩ
400V/220µF
+ + C17 +
~ C7 C18
D9 1000µF
ERA22-10

R1 GND
560kΩ C15
470pF
MOSFET
2SK2101 D10 R28 R20
ERA22-10 1kΩ 1.2kΩ
R29 R32 R21
R30 Rs PC2 2.2kΩ 10kΩ
4.7kΩ 0.33Ω
33Ω
R22 560Ω
R31 D11
100Ω C12
ERA91-02 0.1µF
C2 IC
FA13842 VR1
RT VCC 22µF + 5k
7 VREF
8.2kΩ UVLO VCC 5VREF 8
30V D1
ENB 2.5V OUT
UVLO OUTPUT ERA91-02
6
ENB

COMP
1
GND
RT/CT 5
4 OSC
CT C11 2R
2200pF 1000pF FB 2
1R 1V S Q
PC2 R19 FF
1kΩ ISNS3 R QB

R18 C14
C10 1kΩ
100pF 0.1µF

Parts tolerances characteristics are not defined in the circuit design

sample shown above. When designing an actual circuit for a
product, you must determine parts tolerances and characteristics for
safe and economical operation.

15