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PHYSICAL DESIGN 1

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PHYSICAL DESIGN

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PHYSICAL DESIGN 3

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PHYSICAL DESIGN 4

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confidential and proprietary (“Confidential Information”).
 Confidential Information includes, but is not limited to, the following:
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PHYSICAL DESIGN 5

Course Information

Course Code: TENGVLSIPDIC2001


Course Name: ENG T200 VLSI Physical Design Basics
Document Number: VLSI_PD_Basics_1.0
Version Number: 1.0

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PHYSICAL DESIGN 6

Course content
• Physical Design Overall Flow
• Design terminology
• Data Preparation
• Floor Plan
– IO Planning
• Power Plan
• Placement
• Clock Tree Synthesis
• Routing
• RC Extraction
• Block Level Implementation flow
• Signoff Checks
• ECO

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Physical Design Flow
PHYSICAL DESIGN 8
Physical Design Overall Flow

Load libraries Extract parasitics


No (DSPF/ RSPF/ SPEF/
Is Floor Plan OK
? SDF) and post-
Load Netlist/ route netlist
Constraints Yes

Carry out post-


Carry out Standard route STA
Initialise Floor plan
Cells Placement

Are
Carry out Block Carry out Clock No timings/
Placement Tree Synthesis load
met?
Carry out IO Yes
Planning & No Are clock
Placement constrain Export routed GDS
ts met?

Carry out Power Yes


planning A B
Carry out Routing

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PHYSICAL DESIGN 9

Flow Contd..

A B

Carry out post-


route optimization/
Carry out DRC/
correction Carry out LVS check
Antenna check

Carry out
incremental routing Is the Is the
No design design No
DRC LVS
Extract parasitics clean? clean?
and export netlist Yes Yes

Carry out post- Export full GDS for


route STA tapeout

Are Apply layout


Apply corrections
No timings/ corrections
load
met? Yes

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Design Terminology
PHYSICAL DESIGN 11
Design terminology
Corner Cell

IO Cell (IO Pad)

Bond Pad or Bonding Area


IO Power Ring

Core Power Ring

Hard Macro (RAM/ ROM/


PLL/ Analog
Block)
Core Area

Scribe Line

Total Die Size


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PHYSICAL DESIGN 12
Placement & Routing Terminology:
Track, Grid, Pitch and Spacing
Via Routing Segment (wire)

Line-to-Via Via-to-Via Line-to-


Line

• Track:
• Is a line on the grid which the router follows when creating wires.
• Grid:
• A matrix of intersecting tracks that the Placer and the Router use to Place and Route a design.
• Pitch:
• Should be minimum Line-to-Via distance
• Spacing (S): This is the edge to edge distance between two adjacent geometries on the same layer.

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PHYSICAL DESIGN 13

Placement Grid
• It’s the grid which is used by the placer as a reference for
cells placement
• The grid is a multiple of Metal - 1 pitch in vertical
direction and Metal - 2 pitch in the horizontal direction
• This indirectly indicates that cell height will be a multiple
of Metal - 1 pitch and width will be a multiple of Metal - 2
pitch

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PHYSICAL DESIGN 14

Routing Grid
• It is the grid which is used by the router as a reference for
routing
• This grid will be defined by the foundry
• The smallest unit of the routing grid is the Manufacturing
Grid
• Routing grid is a multiple of Manufacturing Grid
• Routing Grid will be different for different metal layers
because of the different widths of the metal layers
• In case of “Off Grid” routing, the router will follow the
manufacturing grid

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PHYSICAL DESIGN 15

Design objects
• Standard Cells

– Core cells – and, or, inverter, buffer, adder, subtractor, multiplier, multiplexers, delay cells

– Physical only cells – standard fillers, decap fillers, tap cells, switch cells

– Sequential cells – flops (scan and non-scan), latches

• IO Cells

– Signal IO – CMOS IO cells

– Power IO – VDD_core, VSS_core, VDD_io, cut cells, analog power cells

– Special IO – serdes, USB IO, PCIE IO, Memory IO, HDMI IO etc.

• Memories – sometimes called hard macros

• Soft IPs

– IPs for whom RTL is available

• Hard IPs

– IPs for whom only LEF and LIB are available (sometimes even GDS is available, but rarely)

– Available as a black box

– Example: PLL, ADC, DAC, any other analog blocks

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Data Preparation
PHYSICAL DESIGN 17

Data Preparation

• We need some Input files to start activity of physical design.

• Typical Inputs needed are:


From Frontend Team From Foundry/Vendor
 LEFs
 Verilog Net list
 GDS
 Pin pad file
 Runsets - DRC/ LVS/ Antenna
 Clock Details
 Timing Constraints File  Technology Files
 Critical Path Details  Design Rules from Foundry
 Data Flow Diagram  Packaging Rules from Foundry
 Block and Core Power
 Synopsys (.lib, .db) files
Consumption
• For Standard Cells, IO Cells,
Special Cells and ALL the other
Hard Macros used in the design
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PHYSICAL DESIGN 18

Initial Checks on libraries


• Incoming Library check

– Libraries used in the flow:

• LEF - abstract view

• LIB - timing view

• GDS - detailed cell view

• CDL - spice definition of cells (transistor level view)

• ALF - timing view in Ambit format for use in PKS flow

• gds2.map - GDS map file for exporting GDS from SE

– Independent physical verification of GDS to be carried out (DRC/ LVS)

– Independent validation of LEFs and LIBs to be carried out

• LEF - LIB consistency check for all cells

– Check whether the tech LEF is corresponding to the process to which the design is targeted

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PHYSICAL DESIGN 19

Incoming Files/ Information


• Set of files/ info to be received from the Front-end design group

– Netlist

– Constraints file - system level constraints

– Data Flow diagram, expected aspect ratio, die size

– Pin-pad table - as Excel sheet/ text table (including power pads)

– Clock constraints - max skew, max and min insertion delay, no. of clock domains, clock start points
(whether port level or internally generated)

– Scan Chain details - no. of scan chains, scan chain start and end points, whether re-ordering is OK
or not, whether boundary scan present or not, BSCAN cell instance names etc.

– Activity file (similar to VCD file)

– Reports - timing report, power estimation report, area report

– Other - Any timing critical nets, any positionally critical nets, any buffers already present on the
clock path (like global buffers etc.)

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PHYSICAL DESIGN 20
Verilog Netlist - example
A module D ( Q, QN, DIN, clk );
A Y input DIN;
G Y I
B input clk;
output Q;
output QN;

D nor G1 ( .Y(y1), .A(DIN), .B(clk) );


DIN A A not I1 ( .Y(DIN_n), .A(DIN) );
Y Y
B G1 B G3
Q nor G2 ( .Y(y2), .A(clk), .B(DIN_n) );
nor G3 ( .Y(Q), .A(y1), .B(QN) );
nor G4 ( .Y(QN), .A(Q), .B(y2) );
clk endmodule
A Y A Y QN module DFF ( Q, QN, D, clk );
I1 B G2 B G4 input D;
A Y input clk;
output Q;
output QN;

D D1 ( .DIN(DIN), .clk(clk), .Q(q1),


D DIN Q q1 DIN Q Q .QN() );
D D2 ( .DIN(q1), .clk(clk), .Q(Q),
D1 D2 .QN(QN) );
endmodule
clk clk
clk QN
DFF

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PHYSICAL DESIGN 21
Preparation
• Some preparatory steps:
– Die Size calculation
– Total Power estimation
– Power plan calculations:
• Power ring width
• Power strap width
• No. of vertical and horizontal straps
• Strap - to - strap spacing

– Prepare IO Constraints file


– Prepare clock tree constraints and command files
– Prepare placer config file
– Prepare router config file
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Floor Plan
PHYSICAL DESIGN 23

Flow Initialization
LEFs for standard cells, IO cells
Import LEF and all the hard macros and
other objects used in the design

No Version mismatch, Rules or


Resolve issues OK? keywords not understood by SE
(antenna check constructs) etc.
Yes
LIBs for standard cells, IO cells
Import LIB and all the hard macros and
other objects used in the design

No LEF-LIB consistency, negative


Resolve issues OK? rise/ fall time issues, timing arcs
not defined etc., incorrect older
version
Yes
Verilog stub files for standard
Import netlist and stub files cells, IO cells and all the hard
macros and other objects used
in the design
No
Resolve issues OK? Stub files not having defn. of all
cells, some port mismatches,
Yes unable to create the cds_vbin
directory etc.
Initialization completed…save database
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PHYSICAL DESIGN 24

Floor Plan

Specify die size, aspect ratio,


Initialize floor IO to core spacing, die origin,
plan row spacing (generally
abutting)
Carry out block Place hard macros used in the
placement design manually - based on
data flow diagram
Review block Review is done by Front end
placement design group against the data
flow diagram
Is Usually this step involves a lot
No
placement of iterations but the designer
OK? should freeze the floor plan
Yes before proceeding with the
flow
Start IO Here the flow varies
Placement depending upon whether the
IOs are in-line or staggered
or the design is block level
(not fullchip)

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PHYSICAL DESIGN 25

Floor Plan
 Floor plan involves decision on,
 Die size estimation
 pin/pad location
 hard macro placement
 placement and routing blockage
 location and area of the soft macros and its pin locations
 number of power pads and its location.

Always remember………..
 FP is the critical part in PD
 High quality FP ensures accurate circuit timing & performance
 Poor FP results in timing failure, routing congestion, larger power,
larger area, huge IR drop and SI issues

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PHYSICAL DESIGN 26

Hard Macro Placement


 Flyline analysis should be done while placing the
macros
 Orientation of these macros forms an important part of
floorplanning

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PHYSICAL DESIGN 27

Hard Macro Placement


• Avoid spreading standard cells in several areas and creating
small placement traps, with many pockets and isolated regions
between the macros that can trap a standard cell and limit the
routing access
• A physical design engineer must focus on having homogeneous
standard cell area with aligned macros

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PHYSICAL DESIGN 28
Block Halo Calculations
Block Halo Block Halo

Hard Hard
Macro Macro

Width of each track = max. width of the metal + max. spacing

No.of tracks = No.of signals * 2/n .


(where 'n' is the number of the preferred
routing layers
available for macros assuming 50 % of
utilization of
routing resources in each preferred
direction)

Blockhalo width = No.of tracks * Width of each track.

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PHYSICAL DESIGN 29

Pin/Pad Placement
 While fixing the location of the pin or pad always consider
the surrounding environment with which the block or chip
is interacting. This avoids routing congestion and also
benefits in effective circuit timing
 Provide sufficient number of power/ground pads on each
side of the chip for effective power distribution. In
deciding the number of power/ground pads, Power report
and IR-drop in the design should also be considered

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PHYSICAL DESIGN 30

IO Placement - in-line IO pads


IOC file is the IO constraints
Load the IOC file
file. The format is specific to
SE
Check whether Power pads and Corner pads
all pads including are not present in the netlist.
power pads and Hence, they have to be added
corner pads have to the design through a
been placed separate DEF file
Bond pad Two things are to be reviewed. Pad
Review IO order is to be reviewed against the pin-
placement pad table received from front-end
design group. IO pad spacing is to be
reviewed against the IO spacing rules.
No
Is
placeme Also, check that the bond pad of each
Driver and other nt OK? IO pad is towards the outer side.
logic
Yes
IO placement should be frozen before
proceeding with the flow.
Place IO fillers
Pad opening Ensure that IO fillers are placed on all
Start power the four sides of the die
planning

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PHYSICAL DESIGN 31

IO Placement - Staggered IO pads


At this point, only the driver
Load the IOC file
pads are placed and bind
pads are placed later through
some script. The same
Check whether condition as in-line pads
all pads including applies to the Power pads and
power pads and Corner pads in Staggered
corner pads have arrangement
been placed
Three things are to be reviewed. Pad
Review IO order is to be reviewed against the pin-
placement pad table received from front-end
design group. IO pad spacing is to be
reviewed against the IO spacing rules.
Outer Bond pad No
Is Inner and Outer pads should alternate
placeme in the IO ring.
nt OK?
Yes IO placement should be frozen before
Inner Inner
proceeding with the flow.

Place IO fillers Ensure that IO fillers are placed on all


the four sides of the die
Driver Cell Start power
planning
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PHYSICAL DESIGN 32

In-line pad pitch vs Stagger pad pitch

Pad Pitch

Inner Pad

Effective Pad Pitch


Outer Pad

Stagger Pad Pitch

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PHYSICAL DESIGN 33

Blockage Creation
 Create standard cell placement blockage at the corner of the macro because this
part is more prone to routing congestion.
 Also create standard cell placement blockage in long thin channel between
macros

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PHYSICAL DESIGN 34

Floorplan Tips
 In hierarchical design, Cluster based implementation enables to place the
standard cells of the given module in predefined region
 Analog block are more susceptible to noise and signal routes going over such
block cause signal integrity issues, routing blockages on all layers are to be
defined for analog blocks
 Time and efforts that are put in floorplanning save iterations and make design
cycle faster

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PHYSICAL DESIGN 35

Floorplan Tips Contd.


• For placing block-level pins,
 First determine the correct layer for the pins
 Spread out the pins to reduce congestion.
 Avoid placing pins in corners where routing access is limited
 Use multiple pin layers for less congestion
 Never place cells within the perimeter of hard macros.

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PHYSICAL DESIGN 36

Floorplan Tips Contd.


 To keep from blocking access to signal pins, avoid placing cells under
power straps unless the straps are on metal layers higher than metal2
 Use density constraints or placement-blockage arrays to reduce congestion
 Avoid creating any blockage that increases congestion.
 Also group small blocks into one larger block
 It is easier to floorplan with same-sized blocks. Try to work with midsized
blocks. A design partitioned in six to 12 roughly equivalent-sized blocks
constitutes a reasonable candidate for floorplanning
 Depending on the package design, you usually want to start the floorplan
with I/Os at the periphery

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PHYSICAL DESIGN 37

Floorplan Tips Contd.


 Consider parts of the design that are not typical standard cells:
 memories
 analog circuitry (PLLs)
 logic that works with a double-speed clock
 blocks that require a different voltage
 exceptionally large blocks
 unusual design-specific instances (flash)

 place these elements first to ensure that their special needs are accommodated
 If two or more large blocks or other features that make a reasonable floorplan
impossible, you may have to increase the die size or rearrange I/Os
 If any of the large blocks are soft IP, repartitioning that block into smaller pieces
 Arrange rest of the blocks in the remaining space based on their I/Os and power
consumption
 Avoid placing blocks that consume lot of power near center

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PHYSICAL DESIGN 38

Floorplan Checks
 Memory Overlapping
 Die size and Utilisation numbers.
 Blockage Creation specially in channel,Corner and Routing blockage if any.
 Pin/Pad Placement and Correct Layer of Pin

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IO Planning
PHYSICAL DESIGN 40

IO Planning

• A robust power distribution network, which may include


power pads, power rings, coupling caps, bond pads, and
wire bonds, is essential to ensure reliable operation of
circuits in the IC, ideally without sacrificing performance
of the IC

• This poses a serious problem for the design of the power


distribution network.

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PHYSICAL DESIGN 41

IO Planning
• On-chip power demand is met through external power sources (e.g., power and
ground).
• These external power sources are connected to internal power rings, to deliver
the desired power.
• Power pad structures, also located around the periphery of the IC, serve to
connect the external power supplies to the on-chip power rings as well as to
connect the external power supplies to functional circuitry within a core of the IC

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PHYSICAL DESIGN 42

IO Planning
• IO Pins come as inputs. They are not under the control of PD Engineer.
• The macro placement depends on the IO.
• IO planning depends on the following parameters:
o Width
o Pitch
o Layers of the pad
o Height of the pad
o Corner pads
o Orientation of the pad

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PHYSICAL DESIGN 43

Types of Pads
• Signal pads
• Power pads
• ESD pads
• CUP pads

 Power pads, as well as (IO) signal pads, serve as interface points between the
external world and vulnerable on-chip circuitry, power pads typically employ
electrostatic discharge (ESD) structures.

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PHYSICAL DESIGN 44

Types of Power Pads


• VDD, VSS, VDE/VDIO
• VDE/VDIO - provides power supply to interface.
• Typically, VDE/VDIO have high voltages compared to VDD.
• Ex: If VDD=1V, VSS=0V, VDE=2V/3V

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PHYSICAL DESIGN 45

Power Requirement planning


• To decide the number of pads on each side depending on the power requirement:
o Suppose the calculated power requirement is 0.8W, it can be approximated to
1W.
o If 1 Pad can carry 10mW, then 100 pads are required .

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PHYSICAL DESIGN 46

Electro Static Discharge


• ESD is a transient discharge of static charge that arises from either human handling or
a machine contact.

• Although ESD is the result of a static potential in a charged object, the energy
dissipated and damages made are mainly due to the current flowing through ICs
during discharge.

• Most ESD damages are thermally initiated in the form of device /interconnect burn-out
or oxide break-down. The basic phenomenon of ESD is that is a large amount of heat
is generated in a localized volume significantly faster than it can be removed, leading
to a temperature in excess of the materials’ safe operating limits.

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PHYSICAL DESIGN 47

Electro Static Discharge


• ESD Damages:
o pn-junction may melt.
o Gate oxide may have void formation.
o Metal interconnects & Vias may melt or vaporization, leading to shorts or opens.
o Gate-oxide breakdown.

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PHYSICAL DESIGN 48

Electro Static Discharge


• Principle Sources of ESD in ICs:
o Test and Handling Systems
 Equipment can accumulate static charge due to improper grounding. The charge
is transmitted through ICs when it is picked up for placement in test sockets.
o ICs remain charged until they come into contact with a grounded surface (large
metal plates /test sockets). Charge is discharged through the pins of ICs. Large
currents in the internal interconnects can result in high voltage inside the devices
which can cause damage to thin dielectrics and insulators.

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PHYSICAL DESIGN 49

ESD Protection Devices

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PHYSICAL DESIGN 50

ESD Protection Devices


• Two main types of diodes : n+/p-well diodes and p+/n-well diodes. p+/n-well
diodes have a pn-junction between the n-well and p-substrate whereas there is
no isolation between the diode and the p-substrate in n+/p-well diodes.
• When forward-biased, diodes can sustain a large current with a small device
dimension.
• Diodes are widely used for ESD protection at radio frequencies due to the small
junction capacitance, which has a less impact on the bandwidth of RF circuits.

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PHYSICAL DESIGN 51

Simultaneously Switching Outputs


• If a number of outputs were to switch simultaneously from logic-high to logic-low,
the charge will be stored in the I/O load capacitances to flow into the device.
• This sudden flow of current exits the device through internal inductances onto the
board ground, causing a voltage to develop.
• This results in a voltage difference between the device and the board ground,
momentarily developing a low voltage signal on the I/O above the ground level.
This is known as "ground bounce".
• The bounce effect can cause an output-low to be seen as a high by other devices
on the board.

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PHYSICAL DESIGN 52

Simultaneously Switching Outputs


• SSO problems may be reduced or completely avoided by including SSOs as a
design parameter from the early stages of system design:
• Identify potential SSOs and spread them around the package
• Place a power pad after every 3 output pads(SSOs).

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PHYSICAL DESIGN 53

CUP pads
 Circuit under pad or Board over active circuitry (BOAC).
 CUP I/O is the I/O with the bonding pad over the I/O body itself. The pad pin is
located close to the center of the I/O body for easier routing, signal integrity, and
space saving purposes.
 Using the CUP I/O can substantially reduce the die size since the bonding pad does
not take any extra space in addition to the I/O body itself.
 Similar to the bonding pad structures of non CUP wire bond I/O, CUP I/O also
comes with the staggered bonding pad approach and linear bonding pad approach.
 Extra care needs to be exercised while implementing this technology so as to ensure
that the circuit under the bond pad does not suffer any mechanical stress which
could be fatal to the chips operation.

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PHYSICAL DESIGN 54

Staggered Bond style


 Inner and outer pads are for staggered bonding. These bonding pads are not
embedded in the driving buffers because of the size difference.
 Users should attach the appropriate bonding pads to the I/O driving buffers
with the PR boundary aligned with each other at origin (0, 0).
 These bonding pads are placed in the repeated sequence of inner and outer
pads. The pattern is repeated until all the bonding pads are placed.

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PHYSICAL DESIGN 55

In-line I/O pad


 In this pads are placed in a line. In These bonding pads are not embedded in the
driving buffers because of the size difference.
 Users should attach the appropriate bonding pads to the I/O driving buffers with
the PnR boundary aligned with each other at origin (0, 0).

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PHYSICAL DESIGN 56

Comparison of Staggered I/O & In-Line I/O CUP pad

• A) Staggered I/O pad • B) In-Line I/O pad

Bond pad

Driver
logic

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Power Plan
PHYSICAL DESIGN 58

Power Planning
• This step involves placement of:
– Core power ring
– Vertical and Horizontal power straps in the core
– Standard cells power hook up
– Block power hook up
– IO power hook up
This step is preferably done manually by the engineer

• Power dissipation figure is first estimated through a tool or through calculations


• Total power comprises of Static power, Dynamic Power and Short Circuit power
• Based on this, the power ring width, power strap width, no. of vertical and horizontal straps etc.
are calculated

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PHYSICAL DESIGN 59

Power Calculations - Basics

t
Ne
t

W  Width of the net


L  Length of the net
t  Thickness of the net
 this is foundry dependant and is predefined
Rsh (or Rsquare)  Sheet resistance of the net

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PHYSICAL DESIGN 60

Power Planning - Basics


The resistance of the net is given as:
L
R = ρ ×
A
L
R = ρ ×
t×W
ρ L
R = ×
t W
L
R = R sh × where, - - - (1)
W
ρ
R sh = ohms - - - - - - - - - - (2)
t

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PHYSICAL DESIGN 61

Power Planning - Core Ring


Let,
J → mA/ µ
→ be the current density for the metal layers on which power planning is to be done
Pchip → mW
→ be the total power consumptio n of the chip
→ this is the sum of static power and dynamic power...ar rived at using power analysis tools

Pchip = Vdd × I chip where,


I chip is the current flowing in the power net
Pchip
I chip =
V dd
I chip
Now, J =
W
Pchip
∴ J =
W × V dd
Pchip
∴W =
ring
J × V dd
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PHYSICAL DESIGN 62

Power Planning - No. of power pads

Now,
I chip = J × Wring
Let,
i pad = mA, maximum current carrying capacity of a
power pad (say, pvdi)
n = the minimum number of power pads required
in a design
I chip
∴n =
i pad

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PHYSICAL DESIGN 63

Power Planning - Strap spacing


d

Cell1

2d

Cell2

d
Let,
d  Width of the power pin of the cell - later connected through
followpins. These form the horizontal power straps
On abutting two rows, as above, the width of the strap becomes
"2d” microns
Let,
J  current density of the metal layer on which followpins is to be done

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PHYSICAL DESIGN 64

Power Planning - Strap spacing


• Vertical strap spacing is controlled by the maximum
allowable IR drop for a technology - this value is
specified by the foundry

Cell1
Crossover vias

Cell2 Vertical Power Strap

Can be modeled as

Rsection
V1 V2

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PHYSICAL DESIGN 65
Power Planning - Strap spacing
• Current flowing through a strap will be
istrap = J × 2d --- (1)

• Let Vmax be the maximum allowable IR drop for the technology being used
• From the model of the section,

V1 − V2 < Vmax
istrap × Rsec tion < Vmax
• Now,

L --- (2)
Rsec tion = Rsh ×
2d
• Substituting (1) into the above equation
L
istrap × Rsh × < Vmax
2d

L
J × 2d × Rsh × < Vmax
2d
V
L < max --- Spacing between two
J × Rsh vertical straps

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN

Power Planning - Strap Width Calculations


• Total core area = Wcore × Hcore
• Spacing between two consecutive vertical straps =Lµ
• Let number of vertical straps = Nv
Wcore
∴ Nv =
L
• Since the followpins are also horizontal straps, the number of extra horizontal straps required could be
calculated as follows:
Vertical Strap Spacing =L
Horizontal Strap Spacing =2×L
• Let number of horizontal straps H core = Nh
∴ Nh =
2× L
• Now, due to these Nv and Nh the die gets divided into regions. Assuming that the cell placement is uniform,
the power supply network over the die also has to be uniform
Wring
∴ Wstrap =
Nv × Nh

66
Copyright © 2013-2014, Infosys Limited
PHYSICAL DESIGN 67

Initialization: Power Calculations


Ring Width

Total gate count of the design = Tg ( 2 input NAND gate equivalents)


Frequency of operation = f MHz
Power consumption of 2 i/p NAND gate = Pg
Percentage of devices switching at a given time = S%

Power for the core Pc = Tg * Pg * f * S watts

Operating voltage = V volts


Current requirement by the Core Ic = ( Pc / V ) mA
Current Density of the metal = J mA/ sq microns

Estimated core power ring width, Wc = ( Ic / J )

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 68
Initialization: Power Calculations
Strap Width

Resistance per sq.um of metal1 = R Ω/ sq microns


Width of metal1 strap in standard cell = Wsm
Metal1 current density = Cd
Max. allowable IR drop = Vd ( approx. 1% of typical voltage
)
Width of metal1 straps, Wm = 2 * Wsm
Max. current drawn by the wire, Im = Cd * Wm
Max. Vertical strap spacing X = Vd /( R * Im )
Max. Horizontal strap spacing Y = 2* X
Core size = W *H

Power strap width (P/G) = 2 * ( X / W ) * ( Y / H ) * Wc


where Wc is the core power ring width

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Power Synthesis 69
System Architecture data Start building Power Flow
• Involvement of: flow diagram Diagram document
• Software architect
• System architect
• Physical design architect Review with Power Architect
Understand power
• Check for: partitioning requirement
• Presence of Ips with different Is flow as per
voltage specifications power states?
• These result into separate Decide on Voltage islands
voltage islands and/ or power domains Yes
• Analyze different system
Export UPF
building blocks and bucket IPs/ module grouping into
them into similar range of each power partition
duty cycle Each voltage island shall be a
• These result into power separate ring around the
gated domains running on Cross check against data block
same voltage flow diagram
• Take care that power domain Place level shifters, isolation
grouping does not result into too buffers for signals as per UPF
many partitions Is grouping Yes
causing data
flow issues? Place AON buffers as per
• Logical checks: UPF
• Make sure that level shifters Done for
are connected to signals Identify power control
signals – these should be in each
crossing from low voltage to Place power switches and power
high voltage domain and vice always ON partition add rings and stripes domain
versa
• Make sure that extra level
Review power management Is EM, IR drop,
shifters are not used
states and generate list of DRC, LVS OK?
• Physical checks:
AON signals, level shifter
• Level shifters connected
requirement, isolation cell
to two voltages
requirement, retention
• VDD-VSS connection of Export power structure DEF
strategy
each domain is correct
and physically clean

Copyright © 2013-2014, Infosys Limited PHYSICAL DESIGN


69
PHYSICAL DESIGN 70

Power Plan Carry out the power plan


Place the core power ring and
vertical and horizontal power straps.
Check whether all blocks
are hooked up, all core Hook up the blocks and core power
power pads are hooked pads to the rings and the straps.
up and followpins is
completed Blocks: Have as many hook ups as
possible
Carry out EM and IR drop Core power pads should be properly
analysis on power mesh hooked up to the power rings.
There should be no jogs when
hooking up the power pads or blocks.
Is design EMIR
clean? Standard Cells power hook up is
called “followpins”.

Run DRC and LVS on the


Three things to be reviewed here.
power planned design • There should be as many hook ups
to the hard macros as possible
• Via generate rules are properly
No used by the tool. Vias generated are
Check and apply corrections Is design DRC & as per the rules.
to the power plan LVS clean? • No jogs should be present in the
hook up (as far as possible)
Yes
Floor Plan completed…save database
Copyright © 2013-2014, Infosys Limited
PHYSICAL DESIGN 71

Check points
• Check for the following points in the layout:
– Block placement should be uniformly distributed so that power consumption is
uniformly distributed over the die

• This prevents the die from having hot-spots

– Block placement should be aesthetically good - wherever possible symmetry


should be observed

– Ensure that IO cells placement is following the IO spacing rules and any other rule
that the foundry/ packaging foundry places on it

– Ensure that there are no jogs in the power hook-ups

• Jogs introduce vias…more vias mean more contact resistance which in turn mean
more drop on that net

– Understand how the tools orders the pads when it places the IOs automatically
(whether bottom to top and left to right or other method) and check the IO
constraints file accordingly

– Ensure that the design is DRC and LVS clean

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PHYSICAL DESIGN 72

Check points
– Avoid having rows in the narrow channels between two blocks

• Put blockage between these narrow channels during standard cells placement

• Remove the blockage during clock tree synthesis so that, if the blocks are
synchronous (SRAMs) tool can put buffers close to the block

– Try to get a good contiguous chunk of area for standard cells placement

– Have vertical and horizontal power straps running close to block edges so that
hook up wire is short

– If power ring width is > 25 microns, split it into two power rings

• In such cases add shorting links between the two rings of same type (keeping in
mind the slotting rules)

Shorting links

VDD power rings of 20


microns each (total
40 microns) Slots

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PHYSICAL DESIGN 73
Sample IR Drop maps

• IR drop map is typically like a bull’s eye becoming


increasingly red towards the center
– More intense for wire-bond designs

• Make sure that post-powerplan IT drop is clean


Source: http://www.synopsys.com.cn/information/snug/2007-2008-collection/synopsys-power-gating-design-methodology-based-on-smic-90nm-process
Copyright © 2013-2014, Infosys Limited 7
3
Placement
PHYSICAL DESIGN 75

Standard Cells Placement


• Standard Cells Placement should take the following into consideration:
– Whether design is timing critical - timing constraints are available to carry out “timing-driven” placement

• design should not have any combinational feedback loops

• all false paths must have been declared in constraints file

• all multi-cycle paths must have been declared in constraints file

– Whether design has scan chains - following information should be available to carry out scan chain optimization

• No. of scan chains

• Scan chain start and end points

• Whether it is OK to optimize the scan chain (reorder or not?)

– Whether design has boundary scan

– Whether cell placement under vertical power straps is OK

– Whether any specific cap filler cells would be added later

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 76

Pre-placement checks
• Ensure the following before starting placement:
– Disable IO/ pin placement variables since IO placement is already completed

– Set the variable which will prevent placer from touching the already placed instances

– Ensure that all the constraints are translated from TRF format to GCF format (check
PEARL log file for details of translation run)

– If any local congestion is to be controlled, set the corresponding variable

– If placement is to be done in “timing-driven” mode, set the corresponding variable

– If design has boundary scan, set the corresponding variable

– If the design has scan inserted into it, set the corresponding variables

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 77
Placement flow
Tool can employ buffer In case of placer, the designer
addition, deletion, gate Prepare placement prepares a config file where
resizing (up-sizing and config file based on variables can be set as per design
down-sizing) to optimize the design criteria criteria.
logic – can be done
manually as well In the config file the designer
Carry out Standard Cells should enable timing analysis so
Even the buffers to be used/ placement that the tool can write out a timing
not to be used can be report.
specified in the config file
If the placement is “timing-driven”
then the timing constraints are
No Are timings required to be passed in SDC
OK ? format. Tool internally converts the
Synopsys constraints file (obtained
Yes from write_script command) into
Carry out
internal format.
optimization
Other things that should The designer should check whether
be checked: all the constraints got translated
• cut ratio (weighted) into GCF format.
Placement completed…
• No. of buffers added save database
• Wire length in H and V Log file is used for review purpose.
direction It indicates if there was any
• Cells are not placed in problem during TRF to GCF
blockages translation
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PHYSICAL DESIGN 78

Placement Constraints
• We have to guide the tool by giving the constraints so that
proper placement can be done
• Module Constraints Type
– The entire design size is initially calculated during design import,
and each module size is calculated.
– The size of the modules are determined by either the core
utilization or the core width and height specifications.
– The imported design modules can have one of the following
constraint types:
1. Fence

2. Region

3. Guide

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PHYSICAL DESIGN 79

Fence
• This is a hard constraint in the
core design area.

• The physical outline of a fence


module is rigid, and the design for
the module is self contained within
the rigid outline.

• Only child instances must be


contained within the partition
physical outline; non-child blocks
or modules that do not belong to
the partition are excluded, and
should not be pre-placed within
another partition.

• This restriction is a hard restriction


for third party back-end tools
where the placement file for a
partition does not match the
partition netlist.

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PHYSICAL DESIGN 80

Region
• This constraint is the
same as a fence
constraint except that
instances from other
modules can be placed
within its physical
outline by placement.
• A module guide is
changed to a status of
Region when
preplaced in the core
design area.

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PHYSICAL DESIGN 81

Guide
• The module is
preplaced in the core
design area.
• A module guide
represents the logical
module structure of the
netlist.
• The purpose of a
module guide is to guide
placement to place the
cells of the module in
the vicinity of the guide’s
location.

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PHYSICAL DESIGN 82

Scan chain reordering


• Scan chains are created due to testing the silicon (DFT).

• In scan chains all flops are connected in such a way that it can make one or multiple chains
where data can be shifted in or out of these flops while testing the chip.

•Since these chains are for test, it does not matter what sequence is followed while connecting
these flops in chain.

•This means that you can always reorder them while implementing if it helps. It makes sense to
reorder flops in the chain such that flops placed close to each other are placed closer in chain and
hence reducing wire length and congestion.

• PnR tools can reorder flops once the initial placement of cells is available.

• Tool need to know the flops in chain and trace them to know what it can reorder.

•You can specify this to the tool through scandef file available from synthesis.

• You can also specify this through other formats which are supported by different tools.

•Alternatively you can also tell the tool about scanin and scanout ports and tool will automatically
trace the scan chains.

Copyright © 2013-2014, Infosys Limited


Scan chain reordering PHYSICAL DESIGN 83

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PHYSICAL DESIGN 84

High Fanout Synthesis


High fanout synthesis is to create buffer tree for nets with very high
fanout (usually more than 50). Synthesis tool might have done high
fanout synthesis based on fanout already which might not make sense
anymore due to change in placement. Hence tool will first remove
buffers from high fanout nets and then do high fanout synthesis
(HFNS).
High fanout synthesis is a simple buffer tree made based on fanout and
placement of cells connected to the high fanout net.
Some of the settings available with tools that effect HFNS:
1. Fanout limit: This is a number which specifies that all nets with
fanout more than this limit will be treated for HFNS.
2. Congestion or timing effort: Usually congestion and timing effort
given to placement optimization command will effect HFNS
algorithm to be affected or tweaked.

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PHYSICAL DESIGN 85

High Fanout Synthesis

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PHYSICAL DESIGN 86

Various types of cells used during PnR


 Well Tap cells
 End cap cells
 Tie High & Tie Low cells
 Decoupling cells

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PHYSICAL DESIGN 87

Well Tap cells


 Well taps are physical-only filler cells that are required by some technology
libraries to limit resistance between power or ground connections to wells of the
substrate.
 Well-tap cells are placed in a preplaced status, so future placement commands
do not move them.
 Add well taps after the floorplan is fixed and hard blocks are placed, but before
placing standard cells.

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PHYSICAL DESIGN 88

Latch up scenario

N-well tap P-well tap

Cross section of parasitic Equivalent ckt


transistors in Bulk CMOS

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PHYSICAL DESIGN 89

End cap cells


 End-cap cells are preplaced physical-only cells that are required to meet certain
design rules & it is only for base layer of a transistor.
 They are placed at the ends of the site rows, and are used in some technologies
for power distribution. End-cap cells are placed in a preplaced status, so future
placement commands do not move them.
 Add end-cap cells to the design before any other standard cells are placed, but
after hard blocks are placed in the floor plan.

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PHYSICAL DESIGN 90

Graphical representation of end cap


cells

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PHYSICAL DESIGN 91

Tie High & Tie Low cells


 In PnR there are some unused cells called spare cells used for ECO purpose.
 The spare cells that you need to insert in your design will come from the top level
designer. But if not then you can insert spare cells equal to 2% of your total
design cells. And regarding to the spare cell list, you can include the cells as per
the max number of the types used in your design.

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 92

 The library does not have well or substrate ties inside the
cells. You are required to tie the NWELLS to Vdd and the
substrate to Vss before place-and-route using the Tie-high
& Tie low cells.
 Tie-high and Tie-Low cells are used when you want to
connect the gate of transistor to either power or ground. In
deep sub micron processes, if we directly connect the gate
to power/ground the transistor might be turned on/off due
to power or ground bounce.
 The suggestion from foundry is to use tie cells for this
purpose. These cells are part of standard-cell library and
are mapped by synthesis tools

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PHYSICAL DESIGN 93

Arrangement of Tie high & Tie low cells : 1

Power
rails

Spare cell which is to be tied to vss through tie-low cell.

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PHYSICAL DESIGN 94
Arrangement of Tie high & Tie low cells : 2

Power
rails

Actual cell which is to be connected to


vdd through tie high cell
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PHYSICAL DESIGN 95

 The interesting part is the "placement" and "fanout" of these cells.


1) Need to ensure that fan out of these cells is one
2) Placement of tie-cells - Tie cells must be placed close to the cells which they
drive.
 suppose there is some logic that connects some input pin of say nand gate to
VSS or VDD, if we connect the input pin of that nand gate directly to vss or vdd
supply, there is chance of getting damaged the nand gate due to noise or logic
goes wrong by noise trigger and some times due to power instability gate may
be damaged so by using TIE-high and TIE-low cells to the nand gate we are
providing protection to the nand gate.

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 96

Decoupling cells
 Adding decoupling capacitance to a design can help maintain a stable voltage
between power and ground when signal nets switch.
 This can reduce IR drop for power nets and limit bouncing on ground nets.

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PHYSICAL DESIGN 97

dcap implementation-1
Standard
rows

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PHYSICAL DESIGN 98

dcap implementation-2

Power stripes

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PHYSICAL DESIGN 99

Check points
• The following should also be checked after the placement is completed

– Whether all cells placed

– Cell placement should not overlap

– Cells should not be placed in areas that are blocked either as blockages or keep-outs

– Cells should not have been placed in empty areas

– Cell Density is under control

• There are no hot spots created anywhere

• If created, these should be explained

– DRCs should be under control (< 50-75 shorts)

– No. of over-capacity Gcells is less than 5% (if greater, the design will not be routable)

– Whether all boundary scan cells are placed close to the corresponding Ios

– All placement blockages are honored

– Registers are not placed within the channels formed by memories

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 100
Placement: Pre-wire Keepout Requirements
Cells are placed under Cells are not placed under
vertical stripes vertical stripes

Without With
Prewire Keepout option Prewire Keepout option
Pre-placement RUF = 70% Pre-placement RUF = 70%
Post-placement RUF = 69.84% Post-placement RUF = 74.24 %
Copyright © 2013-2014, Infosys Limited
Clock Tree Synthesis
PHYSICAL DESIGN 102

Clock Tree Synthesis


• Clock tree synthesis should take into account the following:

– How many clocks are present in the design

– The following information for each clock should be obtained from the front-end design engineer

• Max. allowable skew

• Max. insertion delay

• Min insertion delay

– The max transition time information should be obtained from the library or front-end design engineer

– Whether any clock is gated

– Whether there are gates along the clock paths

– Whether any buffers in the clock path should be preserved

– Whether any pins are to be excluded from the leaf pins

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 103

Typical real-life clock structure

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 104

CTS flow
All the design criteria should be
Prepare CTS constraints covered by way of constraints to be
file based on design applied on the CTS tool.
criteria
Points to be observed are:
Carry out clock tree and • Insertion delay constraint should
physical tree synthesis be met
• Clock skew must be minimum
on Placed database • Transition time constraint must
be met
• The components to be preserved
Are should have been preserved after
No CTS
constraints
• Only specified buffers were used
met ? by the CTS tool
Yes • No. of buffers added should be
Carry out re-
minimum
structuring • All the physical trees (for high-
fanout nets) should also have been
synthesized eg. preset, reset etc.
• Blockages or placement
CTS completed… constraints that were passed to the
save database placer should also have been
passed to CTS tool
• Post-CTS routability

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 105

Check Points
• The following should be checked after CTS is completed
– There are no overlaps during buffer/ inverter placement
– All clock report should not indicate any violation
– The exported DEF reflects the inserted buffers and their
corresponding nets
– If the buffer/ inverter to be used was specified as a constraint then the
clock structure should not indicate any other type of buffer
– The components specified under “preserved_components” are really
preserved
– If CTS was used for meeting the load violation (max_transition
violation) after routing then all the max_transition time constraints
should have been met
– CTS tool should have followed all the placement constraints (if they
were also passed to the CTS tool)

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Routing
PHYSICAL DESIGN 107

Routing
• Basically consists of two steps
– Global routing - here, only the routing resources are assigned to the routing end points
– Final/ Detailed routing - here, nets are physically routed

• Following points should be checked before starting this step


– Routability - the number of over-capacity GCells should be less than 5% for the design to be routable.
This information is present in the QPlace log file and CTS initial placement log file
– Clock tree synthesis is completed
– IO fillers are already placed
– All the pads are facing such that their pad opening are towards the inside of the die
– Manufacturing grid is specified
– Antenna correction rule to be employed is specified vis-à-vis that followed by the foundry

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 108

Routing
• Points continued…
– All blockages are removed unless they are really required

– Power pins of all the blocks are hooked up to power straps

– All power pads are hooked up to the core power rings

– All standard cells power pins are hooked up to the power mesh

– All timings up to routing steps have been met

• Designer should take into account the following points


– Whether routing is to be carried out “timing driven”

– Whether any timing critical nets have been specified by the front end designer

– Whether any positionally critical nets have been specified by the front end designer

– Whether any nets are to be routed using non-default rules

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 109

Routing flow
The order for routing could Wroute variables can be passed to
be: Prepare routing the tool through a config file
1) Clock nets configuration file based
2) Timing Critical nets on design criteria All the design considerations can
3) Positionally critical nets be set on router through variables
4) Other nets
Carry out global and
final routing on CTS The following considerations are to
Check whether design is be checked:
routable before even database • timing driven or not
starting routing • timing critical nets - can be
separately routed
• clock nets - can be separately
Yes Are there routed
violations? • positionally critical nets - can be
separately routed
No • antenna correction rule - should
be the same as the one followed by
Carry out search-and- the foundry
repair • manufacturing grid should have
been specified as per the DRC deck
and Design Rule document
• post route optimization can be
Routing completed… carried out
save database
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PHYSICAL DESIGN 110

Routing Goal

• This stage involves routing of nets connecting different


standard cells through different metal layers.

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PHYSICAL DESIGN 111

Routing Flow
Placement & CTS

Global Routing

Track Assignment

Detailed Routing

Search & Repair


(Optimization)
Design for Manufacturing
(DFM)

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PHYSICAL DESIGN 112

Global Routing
• Guide the detailed router in large design

• May perform quick initial detail routing

• Also used in floorplanning and placement

What does Global Router do ?

• Global routing maps general pathways through the design for each unrouted net (signal nets and clock
nets)

• The global router uses a two-dimensional array of global routing cells to model the demand and
capacity of global routing.

• Assigns nets to the global routing cells through which they pass. For each global routing cell, the routing
capacity is calculated according to the blockages, pins, and routing tracks inside the cell.

• Calculates the demand for wire tracks in each global routing cell and reports the overflows, which are
the number of wire tracks.

• Attempts to find out the shortest path through the global routing cell but does not make actual
connections or assign net to specific tracks within cells.

• Detailed router uses the global routing paths as a routing plan.

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 113

Detail routing
• Connect all pins in each net

• Must understand most or all design rules

• May use a compactor to optimize result

• Necessary in all applications

What does Detail Router do ?

• Router follows the global routing plan and lays down actual wires that connect the pins to their
corresponding nets.

• Detail route is concerned with fixing all the DRC violations after track Assignment. The detail
router does not work on the whole chip at the same time like Track Assignment

• Instead it works by rerouting within the confines of a small area called an “SBox”. It traverses
the whole design box by box until the routing pass is complete. The router takes two passes
through the chip using the same size Sbox.

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PHYSICAL DESIGN 114

Search and Repair


• Detailed router creates short and spacing violations rather than
leave unconnected nets.
• The router runs search-and-repair routing during detailed routing.
During search and repair, it locates shorts and spacing violations
and reroutes the affected area to eliminate as many of the violations
as possible.
• The primary goal of detailed routing is to complete all of the required
interconnect without leaving shorts or spacing violations
• Router also runs post route optimization as part of detailed routing.
During post route optimization it runs more rigorous search and
repair steps.
• Detailed routing stops automatically if it can not make further
progress on routing the design.

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 115

Grid-Based Routing System:


• Metal traces (routes) are built
along, and centered around
routing tracks
• Each metal layer has its own
tracks and preferred routing
direction:
– M1: Horizontal
– M2: Vertical, etc…
• The tracks and preferred
routing directions are defined
in a "unitTile" cell in the
standard cell library

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PHYSICAL DESIGN 116

What is in Routing Stage ?


Design with routed power nets and Technology file with
unrouted clock trees design rule definitions

Set Routing Options

Route Clock Nets

Route Signal Nets


Perform PostRoute
Optimization
Perform DFM Optimization

Verify Design Rule

Copyright © 2013-2014, Infosys Limited


PHYSICAL DESIGN 117

• During routing stage we do routing for

- Clock nets

- Signal nets

• Clock routing should be done before the signal routing.

• For tight control over clock timing, run global and detailed routing on clock nets before routing other
nets.

• Fix the locations of the nets during detailed routing and unfix them during post-route optimization.

• Power Rings are made in top two metal layers because they are wider metals and have less resistance.

• For Clock Routing two metal layers just below the Power route layers are used.

• For Full Chip Top two metal layers are used for Full Chip routing and just below two layers are used for
block Power Planning. (For a 10 metal layer process , M10 & M9 should be used for top level and M8 &
M7 should be used for Block Level and M5 & M6 should be used for Clock Routing.)

• All metal layers below clock routing and above Metal1 are used for Signal Routing. (M1 is used for Std.
Cell Pin routing.)

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PHYSICAL DESIGN 118

Clock Routing
• Moreover, as the technology is shrinking and utilization target number is
increasing, more number of nets has to be packed in lesser area. Thus at
congested places in the design, the nets have to detour to avoid shorts and
spacing violations.

• To avoid detouring in the clock, nets are given maximum weight and are
routed before the signal nets. Otherwise the nets may get detoured as shown
in the Figure –

Detoured clock net

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PHYSICAL DESIGN 119

Different net topologies


• it is necessary to decide an optimal wire routing rule for the clock
nets so that clock power consumption, net delays, routing
resources, crosstalk, EM and buffer delays are less.
• The width and spacing define each topology. Different net
topologies followed in the clock tree synthesis are
- Single width single space
- Single width double space
- Single width triple space NDR
- Double width double space
- Net with shielding
• Since the default behavior for routing is Single Width Single
Spacing, other topologies except Single Width Single Spacing are
called Non Default Rule (NDR).

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PHYSICAL DESIGN 120
Single width single space net topology
(SWSS)

• In SWSS, the width and spacing of net are equal to the


minimum spacing between two adjacent metal wires.

• Due to lesser spacing, it has more coupling capacitance


and thus crosstalk impact is more.

• It also increases the overall net capacitance and thus


increases the net delays.

• For each metal wire routing, it requires 3 tracks.

Results:
• Less Congestion
• More Clock Buffers
• More power consumption
• More prone to EM and noise

Copyright © 2013-2014, Infosys Limited


Single width double space net topology PHYSICAL DESIGN 121

(SWDS)
• In SWDS, clock net is of single width and the spacing
between clock nets is doubled.

• Due to increasing spacing coupling capacitance will


decreases. Hence, noise is reduced as compared to
SWSS topology.

• But In this topology clock routing area increases because


number of tracks used for routing is increases.

• For each metal wire routing it requires 5 tracks.

Results:
• Congestion will increase due to the double spacing requirement
• Clock nets are still prone to EM
• The noise is reduced because the increased spacing decreases the coupling capacitance
• since the ground capacitance per unit length still remains the same as in SWSS, thus the
noise reduction is not huge.
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Single width triple space net topology PHYSICAL DESIGN 122

(SWTS)
• In SWTS, clock net is again of single
width and the spacing becomes three
time the width of clock nets.

• The coupling capacitance becomes


least in this case.

• Hence, the noise effect on clock tree


decreases but congestion in clock tree
increases as number of tracks
consumed is maximum in this topology.

Results:
• Congestion further increases due to the extra spacing.
• Clock nets are still prone to EM.
• With SWTS we are able to achieve significant noise reduction
as the coupling capacitance is very much reduced since there is
triple spacing between wires.
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PHYSICAL DESIGN 123
Double width double space net topology
(DWDS)
• In DWDS, the width and spacing are
doubled.
• As we widen the interconnects, resistance
decreases and ground capacitance
increases.
• Here the resulting routing congestion would
be reduced with respect to SWTS.
Results:
• on routing the clock using DWDS, we end up with a reduced buffer count, but slight increase in power
due to higher drive strengths (this is because net capacitances are larger due to increase in area of
wires)
• The congestion is slightly less than that seen in SWDS
• Though the spacing is same as in SWDS, yet noise is much less due to increased ground capacitance
arising from double width of wires
• This also results in the wires being far less prone to EM failure (due to wider metal width)
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PHYSICAL DESIGN 124

Net with shielding topology


• In this topology the clock is routed with single
width and is shielded with power/ground signal on
both the sides of the wire as shown in figure.

• It makes the clock signals immune from the


crosstalk interference from the adjacent signals.

• On the contrary, it takes more routing resources


and increases the capacitance of the clock net.

Note:
• We do shielding on clock nets so that crosstalk with signal nets can be avoided.
• We do shielding for long nets.
• What if we do shielding for short nets?
- capacitance of the short net will increase that will cause more net delay.

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PHYSICAL DESIGN 125

Conclusion on net topology


• Many techniques used to control power consumption in clock trees are also
inherently beneficial for achieving SI closure.

• Clock tree synthesis requires the robust implementation of length control rules,
clock gating and load balancing.

• In clock tree routing, clock wires should be shielded to reduce coupling


capacitance between active clock wires and neighboring nets.

• Typically, clock nets are routed with non-default rules (NDRs), which are either
defined in the technology files or specified by the user before clock routing.

• The NDRs for clock routing usually define double-width wires and double
spacing around wires as compared to the default rules.

• Double-width wires reduce wire resistance, and double spacing allows room for
shielding to be added.

• Shielding is simply grounded metal that dampens any signal noise from the
active clock nets

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PHYSICAL DESIGN 126

Specifying Routing Layers


• By default, the router uses all possible routing layers for routing wires.

• In some situations, we might want to limit routing to a layer range that does not include all routing
layers.

• For example, reserve the top layers for power and ground stripes or perform ECO routing on a few
layers only.

Specifying Hard Layer Limits

• the router routes all nets within those limits.

• If there is a pin outside the limits you specify, the router uses vias, including stacked vias, to access the
pin.

Specifying Soft Layer Limits

• the router attempts to route specific nets within a layer range, but might route some nets outside the
layer range if necessary to complete routing without creating violations.

• In addition, you can specify the effort level for staying within the range

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PHYSICAL DESIGN 127

Creating Route Guides


A route guide provides routing directives for specific areas of design –
• Preventing routing on specific layers
• Controlling the routing direction on specific layers
• Controlling the routing density on specify layers
• Prioritizing specific routing regions on specific layers
• Creating routing blockage on some specific region

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RC Extraction
PHYSICAL DESIGN 129

RC Extraction
• After routing we do the RC extraction for nets with extractor tool.

Why Extraction?

• Real wire has:

- Resistance

- Capacitance

• Therefore wiring forms a complex geometry that introduces capacitive and resistive parasitic.

• Effects:

- Impact on delay, energy consumption, power distribution

- Introduction of noise sources, which affects reliability

• To evaluate the effect of interconnects on design performance we have to model them

• For modeling the parasitces, we use different extraction corners.

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PHYSICAL DESIGN 130

RC Extraction
• The designer should take the following into account while carrying out parasitic
extraction:
– Which format is to be extracted:
• DSPF

• RSPF

• SPEF

• SDF

– Whether model should include coupling capacitance or should it be coupled to ground


– What is the distance at which the net should be sectioned for modeling
• The above two points will determine tool run time

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PHYSICAL DESIGN 131

Extraction flow
Here, the issues could be due to:
Prepare extraction • libraries
configuration file based • un-connected nets
on design criteria
Otherwise, this is a fairly straight
forward step.
Carry out extraction on
Routed database Only thing to be ensured is that the
entire design is routed and there
were no routing violations.

In the DSPF/ RSPF/ SPEF, check


Yes Are there the units of Resistance and
issues? Capacitance. They should match
with the one specified in the
No library.

Resolve issues

Extraction completed…

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PHYSICAL DESIGN 132

Extraction Corners
• Both R and C varies as various process/temperature parameters are changed.
• Process variation end up with a range of RC values for extracted nets. Typically, bigger wires
have more C and less R, smaller wires have less C and more R. Temperature also plays a part.
• When width changes as process parameter, resistance and capacitance change differently.
• When R is high C is lower and vice-versa.
• There are usually 5 extraction corner variations:
Cmin –when C is minimum
RCmin –when RC product is min
Cmax –when C is max
RCmax –when RC product is max
Typical –typical PVT condition

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PHYSICAL DESIGN 133

How Delay depends on R and C

Physical Wire

Td

Tcell Twire

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PHYSICAL DESIGN 134

The total delay from input of driver to input of receiver cell is


splitted into two parts.
1. Cell-delay which represents real scenario as the cell
output node can charge up much faster when resistance is
involved.
- tool calculates effective capacitance of the RC network
which is used for
deriving cell delay
2. wire delay which represents real delay from cell-output to
receiver cell input.
- Here tool uses various methods to derive the wire
delay

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PHYSICAL DESIGN 135

How does RC effect delay?


• The cell delay component is derived from RC network so it will depend on both R
and C.
- Though it depends on what value of R (Rmax-Rmin) and C (Cmin –Cmax) it is
maximum.
• The wire delay also depends on R and C both and its delay is maximum when
product RC is maximum.
- When wire is long and R is significant RCmax will become worst
- When wire is small, R is insignificant and hence Cmax becomes worst corner

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PHYSICAL DESIGN 136
Too many Analysis Corners &
modes
• One reason timing closure takes so long is that as process nodes shrink, there
are more and more modes and corners to consider.

• A quick look at theoretically possible corners shows how quickly things can add
up:

- Voltage: Best case, worst case, typical = 3 corners

- Temperature: Best case, worst case, typical = 3 corners

- Process for cells: Fast-fast, slow-slow, fast-slow, slow-fast, typical = 5 corners

- Process for interconnect: Max C, Min C, Max RC, Min RC, typical = 5 corners

• Multiply this out and you get 3X3X5X5=225 corners.

• And that's not even considering operational and test modes. Throw in 6 modes
and you're well over 1,000 views.

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Block Level Implementation Flow
Block level implementation – complete flow PHYSICAL DESIGN 138

Floor plan DEF Netlist Merged SDC


Update constraints

Libra Netli DEF UPF Incremental compile and report Floor plan implementation
ries st
Placement and Optimization
Floor plan: Is timing, area OK No
• Size, shape, utilization, aspect ratio ?
CTS and Optimization
• Pin placement
• Block placement Floor plan implementation
• Power planning
Routing and Optimization
• Power structure floor planning
(switch cells, isolation cells, Check floor plan, power plan
retention flops)
All metrics Timing closure
reasonable
Scan Constraints Block level met?
Map file for MBIST/BSCAN and DFT floor plan IR/EM Analysis & Closure
strategy/ methodology and LEC DRC/LVS/Antenna Closure
closure
Netlist SDC
SDC cleanup and exceptions Block level
physical RC extraction
Block level DFT design and
implementation STA (timing, slew, max-cap)
closure Xtalk, Noise Analysis
Floor plan Synthesis Scan Constraints No ECO fixing
Constraints Map file for MBIST/BSCAN Meeting STA
(with equivalence

Less SCAN Coverage


Noise, Xtalk
check)

MBIST/BSCAN fail
Power mesh closure – EM IR DFT insertion
Pre- and post-layout Equivalence
Placement and Optimization Equivalence check Check Fail

Final reviews
CTS and Optimization Zero delay DFT
simulation closed?

Routing and Optimization Yes .v, .gds, .sp, .lef, .def,


Reports
.spef, .sdf
SDC
Timing closure SDC
Netlist SDC
Second signoff deliverables
Feedback to top level: - Block level closed data for top level integration
DFT inserted DFT
• Pin position changes - All reports – STA, xtalk, noise, EM, IR, DRC, LVS,
• Timing constraints netlist constraint
s Antenna
• Block size and shape changes
• Power plan refinement

Copyright © 2013-2014, Infosys Limited 138


Signoff Checks
PHYSICAL DESIGN 140
Signoff Checks
- Paths from top level, needing closure at cluster level
Netlist STA SDCs Libraries
- Paths needing fixes at cluster level
- Paths from DFT/ verification needing closure at cluster level

Equivalence check between pre- and post-layout netlist


Library Process File
Design DB Map file Run script
DB (.nxtgrd)
No
EC results OK? Fix EC Issues

StarRCXT STA (path-based, normal and OCV) for all modes and corners
Design
database or
LEF-DEF Any timing Yes
violations in any ECO fixes
SPEFs for all corners mode/ corner?
(lumped and coupled)
Xtalk and Noise analysis for all modes and corners

Type of analysis Type of library for extraction Is Xtalk and Noise No


analysis ECO fixes
Timing, Xtalk, noise All conditions
analysis
Leakage analysis Leakage max condition library VCDs EM and IR drop analysis

EM Analysis Best case condition with high


interconnect RC Is EM/ IR drop No
clean? ECO fixes
IR drop Worst case condition library (high RC, low
voltage, high temperature)
To physical verification

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Physical Verification PHYSICAL DESIGN 141

APR

Run DRC/ LVS

Check if issue is due to rule


interpretation in routing rules vs rule
deck Any rules
violating?
- Some area rules pass standalone
but fail when surrounded by other
geometries
- Some samenet spacing rules can Signoff DRC/ LVS
become an issue under congested
areas No
- Via overhang can violate spacing in Any rules
violating? To further signoff checks/ tape out
densely routed areas
- All these rules cannot be
coded in routing rules

Yes
If violation is in a region: Check trend. Is violation around Check trend. Is violation around some
- Check cell and routing density some similar geometries cell types?
in the region - These will be all over the die - These will be all over the die
- Try easing out the congestion - Try re-routing in one of the - Run DRC/ LVS on the cell GDS
(there could be rules violating violating areas separately
due to lithography related - If design is too big, re-create - Likelihood of cell GDS and rule
checks (which are not coded the similar routing profile in deck out of sync
in routing rules) layout tool and run DRC to - Get clarification from foundry
check - Possibility of waivers in case of IO
- If confirmed, manually cells
correct violations - Get waiver clarified from
foundry

Copyright © 2013-2014, Infosys Limited 78


PHYSICAL DESIGN 142

Check Points
• The following should be checked:
– All nets have been extracted

– The log file should not indicate any unconnected net

– Format should be as desired by the front end designer for


post-route STA

Copyright © 2013-2014, Infosys Limited


ECO
PHYSICAL DESIGN 144

ECO – Engineering Change Order

ECO

Non -
Functional
Functional
ECO
ECO
- Bugs detected late in flow - Post layout timing fixes (setup/
- Minor feature additions hold/ load-slew/ Xtalk etc.)
- Can be handled through - Implemented through buffer
prior planning, if insertions/ deletion/ sizing
reasonable estimate is - Fixes are always managed locally –
available of the change/ no re-synthesis
feature addition - Can be handled metal-only
- Implemented through spare cells
or ECO cells
- If change is major, this can
start from Synthesis, in
which case it is not an ECO
- Can be handled metal-only (if
change is localized and not
major)

Copyright © 2013-2014, Infosys Limited


ECO Flow PHYSICAL DESIGN 145

Update can be through: For non-functional ECOs,


- Re-synthesis done for new feature. In this case, Update Netlist and existing DEF & Do postlayout DEF shall be
- DEF change is not done. Netlist change is Formal Verification with all fills removed
done followed by,
- DEF translation, flowed by, For functional ECOs,
Load old database choose appropriate DEF
- Adding sections from DEF to existing
postlayout DEF – assuming prior planning (postPlacement)
of the feature in existing design (reserved
placement region) Load new updated DEF
- Do an incremental placement, IPO and
“ecoImplement” is tool-
routing
specific feature, as
- Inserting the required update directly into ecoImplement different tools have
postlayout DEF (for non-functional ECO)
different ways of carrying
- Swapping an existing ECO filler cell with normal
it out
cell (metal fixes only)
Check ECO implementation logs
- Adding connectivity to the pre-inserted spare
cells

ECO Implementation No
Functional ECO checks: as planned?
- Post-synthesis cell count shall be as estimated
before (or close to it – within 10%) else it results
into local congestion hot spots and can trigger ecoPlace
large changes in design
- Make sure that the flops are added to Tool specific
appropriate scan chains
- If memories are added as a part of ECO, make ecoRoute
sure it is covered in MBIST
- If pins are added as ECO, make sure they are
Fix timing and DRCs, Add fills, retime and
placed on appropriate edge To signoff
fix
- Flow starts from CTS as clocks need to be
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2013-2014, to new logic
Infosys added to design
Limited
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