Modern Physical Design: Modern Physical Design

Modern Physical Design:
Algorithm
Technology
Methodology
Andrew B. Kahng UCLA

UCLA
Majid Sarrafzadeh Northwestern

Northwestern
Andrew B. Kahng
1
ICCAD Tutorial: November 11, 1999 C Majid Sarrafzadeh
Introduction
zz This tutorial will cover "the latest word" in physical chip
implementation methodology and physical design (PD) algorithm
technology.
zz The target audience consists of
zz system and circuit designers who would benefit from
understanding tool capabilities in this arena,
zz CAD engineers (both R&D and support),
zz design project managers,
zz academic researchers.
zz Familiarity with basic PD methodology is assumed.
Andrew B. Kahng
2
1
Trade-Off: Depth vs. Breadth
zz Broad spectrum of possible material
zz Only ~6-7 hours for presentation
zz Not all possible topics covered in slides, not all slides covered
in talks
zz ask questions if you’d like to hear about something
something in
in particular,
particular,
esp. related to methodology or particular P&R techniques
z All tutorial materials will be available in softcopy at
zz http://vlsicad.cs.ucla.edu/ICCAD99TUTORIAL
zz http://www.ece.nwu.edu/nucad/ICCAD99TUTORIAL
Andrew B. Kahng
3
Overview of the Tutorial

z PART I: Technology and Methodology Context Setting
(9:00
(9:00 -- 10:00)
10:00)
z PART II: Fundamental Physical Design Formulation and
Algorithms (10:00
(10:00 -- 12:00)
12:00)
zz Coffee
Coffee Break
Break (10:30
(10:30 -- 10:45)
10:45)
zz Lunch
Lunch (12:00
(12:00 -- 1:00)
1:00)
z PART III: Interaction with Upstream Floorplanning and
Logic Synthesis (1:00
(1:00 -- 2:00)
2:00)
z PART IV: Interaction with extraction, analysis, and
performance validation (2:00
(2:00 -- 3:30)
3:30)
zz Coffee
Coffee Break
Break (3:30
(3:30 -- 3:45)
3:45)
z PART V: Linkage to Custom Layout (3:45
(3:45 -- 4:45)
4:45)
z Conclusion (4:45
(4:45 -- 5:00)
5:00)
Andrew B. Kahng
4
2
Modern Physical Design:
Algorithm
Technology
Methodology
(Part I)
Andrew B. Kahng UCLA
UCLA
Majid Sarrafzadeh Northwestern

Northwestern
Andrew B. Kahng
5
Outline
z Technology trends
z Post-layout optimization methodologies
zz manufacturability and reliability
zz performance
z Custom or custom-on-the-fly methodologies
z Flavors of classic planning-based methodologies
z Implications for P&R
Andrew B. Kahng
6
3
Overall Roadmap Technology
Characteristics
YEAR OF FIRS T P RO DUCT S HIP M ENT 1997 1999 2002 2005 2008 2011 2014
TE C H N O LO G Y N O D E
250 180 130 100 70 50 35
D E N S E L IN E S (D R A M H A LF -P ITC H ) (n m )
IS O L A TE D LIN E S (M P U G A TE S ) (nm ) 200 140 100 70 50 35 25
Log ic (Low -V o lum e— A S IC )‡
U s ab le trans is tors /c m 2 (auto lay o ut) 8M 14M 24M 40M 64M 100 M 160 M
N onrec urring en gin eering c os t
50 25 15 10 5 2.5 1.3
/us able trans is tor (m ic roc ents )
N um ber o f C hip I/O s – M ax im um
C hip-to-pac k age (pa ds )
151 5 186 7 255 3 349 2 477 6 653 2 893 5
(hig h-p erform a nc e)
C hip-to-pac k age (pa ds )
758 934 127 7 174 7 238 6 326 8 447 0
(c os t-pe rform an c e)
N um ber o f P ac k ag e P ins /B alls – M ax im u m
M ic rop roc e s s or/c o ntrolle r
568 700 957 130 9 179 1 244 9 335 0
A S IC
113 6 140 0 191 5 261 9 358 1 489 8 670 0
(hig h-p erform a nc e)
P ac k age c os t (c ents /pin)
0.78-2.7 1 0.70-2.5 2 0.60-2.1 6 0.51-1.8 5 0.44-1.5 9 0.38-1.3 6 0.33-1.1 7
P ow er S u pply V oltage (V )
M in im um logic V dd (V ) 1.8–2.5 1.5–1.8 1.2–1.5 0.9–1.2 0.6–0.9 0.5–0.6 0.37-0.4 2
M ax im um P ow er
H igh-perform anc e w ith heat s ink (W ) 70 90 130 160 170 175 183
B attery (W )— (H an d-h eld ) 1.2 1.4 2 2.4 2.8 3.2 3.7
Andrew B. Kahng
7
Overall Roadmap Technology

Cont’d)
Characteristics ((Cont’d)
YEAR OF FIRST PRODUCT SHIPMENT 1997 1999 2002 2005 2008 2011 2014
TECHNOLOGY NODE
250 180 130 100 70 50 35
DENSE LINES (DRAM HALF-PITCH) (nm)
Chip Frequency (MHz)
On-chip local clock
750 1250 2100 3500 6000 10000 16903
(high-performance)
On-chip, across-chip clock
375 1200 1600 2000 2500 3000 3674
(high-performance)
300 500 700 900 1200 1500 1936
(high-performance ASIC)
400 600 800 1100 1400 1800 2303
(cost-performance)
Chip-to-board (off-chip) speed
(high-performance, reduced-width, 375 1200 1600 2000 2500 3000 3674
multiplexed bus)
Chip-to-board (off-chip) speed
250 480 885 1035 1285 1540 1878
(high-performance, peripheral buses)
Chip Size (mm2) (@sample/introduction)
DRAM 280 400 560 790 1120 1580 2240
Microprocessor 300 340 430 520 620 750 901
ASIC [max litho field area] 480 800 900 1000 1100 1300 1482
Lithographic Field Size (mm2) 22 x 22 25 x 32 25 x 36 25 x 40 25 x 44 25 x 52 25 x 59
484 800 900 1000 1100 1300 1482
Maximum Number Wiring Levels 6 6–7 7 7–8 8–9 9 10
Andrew B. Kahng
8
4
Technology Scaling Trends
z Interconnect
zz Impact of scaling on parasitic capacitance
zz Impact of scaling on inductance coupling
zz Impact of new materials on parasitic capacitance & resistance
zz Trends in number of layers, routing pitch
z Device
zz Vdd
dd, Vtt, sizing
zz Circuit trends (multithreshold CMOS, multiple supply voltages,
dynamic CMOS)
zz Impact of scaling on power and reliability
Andrew B. Kahng
9
Reachability in τcrit
crit
= 80 ps
25 x 25 mm chip
Andrew B. Kahng
10
5
z Scaling of x0.7 every three years
zz .25u .18u .13u .10u .07u .05u
zz 1997 1999 2002 2005 2008 2011
zz 5LM 6LM 7LM 7LM 8LM 9LM
z Interconnect delay dominates system performance
zz consumes 70% of clock cycle
z Cross coupling capacitance is dominating
zz cross capacitance → 100%, ground capacitance → 0%
zz 90% in .18u
zz huge signal integrity implications (e.g., guardbands in static
analysis approaches)
z Multiple clock cycles required to cross chip
zz whether 3 or 15 not as important as fact of “multiple” > 1
Andrew B. Kahng
11
Technology Extrapolation Sensitivity
Andrew B. Kahng
12
6
Technology Extrapolation Sensitivity
Andrew B. Kahng
13
http://vlsicad.cs.ucla.edu/GSRC/GTX/
Andrew B. Kahng
14
7
Andrew B. Kahng
15
Deep- Submicron Interconnect

Deep-Submicron
Complexity
18
Estimated Number of Nets At-Risk 16

At-Risk Nets (millions)
Risk Factors: 14
Interconnect Delay
Signal Integrity 12
Electromigration
Process Variations 10
2
0.13
0.18
0.25
0.35
0.5
Technology (µ)
Andrew B. Kahng
16
Courtesy Hormoz/Muddu, ASIC99 ICCAD Tutorial: November 11, 1999 C Majid Sarrafzadeh
8
Scaling of Noise with Process
z Cross coupling noise increases with
zz process shrink
zz frequency of operation
z Propagated noise increases with decrease in noise
margins
zz decrease in supply voltage
zz more extreme P/N ratios for high speed operation
z IR drop noise increases with
zz complexity of chip size
zz frequency of chip
zz shrinking of metal layers
layers
Andrew B. Kahng
17
New Materials Implications

z Lower dielectric
zz reduces total capacitance
zz doesn’t change cross-coupled / grounded capacitance
proportions
z Copper metallization
zz reduces RC delay
zz avoids electromigration (factor of 4-5 ?)
zz thinner deposition reduces cross cap
z Multiple layers of routing
zz enabled by planarized processes; 10% extra cost per layer
zz reverse-scaled top-level interconnects
zz relative routing pitch may increase
zz room for shielding
Andrew B. Kahng
18
9
Technical Issues in UDSM Design
z New issues and problems arising in UDSM technology
zz catastrophic yield: critical area, antennas
zz parametric yield: density control (filling) for CMP
zz parametric yield: subwavelength lithography implications
zz optical
optical proximity
proximity correction
correction (OPC)
(OPC)
zz phase-shifting
phase-shifting mask
mask design
design (PSM)
(PSM)
zz signal integrity
zz crosstalk
crosstalk and
and delay
delay uncertainty
uncertainty
zz DC
DC electromigration
electromigration
zz AC
AC self-heat
self-heat
zz hot
hot electrons
electrons
z Current context: cell-based place-and-route methodology
zz placement and routing formulations, basic technologies
zz methodology contexts
Andrew B. Kahng
19
Technical Issues in UDSM Design

z Manufacturability (chip can't be built)
zz antenna rules
zz minimum area rules for stacked vias
zz CMP (chemical mechanical polishing) area fill rules
zz layout corrections for optical proximity effects in subwavelength
lithography; associated verification issues
z Signal integrity (failure to meet timing targets)
zz crosstalk induced errors
zz timing dependence on crosstalk
zz IR drop on power supplies
z Reliability (design failures in the field)
zz electromigration on power supplies
zz hot electron effects on devices
zz wire self heat effects on clocks and signals
Andrew B. Kahng
20
10
Why Now?
z These effects have always existed, but become worse
at UDSM sizes because of:
zz finer geometries
zz greater
greater wire
wire and
and via
via resistance
resistance
zz higher
higher electric
electric fields
fields ifif supply
supply voltage
voltage not
not scaled
scaled
zz more metal layers
zz higher
higher ratio
ratio of
of cross
cross coupling
coupling to to grounded
grounded capacitance
capacitance
zz lower supply voltages
zz more
more current
current for
for given
given power
power
zz lower device thresholds
zz smaller
smaller noise
noise margins
margins
z Focus on interconnect
zz susceptible to patterning difficulties
zz CMP,
CMP, optical
optical exposure,
exposure, resist
resist development/etch,
development/etch, CVD,
CVD, ...
...
zz susceptible to defects
zz critical
critical area,
area, critical
critical volume
volume
Andrew B. Kahng
21
Issues in IC Design
SYSTEM SUBSYSTEM CIRCUIT PHYSICAL MANUFACTURE
DESIGN DESIGN DESIGN DESIGN INTERFACE
Spec RTL/code Gates/Cells Xtrs Masks Chip
SW design Logic Analog and Detailed Mask

Design Partitioning optimization macro placement correction
Functional Technology design Detailed Yield
mapping mapping Extraction routing optimization
Sorting
Floorplanning
Analysis Performance Power Power, Power N/A
modeling estimation noise distribution
Power analysis analysis
estimation Signal
integrity
System Functional Circuit
N/A
Verification simulation simulation simulation
Formal checking LVS/DRC
Equivalence checking
Static timing verification
Test Test logic Test Pattern Chip test &

Test architecture insertion model generation & diagnostics
generation merge
New Figure 4 (Draft Rev. B, 3-12-99) Red denotes most challenging activity
11
ASSP: 44% WallTime, 39% Total Effort
After First Tape-out
Time and Effort Allocation by First Tape-out
100%
First Tape-out
Percent of Total Project Effort
80%
(Man-Weeks)
60%
40%
61%
39%
20%
56% 44%
0%
0% 20% 40% 60% 80% 100%
Start of Concept Phase Release to Manufacturing

Percent of Total Project Duration
* Data Source: Collett International Inc.’s Design Productivity Management SystemTM (DPMS) database.
** ASSP (Application Specific Standard Product): Standard “off--the-shelf” IC product that has been Andrew B. Kahng
23 designed to implement a specific application function.
ASSP Design Productivity +27% Annually

Design Productivity Trend* Key
10X
= ASSP*** design
9X
8X
Design Productivity
7X
6X
5X
4X
3X
2X
1X
0
06/94 06/95 06/96 06/97 06/98
Project Start Date
* Data Source: Collett International Inc.’s Design Productivity Management SystemTM (DPMS) database.
** Methodology: The design productivity trendline is the ordinary-least-squares (OLS) regression line. 27% is the compound
annual growth rate between 06/94 & 06/98.
*** ASSP (Application Specific Standard Product): Standard “off--the-shelf” IC product that has been designed to implement
Andrew B. Kahng
a specific application function.
24
12
Silicon Complexity and Design
Complexity
z Silicon complexity: physical effects cannot be ignored
zz fast but weak gates; resistive and cross-coupled interconnects
zz subwavelength lithography from 350nm generation onward
zz delay, power, signal integrity, manufacturability, reliability all
become first-class objectives along with area
z Design complexity: more functionality and
customization, in less time
zz reuse-based design methodologies for SOC
z Interactions increase complexity
zz need robust, top-down, convergent design methodology
Andrew B. Kahng
25
Guiding Philosophy in the Back-End

z Many opportunities to leave $$$ on table
zz physical effects of process, migratability
zz design rules more conservative, design waivers up
zz device-level layout optimizations in cell-based methodologies
z Verification cost increases
z Prevention becomes necessary complement to
checking
z Successive approximation = design convergence
zz upstream activities pass intentions, assumptions downstream
zz downstream activities must be predictable
zz models of analysis/verification = objectives for synthesis
z More “custom” bias in automated methodologies
Andrew B. Kahng
26
13
Implications of Complexity
z UDSM: Silicon complexity + Design complexity
zz convergent design: must abstract what’s beneath
zz prevention
prevention with
with respect
respect to
to analysis/verification
analysis/verification checks
checks
zz many
many issues
issues to
to worry
worry about
about (all
(all are
are “first-class
“first-class citizens”
citizens”
zz apply
apply methodology
methodology (P/G/clock
(P/G/clock design,
design, circuit
circuit tricks,
tricks, …)
…) whenever
whenever possible
possible
zz must concede loss of clean abstractions: need unifications
zz synthesis
synthesis and
and analysis
analysis in
in tight
tight loop
loop
zz logic
logic and layout : chip implementation planning
and layout : chip implementation planning methodologies
methodologies
zz layout
layout and
and manufacturing
manufacturing :: CMP/OPC/PSM,
CMP/OPC/PSM, yield,
yield, reliability,
reliability, SI,
SI, statistical
statistical
design,
design, ……
zz must hit function/cost/TAT points that maximize $/wafer
zz reuse-based
reuse-based methodology
methodology
zz need
need for differentiating IP
for differentiating IP →→ custom-ization
custom-ization
Andrew B. Kahng
27
Outline
z Technology trends
zz performance
Andrew B. Kahng
28
14
Example: Defect-related Yield Loss
z High susceptibility to spot defect-related yield loss,
particularly in metallization stages of process
z Most common failure mechanisms: shorts or opens due
to extra or missing material between metal tracks
z Design tools fail to realize that values in design manuals
are minimum values, not target values
z Spot defect yield loss modeling
zz extremely well-studied field
zz first-order yield prediction: Poisson yield model
zz critical-area model much more successful
zz fatal defect types (two types of short circuits, one type of open)
Andrew B. Kahng
29
Defect-related Yield Loss
fatal defect types (two types of short circuits, one type of open)
Andrew B. Kahng
30
15
Critical Area for Short Circuits
Critical Area for Shorts
Andrew B. Kahng
31
Critical Area for Short Circuits
Critical Area
for Shorts
Andrew B. Kahng
32
16
Approaches to Spot Defect Yield
Loss
z Modify wire placements to minimize critical area
z Router issue
zz router understands critical-area analyses, optimizations
zz spread, push/shove (gridless, compaction technology)
zz layer reassignment, via shifting (standard capabilities)
zz related: via doubling when available, etc.
z Post-processing approaches in PV are awkward
zz breaks performance verification in layout (if layout has been
changed by physical verification)
zz no easy loop back to physical design: convergence problems
Andrew B. Kahng
33
Example: Antennas
z Charging in semiconductor processing
zz many process steps use plasmas, charged particles
zz charge collects on conducting poly, metal surfaces
zz capacitive coupling: large electrical fields over gate oxides
zz stresses cause damage, or complete breakdown
zz induced Vtt shifts affect device matching (e.g., in analog)
Andrew B. Kahng
34
17
Antennas
z Standard solution: limit antenna ratio
zz antenna ratio = (Apoly
poly + AM1
M1 + ... ) / Agate-ox
gate-ox
zz e.g., antenna ratio < 300
Mx ≡ metal (x) area electrically connected to node without using
zz AMx
metal (x+1), and not connected to an active area
Andrew B. Kahng
35
Antennas
z Standard solution: limit antenna ratio
z General solution == bridging (break antenna by moving
route to higher layer)
z Antennas also solved by protection diodes
zz not free (leakage power, area penalties)
z Basically, annoying-but-solved problem
zz not clear whether today’s approaches scale into the future
zz (today, mostly post-processing approaches)
Andrew B. Kahng
36
18
Wire Spacing and Layout Methodology
z Routing tools do not always optimize for spacing

z Stand-alone spacing
z layout (GDSII/DEF) -> layout (GDSII/DEF)
z Need tight interface to extraction and timing simulation
z Future: built-in extraction and timing estimates
Andrew B. Kahng
37
Courtesy M. Berkens, DAC99 ICCAD Tutorial: November 11, 1999 C Majid Sarrafzadeh
Data Aspects of Post Layout Optimization
z Jogging increases amount of data significantly

z Massive data needs striping
z minor loss of optimality for large stripes
z need work across hierarchy
z fix boundary location, “look” beyond cut-line
z need propagate net information
z Must support multi-processing for reasonable TAT
Andrew B. Kahng
38
19
Wire Spacing and Shielding
z Pre routing specification

z convenient, handled by router
z robust but conservative
z may consume big area
z Post routing specification
z area efficient-shield only where needed & have space
z ease task of router
z sufficient shielding is not guaranteed
z Either way: definite interactions w/ fill insertion,
possible interactions w/ phase-shifting (M1,M2?)
Andrew B. Kahng
39
Opportunities for Via Strengthening
z Add cut holes where possible

z wire widening may need larger/more vias
z “non square” via cells
z Increase metal-via overhang
z non uniform overhang
Andrew B. Kahng
40
20
Wire spacing example
before spacing after spacing
Andrew B. Kahng
41
Outline
z Technology trends
zz performance
Andrew B. Kahng
42
21
Performance Optimization Methodology
z Tradeoffs: Speed / Power / Area
z Must compromise and choose between often competing
criteria
z For given criteria (constraints) on some variables, make
best choice for free variables (min cost) => Need to be
on boundary of feasible region
Andrew B. Kahng
43
Courtesy Bamji, DAC99 ICCAD Tutorial: November 11, 1999 C Majid Sarrafzadeh
Optimization
Methods
Reorganize Logic
Re r
tim ffe
e Bu
Size
e
ac
Sp
z Many different kinds of delay/area optimization are

possible
z Many optimizations are somewhat independent
zz use
use several
several different
different optimizations.
optimizations. Apply
Apply whichever
whichever ones
ones are
are
applicable
applicable
Andrew B. Kahng
44
22
Optimization at Layout Level
z Size Transistors
z Space/size wires
z Add/delete buffers
z Modify circuit locally
Andrew B. Kahng
45
Transistor Sizing
Area Delay Curve
Area Feasible X You are here

Region Optimal Curve
lowest area for
You need
a given delay
to be here
Infeasible
Region X
Min cost
No assignment of sizes can produce a result here
Min delay Required Delay Delay
Andrew B. Kahng
46
23
Transistor sizing
What will it buy me?
z Scenario: Lots of capacitance in wires
zz will it buy me speed: Yes
zz will is save me power: “Yes” (qualified)
Architecture cannot
Architecture is
Area satisfy application
an overkill for
(increase parallelism)
Delay cannot this application
be improved Architecture and
at any cost application are
well matched
Delay can be improved
at almost no cost
Delay
Andrew B. Kahng
47
Transistor Sizing
Convexity + Dual Goals
5ns 10ns
W1 Circuits of constant delay:15ns

(size of Xtr1)
Faster circuits inside this curve
Optimal
point for Circuits of constant cost W1 +W2 = Cte
10ns
W2
(size of Xtr2)
Note: Actually circuit delay is Posynomial ~ Convex
Andrew B. Kahng
48
24
Transistor Sizing
Methods
z Exact Solutions
zz gradient Search
zz convex Programming
z Approximate methods (very good solutions)
zz iterative improvement on critical path (e.g. TILOS)
Andrew B. Kahng
49
Convex Programming
Outside Delay Case
z Add more and more bounds
zz guess new solution (deep) inside bounds
Bound 1 New guess delay is too slow so

W1
New guess add new bound: Tangent
to curve of equal delay at new
New bound
Required guess. New feasible region is

Delay to the left (region which contains
X
required delay).
nd 2
Bou
W2
Andrew B. Kahng
50
25
Convex Programming
Inside Delay Case
z New guess delay is adequate but try and improve cost
Bound 1
W1 Add a bound to force
New guess search into region
of lower cost. New bound
Bound 3
Required
is constant cost curve
Delay
X passing through new
N
guess. New feasible

ew
nd 2
bo
Constant cost Bou region is below new

un
d
bound.
W2
Andrew B. Kahng
51
Transistor Sizing
Approximate Solutions
Circuit delay affected

only by delay of
Move maximally in this critical path. Upsize by
direction D1 to improve delay
W1 small amount
transistors on crit path
with biggest D1/D2 =
Co
ns
improvement/cost.
ta nt
De Repeat until timing met
lay
Move minimally in this
Co st
direction D2 to reduce cost

ns
co
ta
nt
W2
Andrew B. Kahng
52
26
Transistor Sizing
TILOS method
δ2 = slowdown of T δ1= speedup of T

T Effective speedup of
T = δ1 - δ2 = 5
5
3
Critical Path
4
Effective speedup
per unit area
z Increase Xtr on critical path with largest per unit

effective speedup: T
Andrew B. Kahng
53
Short Circuit Power Optimization

z Critical path methods miss short circuit power
Critical path
Short circuit power burned

Islow
in all of these gates due to
slow input rise time. Gates not
Slow node on critical path
zz Increase Islow
slow
until capacitive power increase for driving Islow
slow
is more
than decrease in S.C. power
zz sweep
sweep circuit
circuit from
from outputs
outputs to
to inputs
inputs
Andrew B. Kahng
54
27
TILOS Optimization Trajectory
Starting Point. Feasible

Region
Power X
do
wn
Reduce siz
e Note:
S.C.
Min Size != Min Power
X
.
uit
Ci e
Infeasible
S. d u c
X fix timin
rc
Region g
Re
X
Required delay Delay
Andrew B. Kahng
55
Buffer Insertion
Area delay tradeoffs
W
With
it h
Feasible Region
Area
bu
ou
Is the Union of both

f fe
t bu
feasible regions
r
ffer
Area of Min
Optimization Size buffer
Add buffer at
Trajectory
this point
Delay
z Optimal curve is envelope of curves

zz jump to buffered curve during timing optimization
Andrew B. Kahng
56
28
Local Re-synthesis
z Pass Xtr re-synthesis, logic reorganization
z Gate collapsing
Tp
P1 P3
P2
N3
N1 N2 Tn
zz TPP conducts <=> N11 conducts. Replace TPP with N11

zz repeat
repeat for
for P
P22 and
and T
Tnn for
for correct
correct NMOS/PMOS
NMOS/PMOS
Andrew B. Kahng
57
Gate Collapsing
Example
z Trade off drive-capability/logic-levels

zz Intrinsic Delay RC Delay
zz reduce number of transistors (area )
Andrew B. Kahng
58
29
Outline
z Technology trends
zz performance
Andrew B. Kahng
59
Custom Methodology in ASIC(?) / COT
z How much is on the table w.r.t. performance?

zz 4x
4x speed,
speed, 1/3x
1/3x area,
area, 1/10x
1/10x power
power (Alpha
(Alpha vs.
vs. Strongarm
Strongarm vs.
vs. “ASIC”)
“ASIC”)
zz layout
layout methodology
methodology spans
spans RTL
RTL syn,
syn, auto
auto P&R,
P&R, tiling/generation,
tiling/generation,
manual
manual
zz library
library methodology
methodology spans
spans gate
gate array,
array, std
std cell,
cell, rich
rich std
std cell,
cell, liquid
liquid lib,
lib,
…
…
z Traditional view of cell-based ASIC
zz Advantages: high productivity, TTM, portability (soft IP, gates)
zz Disadvantages: slower, more power, more area, slow production
of std cell library
z Traditional view of Custom
zz Advantages: faster, less power, less area, more circuit styles
zz Disadvantages: low productivity, longer TTM, limited reuse
Andrew B. Kahng
60
30
z With sub-wavelength lithography:

zz how much more guardbanding will standard cells need?
zz composability is difficult to guarantee at edges of PSM layouts,
when PSM layouts are routed, when hard IPs are made with
different density targets, etc.
zz context-independent composability is the foundation of cell-
based methodology!
z With variant process flavors:
zz hard layouts (including cells) will be more difficult to reuse
z → Relative cost of custom decreases
z On the other hand, productivity is always an issue...
Andrew B. Kahng
61
z Architecture
zz heavy pipelining
zz fewer logic levels between latches
z Dynamic logic
zz used on all critical paths
z Hand-crafted circuit topologies, sizing and layout
zz good attention to design reduces guardbands
The last seems to be the lowest-hanging fruit for ASIC
Andrew B. Kahng
62
31
z ASIC market forces (IP differentiation) will define needs
for xtor-level analyses and syntheses
z Flexible-hierarchical top-down methodology
zz basic strategy: iteratively re-optimize chunks of the design as
defined by the layout, i.e., cut out a piece of physical hierarchy,
reoptimize it (“peephole optimization”)
zz for
for timing/power/area
timing/power/area (e.g.,
(e.g., for
for mismatched
mismatched input
input arrival
arrival times,
times,
slews)
slews)
zz for
for auto-layout
auto-layout (e.g.,
(e.g., pin
pin access
access and
and cell
cell porosity
porosity for
for router)
router)
zz for
for manufacturability (density control, critical area, phase-
manufacturability (density control, critical area, phase-
assignability)
assignability)
zz DOF’s:
DOF’s: diffusion
diffusion sharing,
sharing, sizing,
sizing, new
new mapping
mapping // circuit
circuit topology
topology
sol’s
sol’s
zz chunk
chunk size:
size: as
as large
large as
as possible
possible (tradeoff
(tradeoff between
between near-optimality,
near-optimality,
CPU
CPU time)
time)
zz antecedents: IBM C5M, Motorola CELLERITY, DEC CLEO
zz “infinite library”recovers performance, density that a 300-cell
library and classic cell-based flow leave on the table
Andrew B. Kahng
63

z Supporting belief: characterization and verification are
increasingly a non-issue
zz CPUs
CPUs get
get faster;
faster; size
size of
of layout
layout chunks
chunks (O(100-1000)
(O(100-1000) xtors)
xtors) stay
stay
same
same
zz natural
natural instance
instance complexity
complexity limits
limits due
due to
to hierarchy,
hierarchy, layers
layers of
of
interest
interest
z Compactor-based migration tools are an ingredient ?
zz migration
migration perspective
perspective can
can infer
infer too
too many
many constraints
constraints that
that aren’t
aren’t
there
there (consequence
(consequence of
of compaction
compaction mindset)
mindset)
zz little
little clue
clue about
about integrated
integrated performance
performance analyses
analyses
z Tuners are an ingredient ? (size, dual-Vt, multi-supply)
zz limit
limit DOFs
DOFs (e.g.,
(e.g., repeater
repeater insertion
insertion and
and clustering,
clustering, inverter
inverter opts
opts
zz cannot handle modern design rules, all-angle geometries
cannot handle modern design rules, all-angle geometries
zz not
not intended
intended to
to do
do high-quality
high-quality layout
layout synthesis
synthesis
z Layout synthesis is an ingredient ?
zz requires
requires optimizations
optimizations based
based on
on detailed
detailed analyses
analyses (routability,
(routability,
signal
signal integrity,
integrity, manufacturability),
manufacturability), transparent
transparent links
links to
to
characterization
characterization andand verification
verification
Andrew B. Kahng
64
32
z “Layout or re-layout on the fly” is an element of

performance- and cost-driven ASIC methodology going
forward
z “Polygon layout as a DOF in circuit optimization” is a
very small step from “polygon layout as a DOF in
process migration”
zz designers are already reconciled to the latter
Andrew B. Kahng
65
Outline
z Technology trends
zz performance
Andrew B. Kahng
66
33
Sylvester-Keutzer: Classic Picture
Andrew B. Kahng
67
Sylvester-Keutzer, Computer Nov. 99 ICCAD Tutorial: November 11, 1999 C Majid Sarrafzadeh
Sylvester-Keutzer: Combining
Logical and Physical
Andrew B. Kahng
68
Sylvester-Keutzer, Computer Nov. 99 ICCAD Tutorial: November 11, 1999 C Majid Sarrafzadeh
34
Required Advance in Design System Architecture
Yesterday 1000nm Today 180nm Tomorrow 50nm
System System System System System

Design Design Model Design Model
Functional
Software Performance
Perf. SPEC
Logic Design Hw/Sw Testability
Design Optimization Model Verification
Functional
Cockpit
Verification
RTL SW Auto-Pilot
RTL SW Optimize Analyze
Opt Hw/Sw Comm. Perf.
Synthesis SW Timing
EQ check
Synthesis Logic Hw/Sw Power
+ Timing Analysis Circuit Data Noise
Equivalence checking
File + Placement Opt Model
Place Test
Wire Mfg.
Timing Analysis Performance other
Repository
other
File Testability
Verification
Functional
File MASKS
Verification
Place/Wire
+ Timing Analysis
Place/Wire + Logic Opt
File
File
Multiple design files are converged into one efficient Data Model
Timing Analysis Disk accesses are eliminated in critical methodology loops
MASKS Verification of Function, Performance, Testability and other design
Performance criteria all move to earlier, higher levels of abstraction followed by
File Verification equivalence checking and
assertion driven design optimizations
Testability Industry Standard interfaces for data access and control
MASKS Verification Incremental modular tools for optimization and analysis
New Table 8
Planning / Implementation
Methodologies
z Centered on logic design
zz wire-planning methodology with block/cell global placement
zz global routing directives passed forward to chip finishing
zz constant-delay methodology may be used to guide sizing
z Centered on physical design
zz placement-driven or placement-knowledgeable logic synthesis
z Buffer between logic and layout synthesis
zz placement, timing, sizing optimization tools
z Centered on SOC, chip-level planning
zz interface synthesis between blocks
zz communications protocol, protocol implementation decisions
guide logic and physical implementation
Andrew B. Kahng
70
35
Planning / Implementation
Methodologies
z Centered on logic design
zz wire-planning methodology with block/cell global placement
zz global routing directives passed forward to chip finishing
zz constant-delay methodology may be used to guide sizing
z Centered on physical design
zz placement-driven or placement-knowledgeable logic synthesis
z Buffer between logic and layout synthesis
zz placement, timing, sizing optimization tools
z Centered on SOC, chip-level planning
zz interface synthesis between blocks
zz communications protocol, protocol implementation decisions
guide logic and physical implementation
Andrew B. Kahng
71
Performance Optimization Tool Flow

Architectural/ Behavioral Design
RTL Design
Floor Planning Logic Synthesis

Electrical Analysis
Placement /Estimation Optimization
Global Routing Detailed Routing
Extraction
EM Power Timing Signal Integrity Clock

Analysis Analysis Analysis Analysis Analysis
Andrew B. Kahng
72
36
Performance Optimization Methodology
z Design Optimization
zz global restructuring optimization -- logic optimization on layout
using actual RC, noise peak values etc.
zz localized optimization -- with no structural changes and least
layout impact
zz repeater/buffer insertion for global wires
z Physical optimization
zz high fanout net synthesis (eg. for clock nets); buffer trees to meet
delay/skew and fanout requirements
zz automatically determine network topology (# levels, #buffers, and
type of buffers)
zz wire sizing, spacing, shielding etc.
z Fixing timing violations automatically
zz fix setup/hold time violations
zz fix maximum slew and fanout violations
Andrew B. Kahng
73
Ultra Deep Submicron Timing
GL
Total
RCw
Delay=Gi+GL+RCw
Gi
Gi = Intrinsic Gate Delay
60%
GL = Gate Delay from Load
RCw= Delay from Interconn
Loading
20% 25%
20%
10% Critical Path Delay
5%
0% 0% 0% Electrical Optimization
Gi GL RCw Logic Optimization
50K gate Block at 0.18 microns
Andrew B. Kahng
74
37
KEY ISSUE: PREDICTABILITY
z Everything we do is ultimately aimed at a predictable,

estimatable back end (physical implementation after
some handoff level of design)
z Predictability == regression models
z Predictability == an enforceable assumption
zz constant-delay paradigm (logical effort, DEC, IBM, ...)
z Predictability == fast constructive prediction
zz RT-level (Tera), gate-level flat full-chip (SPC)
z Predictability == remove the need for predictability
zz GALS, LIS
zz “protocol- / communication-based system-level design”
Andrew B. Kahng
75
Problems With Physical Hierarchy
z Physical hierarchy = hierarchical organization of the

core layout region
z In general, no relation to high-quality (e.g., w.r.t. timing,
routability) embedding of logic
zz artifactual physical hierarchy created by top-down placers
zz core region is relatively homogeneous, isotropic: imposing a
hierarchy is generally harmful
z Of course, some obvious exceptions
zz regular structures (memories, PLAs, datapaths)
zz hard IP blocks
zz but these don’t fit well in top-down placement anyway
z General trend: non-hierarchical embedding approaches
Andrew B. Kahng
76
38
The Problem With Hierarchies
z Two hierarchies: logical/functional, and physical

zz schematic hierarchy also typical in structured-custom
z RTL design = logical/functional hierarchy
zz provides valuable clues for physical embedding: datapath
structure, timing structure, etc.
zz can be incredibly misleading (e.g., all clock buffers in a single
hierarchy block)
z Main issues:
zz how to leverage logical/functional hierarchy during embedding
zz when to deviate from designer’s hierarchy
zz methodology for hierarchy reconciliation (buffers, repartitioning /
reclustering, etc.)
Andrew B. Kahng
77
Interconnect Complexities
zz Interconnect effects play a major role in the increasing costs for
large hard-block or rectilinear-outline based design styles
zz Probabilistic wireload models fail
zz Without new capabilities for soft IP design and assembly,
interconnect problems will significantly impact performance and cost
for emerging IC technologies
Local wires
Occurrence Rate
blocks
(Normalized)
global
Global wires wires
~0.5 wirelength
die _ size
Andrew B. Kahng
78
Courtesy Pileggi, MARCO GSRC ICCAD Tutorial: November 11, 1999 C Majid Sarrafzadeh
39
Technology Scaling
zz Block sizes cannot grow as rapidly as chip sizes since block design
becomes increasingly more difficult --- each block is a chip design
over multiple configurations
zz If the blocks are inflexible, the global wiring problems begin to
dominate all aspects of performance quality and system cost
Occurrence Rate
(Normalized)
Larger chip with

wirelength finer feature sizes
~0.5
die _ size
Andrew B. Kahng
79
Soft Blocks
zz With soft,
soft, flexible
flexible blocks, the system assembly can more thoroughly
exploit the available technology
zz Interconnect problem is controlled via: soft boundaries for area re-
shaping; re-synthesis and re-mapping for timing; smart wires; and
top-down specified block synthesis
zz Cf. “Amoeba” placement, coloring analysis of “good” placements
with respect to original logic hierarchy, etc.
Occurrence Rate
(Normalized)
Superior timing,
wirelength power and cost
~0.5
die _ size
Andrew B. Kahng
80
40
Soft-Block Assembly
zz Hard rectilinear blocks make prediction of global wires extremely
difficult
zz Top-down constraint-driven assembly of soft fabrics: ability to
significantly restructure circuit level blocks during the assembly
process helps reach performance goals
zz For
For example,
example, timing-critical
timing-critical interconnect
interconnect paths
paths can
can be
be completely
completely
restructured
restructured during
during assembly
assembly without
without changing
changing any
any of
of the
the system
system level
level
specification
specification
zz Key issue: how to determine the soft blocks in the first place
zz non-classical
non-classical partitioning
partitioning objectives:
objectives: area
area sensitivity,
sensitivity, functional
functional and
and
clocking
clocking structure,
structure, critical
critical timing-path
timing-path awareness,
awareness, matching
matching capabilities
capabilities
of
of block
block placer
placer
zz block
block placement:
placement: largely
largely unsolved
unsolved issue
issue
zz unclear
unclear whether
whether packing-centric
packing-centric or
or connectivity-centric
connectivity-centric approaches
approaches are
are best
best
Andrew B. Kahng
81
Outline
z Technology trends
zz performance
Andrew B. Kahng
82
41
Cell-Based P&R: Classic Context
z Architecture design
zz golden
golden microarchitecture
microarchitecture design,
design, behavioral
behavioral model,
model, RT-level
RT-level structural
structural
HDL
HDL passed
passed to
to chip
chip planning
planning
zz cycle
cycle time
time and
and cycle-accurate
cycle-accurate timing
timing boundaries
boundaries established
established
zz hierarchy
hierarchy correspondences
correspondences (structural-functional,
(structural-functional, logical
logical (schematic)
(schematic)
and
and physical)
physical) well-established
well-established
z Chip planning
zz hierarchical
hierarchical floorplan,
floorplan, mixed
mixed hard-soft
hard-soft block
block placement
placement
zz block
block context-sensitivity:
context-sensitivity: no-fly,
no-fly, layer
layer usage,
usage, other
other routing
routing constraints
constraints
zz route
route planning
planning of
of all
all global
global nets
nets (control/data
(control/data signals,
signals, clock,
clock, P/G)
P/G)
zz induces
induces pin
pin assignments/orderings,
assignments/orderings, hard
hard (partial)
(partial) pre-routes,
pre-routes, etc.
etc.
z Individual block design -- various P&R methodologies
z Chip assembly -- possibly implicit in above steps
z What follows: qualitative review of key goals, purposes
Andrew B. Kahng
83
Placement Directions
z Global placement
zz engines (analytic, top-down partitioning based, (iterative annealing
based) remain the same; all support “anytime” convergent solution
zz becomes more hierarchical
zz block
block placement,
placement, latch
latch placement
placement before
before “cell
“cell placement”
placement”
zz support placement of partially/probabilistically specified design
z Detailed placement
zz LEQ/EEQ substitution
zz shifting, spacing and alignment for routability
zz ECOs for timing, signal integrity, reliability
zz closely tied to performance analysis backplane (STA/PV)
zz support incremental “construct by correction” use model
Andrew B. Kahng
84
42
Function of a UDSM Router
z Ultimately responsible for meeting specs/assumptions
zz slew, noise, delay, critical-area, antenna ratio, PSM-amenable …
z Checks performability throughout top-down physical impl.
zz actively understands, invokes analysis engines and macromodels
z Many functions
zz circuit-level IP generation: clock, power, test, package substrate
routing
zz pin assignment and track ordering engines
zz monolithic topology optimization engines
zz owns key DOFs: small re-mapping, incremental placement,
device-level layout resynthesis
zz is hierarchical, scalable, incremental, controllable, well-
characterized (well-modeled), detunable (e.g., coarse/quick
routing), ...
Andrew B. Kahng
85
Out-of-Box Uses of Routing Results

z Modify floorplan
zz floorplan
floorplan compaction,
compaction, pin
pin assignments
assignments derived
derived from
from top-level
top-level route
route
planning
planning
z Determine synthesis constraints
zz budgets
budgets for
for intra-block
intra-block delay,
delay, block
block input/output
input/output boundary
boundary conditions
conditions
z Modify netlist
zz driver
driver sizing,
sizing, repeater
repeater insertion,
insertion, buffer
buffer clustering
clustering
z Placement directives for block layout
zz over-block
over-block route
route planning
planning affects
affects utilization
utilization factors
factors within
within blocks
blocks
z Performance-driven routing directives
zz wire
wire tapering/spacing/shielding
tapering/spacing/shielding choices,
choices, assumed
assumed layer
layer assignments,
assignments,
etc.
etc.
Andrew B. Kahng
86
43
Routing Directions
z Cost functions and constraints
zz rich
rich vocabulary,
vocabulary, powerful
powerful mechanisms
mechanisms to
to capture,
capture, translate,
translate,
enforce
enforce
z Degrees of freedom
zz wire
wire widths/spacings,
widths/spacings, shielding/interleaving,
shielding/interleaving, driver/repeater
driver/repeater sizing
sizing
zz router empowered to perform small logic resyntheses
router empowered to perform small logic resyntheses
z “Methodology”
zz carefully
carefully delineated
delineated scopes
scopes of
of router
router application
application
zz instance
instance complexities remain tractable due
complexities remain tractable due to
to hierarchy
hierarchy and
and
restrictions
restrictions (e.g.,
(e.g., layer
layer assignment
assignment rules)
rules) that
that are
are part
part of
of the
the
methodology
methodology
z Change in search mechanisms
zz iterative
iterative ripup/reroute
ripup/reroute replaced
replaced by
by “atomic
“atomic topology
topology synthesis
synthesis
utilities”:
utilities”: construct
construct entire topologies to
entire topologies to satisfy
satisfy constraints
constraints in
in
arbitrary
arbitrary contexts
contexts
z Closer alignment with full-/automated-custom view
zz “peephole
“peephole optimizations”
optimizations” of
of layout
layout are
are the
the natural
natural extensions
extensions of
of
Motorola
Motorola CELLERITY,
CELLERITY, IBM
IBM CM5,
CM5, etc.
etc. methodologies
methodologies Andrew B. Kahng
87
Noise Sources
z Analog design concerns are due physical noise sources
zz because of discreteness of electronic charge and stochastic
nature of electronic transport processes
zz example: thermal noise, flicker noise, shot noise
z Digital circuits due to large, abrupt voltage swings,
create deterministic noise which is several orders of
magnitude higher than stochastic physical noise
zz still digital circuits are prevalent because hey are inherently
immune to noise
z Technology scaling and performance demands made
noisiness of digital circuits a big problem
Andrew B. Kahng
88
44

Modern Physical Design: Modern Physical Design

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Modern Physical Design: Modern Physical Design

Transféré par

Droits d'auteur :

Formats disponibles

Modern Physical Design:

Andrew B. Kahng UCLA

Majid Sarrafzadeh Northwestern

Overview of the Tutorial

Majid Sarrafzadeh Northwestern

Overall Roadmap Technology

Technology Scaling Trends

Technology Extrapolation Sensitivity

Deep- Submicron Interconnect

Estimated Number of Nets At-Risk 16

New Materials Implications

Technical Issues in UDSM Design

Spec RTL/code Gates/Cells Xtrs Masks Chip

SW design Logic Analog and Detailed Mask

Test Test logic Test Pattern Chip test &

Start of Concept Phase Release to Manufacturing

ASSP Design Productivity +27% Annually

Guiding Philosophy in the Back-End

Defect-related Yield Loss

Critical Area for Shorts

Critical Area for Short Circuits

z Routing tools do not always optimize for spacing

Data Aspects of Post Layout Optimization

z Jogging increases amount of data significantly

z Pre routing specification

Opportunities for Via Strengthening

z Add cut holes where possible

before spacing after spacing

z Many different kinds of delay/area optimization are

Area Feasible X You are here

Min delay Required Delay Delay

W1 Circuits of constant delay:15ns

Bound 1 New guess delay is too slow so

Required guess. New feasible region is

guess. New feasible

Constant cost Bou region is below new

Circuit delay affected

direction D2 to reduce cost

δ2 = slowdown of T δ1= speedup of T

z Increase Xtr on critical path with largest per unit

Short Circuit Power Optimization

Short circuit power burned

Starting Point. Feasible

Required delay Delay

Is the Union of both

z Optimal curve is envelope of curves

zz TPP conducts <=> N11 conducts. Replace TPP with N11

z Trade off drive-capability/logic-levels

Custom Methodology in ASIC(?) / COT

z How much is on the table w.r.t. performance?

z With sub-wavelength lithography:

Custom Methodology in ASIC(?) / COT

The last seems to be the lowest-hanging fruit for ASIC

Custom Methodology in ASIC(?) / COT

z “Layout or re-layout on the fly” is an element of

System System System System System

Performance Optimization Tool Flow

Floor Planning Logic Synthesis

Global Routing Detailed Routing

EM Power Timing Signal Integrity Clock

Ultra Deep Submicron Timing

z Everything we do is ultimately aimed at a predictable,

Problems With Physical Hierarchy