A New Hybrid Asymmetric Multilevel Inverter with
Reduced Number Of Switches
N.Prabaharan
School of Electrical Engineering
VIT University,
Vellore, India
prabaharan.nataraj@gmail.com
Abstract—This paper proposes a new hybrid asymmetric
multilevel inverter for generating the higher number of levels
with reduced number of power semiconductor switches. The
hybrid asymmetric multilevel inverter consists of full bridge
inverter and reduced switch inverter topology. The reduced
switch inverter topology can generate 13-level output voltage
without utilizing full bridge inverter. When the full bridge
inverter is combined with reduced switch inverter topology, it
can generate the 27-level output voltage. Sinusoidal pulse width
modulation technique is used to trigger the multilevel inverter
switches and to achieve high-quality output voltage with lesser
total harmonic distortion. The performance of proposed
multilevel inverter is tested by MATLAB/SIMULINK and
validated the results with different parameters. The output
voltage level of proposed multilevel inverter is satisfied IEEE519
harmonic standard without using any passive filters.
Keywords—multilevel inverter; pulse width modulation;
reduced switch MLI; asymmetric; total harmonic distortion
I. INTRODUCTION
Multilevel inverters have been focused for decades due to
important features for generating the high-quality output
voltage, lower switching stress, utilizing for high
voltage/power applications [1]. The Multilevel inverter has
rapidly increased research topic in power electronics
applications such as electric hybrid vehicle, renewable energy
sources, Flexible AC Transmission System (FACTS) and
electric drives [1,2]. Nowadays many industries are used
conventional MLI configurations such as Diode Clamped
Multilevel Inverter (DCMLI), Flying Capacitor Multilevel
Inverter (FCMLI) and Cascaded H-Bridge Multilevel Inverter
(CHBMLI) in Mega Watt range [2]. But the main problem in
DCMLI and FCMLI has high number of additional
components such as blocking diodes, clamping capacitors and
DC-link capacitors when compared to conventional CHBMLI
[1,2]. The balancing of each capacitor is the difficult task and
also design package is not easier because of utilizing more
number of capacitors [3]. But, CHBMLI free from clamping
diodes and clamping capacitors but high number of switches is
utilized for generating particular output voltage level.
Nowadays, hybrid asymmetric multilevel inverters are
involving to generate the higher number of output voltage level
with the lesser number of switches. Generally, asymmetric
MLI generates a high number of voltage levels when compared
with symmetric MLI. Many topologies are reported in hybrid
978-1-4673-8888-7/16/$31.00 ©2016 IEEE
K.Palanisamy
School of Electrical Engineering
VIT University
Vellore, India
kpalanisamy@vit.ac.in
MLI so far [3]. The developing of hybrid MLI topology is the
main goal to achieve higher number of levels. Most of the
hybrid topology utilizes a very high value of DC source
because topologies are operated at the asymmetric condition.
New hybrid multilevel inverter topologies can be developed
through the controllable degree of freedom of the DC voltage
proportional relation [4]. In [5], a hybrid topology utilizes a
reduced switch topology with secondary windings are cascaded
to achieve high output voltage range. But the drawback is the
utilization of multiple transformers because cost and size of
transformers are high. In [6], Packed U-cell MLI is connected
with CHBMLI in three-phase condition. The topology is
operated at high voltage condition with different transient
conditions. In [7], diode bypassed transistor voltage source
MLI is introduced and it is hybridized with CHBMLI in [8].
The value of CHBMLI is the next consecutive geometric
progression of reduced switch MLI. So, the CHBMLI have
more peak inverse voltage and more stress on the switches. In
[9] transistor clamped MLI topology is combined with
conventional CHBMLI to generate higher voltage level. In [10,
11] requires the high number of DC link capacitors for
achieving required output voltage level. In [12] a bidirectional
switch is connected between two CHBMLI units and it utilized
for fault recovering operation. In [13], a comparative analysis
is carried out for symmetric and asymmetric conditions with
the same number of switches. In [14], a combination of
CHBMLI with double level circuit is utilized for photovoltaic
application. Multiple DC source MLIs are utilized for
photovoltaic and FACTS applications [15-17].
This paper proposes a new hybrid asymmetric multilevel
inverter topology that can generate the higher number of output
voltage levels with the lesser number of power electronics
components and lower DC source value. The value of DC
source in H-Bridge is chosen based on the lowest value of DC
sources in reduced switch topology. The DC source value is
considered as half of the value of lowest value of DC in
reduced switch MLI. Sinusoidal pulse width modulation
(SPWM) with Phase Disposition carrier arrangement is utilized
for generating a 27-level output voltage and the results are
obtained. In the proposed topology, two switches are operated
at the fundamental switching frequency and remaining
switches are operated at high switching frequency. Also, peak
inverse voltage of the proposed MLI is less when compared to
conventional MLI topologies. Comparative study is carried out
with different conventional topologies to prove the proposed TABLE 1 SWITCHING TABLE FOR GENERATING 27-LEVEL OUTPUT VOLTAGE
topology utilizes less number of switches.
Levels Switching states
This paper is organized as follows: Section 2 and section 3
deals with the proposed asymmetric MLI operation and the 0 S1,S2,S3,S4,S7
comparative study for the proving the topology in various 1 S1,S3,S5,S9,S12
aspects respectively. Section 4 and section 5 deals with 2 S1,S6,S7,S10,S12
simulation results and conclusion respectively.
3 S1,S6,S7,S9,S12
II. PROPOSED HYBRID ASYMMETRIC MULTILEVEL 4 S1,S7,S8,S10,S12
INVERTER 5 S1,S7,S8,S9,S12
The proposed hybrid asymmetric multilevel inverter is the 6 S1,S5,S7,S10,S12
combination of reduced switch MLI and CHBMLI. The 7 S1,S5,S7,S9,S12
proposed topology utilizes five DC source with three different
8 S1,S4,S6,S10,S12
combinations. It can generate a 27-level output voltage with
13-level in a positive cycle, 13-level in a negative cycle and 9 S1,S4,S6,S9,S12
zero voltage level using 10 unidirectional switches and 2 10 S1,S4,S8,S10,S12
bidirectional switches. Fig. 1 shows the circuit diagram of 11 S1,S4,S8,S9,S12
proposed multilevel inverter. The advantage of this topology is 12 S1,S4,S5,S10,S12
the generation of particular voltage level has different paths
because the DC sources are connected in different directions. 13 S1,S4,S5,S9,S12
In this topology, the pair of switches S1, S2 and S3, S4 cannot -1 S2,S4,S6,S10,S11
be turned on simultaneously, to avoid the short circuit. In 27- -2 S2,S5,S7,S10,S12
level output voltage, the even voltage levels are generated by -3 S2,S7,S8,S9,S12
using without conventional CHBMLI whereas odd levels are
generated by using with CHBMLI which is clearly represented -4 S2,S7,S8,S10,S12
in Fig. 4.b. -5 S2,S7,S8,S10,S11
-6 S2,S6,S7,S10,S12
Table 1 shows the different modes of operation for
proposed multilevel inverter. Table 2 shows the generalized -7 S2,S3,S5,S9,S12
formulas for proposed MLI based on a number of modules and -8 S2,S3,S5,S10,S12
also a number of output voltage levels. -9 S2,S3,S5,S10,S11
-10 S2,S3,S8,S10,S12
-11 S2,S3,S8,S10,S11
-12 S2,S3,S6,S10,S12
-13 S2,S3,S6,S10,S11

TABLE 2 GENERALIZED FORMULA FOR PROPOSED MLI TOPOLOGY

Based on reduced Based on number of level

Parameters
switch module (n) (NL)

Number of −3
4× +1 −1
DC sources 4
Number of
voltage level 2 × (12 × ) + 1

Number of
3×( − 1)
10 × +4 +1
switches 6

Number of
3×( − 1)
8× +4 −1
driver circuit 6

Fig. 1. Proposed hybrid asymmetric MLI

 III. COMPARATIVE STUDY
A comparative study is mandatory to prove the capability
of the proposed asymmetric MLI topology. The proposed
topology is compared with different types of conventional MLI
such as NPCMLI, FCMLI and CHBMLI. Table 3 shows the
passive filters. From the FFT plot, each harmonic order of the
proposed MLI is less than 5% and the overall voltage THD is
less than 8%.
10

required component details for generating the desired output

Amplitude in volts
5
voltage level. The calculation of components for all topology is
based 27-level output voltage. Also, the proposed topology
0
requires 12 switches but in the table it represents 14 switches.
Because the topology utilizes two bidirectional switches. The
-5
creation of bidirectional switch is the combination of two
switches with emitter coupled. But, the bidirectional switch
-10
requires only one diver circuit. From the table 3, it is clearly
shows that the proposed asymmetric MLI utilizes less number 0 0.005 0.01 0.015 0.02
of components and cost effective. Time in seconds
(a)
TABLE 3 COMPARISION OF COMPONENTS WITH CONVENTIONAL MLIS 6

Voltage in volts (1:50) &

4

Current in amps
Parameters NPCMLI FCMLI CHBMLI Proposed 2

0
Number of diodes 650 - - -
-2

-4
Number of capacitors - 325 - -
-6

Number of voltage level 27 27 27 27 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time in seconds
(b)
Number of switches 52 52 52 14 Fig. 2. (a) Phase Disposition carrier arragement (b) output voltage level for
proposed hybrid asymmetric MLI
Number of driver 52 52 12
52
circuit Fundamental (50Hz) = 325.1 , THD= 4.28%
100
Mag (% of Fundamental)

Fundamental (50Hz) = 325.1 , THD= 4.28%

3
Number of DC sources 1 1 13 5
Mag (% of Fundamental)

80 2.5

60 1.5

1
IV. SIMULATION RESULTS 40 0.5

0
0 50 100 150 200 250 300
The proposed multilevel inverter is designed for 27-level 20 Harmonic order

output voltage and the operation is tested with

MATLAB/SIMULINK. The proposed MLI operates at 0
0 50 100 150 200 250
Sinusoidal Phase Disposition PWM technique. Phase Harmonic order
Disposition states that the all carriers are each in phase with
sane frequency and the same amplitude. Fig. 2.a shows the (a)
phase disposition carrier arrangement for 27-level output level. 300 Proposed MLI output
Reduced switch MLI output
Fig. 3 shows the switching signals for 12 switches. The 200 CHBMLI outupt
switches S1 and S2 operate at the fundamental switching
Voltage in volts

frequency and remaining switches are operated at the high 100

switching frequency (3000 Hz). The following parameters are
0
used in a simulation for testing proposed MLI in
MATLAB/SIMULINK. The parameters are Vdc1=Vdc2=100 -100
V, Vdc3=Vdc4=50 V, Vdc5=25 V, carrier switching frequency
(fs) = 3000 Hz, main switching frequency (fm) = 50 Hz, -200

resistive inductive load (RL) = 422.5 Ω and 25 mH. Fig. 2.b -300
shows the output voltage level and output current waveform for 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
proposed hybrid asymmetric multilevel inverter without Time in seconds
(b)
passive filters. Fig. 4.a shows the simulation FFT plot for
Fig. 4. (a) Phase Disposition FFT plot and (b) Different ouput voltages for
proposed hybrid asymmetric multilevel inverter without proposed hybrid asymmetric MLI
S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1

1
0
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time in seconds
Fig. 3. PWM Switching singal for proposed hybrid asymmetric MLI

[7] A. Al-Judi and E. Nowicki, “Cascading of diode bypassed transistor-

V. CONCLUSION
This paper presented a new hybrid asymmetric multilevel
inverter topology which can generate a 27-level output voltage [8]
with less number of power semiconductor switches. The
operation of MLI is explained with different modes of
operation. The proposed MLI utilized less number of on state [9]
switches for generating a particular voltage level. The main
advantage of this topology is the utilization of unequal DC
sources where easily it can be interconnected with renewable
energy sources like solar, wind, biomass etc. In future, the [10]
proposed inverter would be tested with FACTS devices such as
DVR or DSTATCOM. The total harmonic distortion of the
proposed inverter is 4.39% while using sinusoidal Phase [11]
Disposition PWM technique without a passive filter in output.
A comparative study is carried out with conventional MLI
topologies to prove that the proposed MLI utilizes fewer [12]
components. An experimental setup for the proposed
asymmetric MLI topology can be carried out in future.
REFERENCES [13]
[1] J. Rodriguez,, J. Sheng Lai, and F.Z.Peng,“A multilevel inverters:
survey of topologies, control and applications,” IEEE Trans. Ind.
Electron., vol. 49, no. 4, pp. 724-738, 2002
[14]
[2] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, “A
survey on cascaded multilevel inverters,” IEEE Trans. Ind. Electron.,
vol. 57, no. 7, pp. 2197–2206, 2010.
[3] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, [15]
“Multilevel Inverter Topologies With Reduced Device Count: a
Review,” IEEE Trans. Power Electron., vol. 31, no. 1, pp. 135–151,
2015.
[16]
[4] Z. Jinghua and L. Zhengxi, “Research on hybrid modulation strategies
based on general hybrid topology of multilevel inverter,” in SPEEDAM
2008 - International Symposium on Power Electronics, Electrical
Drives, Automation and Motion, 2008, pp. 784–788.
[17]
[5] Y. Suresh and A. kumar Panda, “Investigation on stacked cascade
multilevel inverter by employing single-phase transformers,” Eng. Sci.
Technol. , an Int. J., vol. 19, pp. 894–903, 2016.
[6] P. Lezana and R. Aceitón, “Hybrid multicell converter: Topology and
modulation,” IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 3938–3945,
2011.
voltage-source units in multilevel inverters,” IET Power Electron., vol.
6, no. 3, pp. 554–560, 2013.
R. S. Alishah, D. Nazarpour, S. H. Hosseini, and M. Sabahi, “New
hybrid structure for multilevel inverter with fewer number of
components for high-voltage levels,” IET Power Electron., vol. 7, no. 1,
pp. 96–104, 2014.
R. S. Alishah, D. Nazarpour, S. H. Hosseini, and M. Sabahi, “Novel
multilevel inverter topologies for medium and high-voltage applications
with lower values of blocked voltage by switches,” IET Power Electron.,
vol. 7, no. 12, pp. 3062–3071, 2014.
M. Kaliamoorthy, V. Rajasekaran, I. G. C. Raj, and L. H. T. Raj,
“Generalised hybrid switching topology for a single-phase modular
multilevel inverter,” IET Power Electron., vol. 7, no. 10, pp. 2472–2485,
2014.
J. S. Choi and F. S. Kang, “Seven-level PWM inverter employing series-
connected capacitors paralleled to a single DC voltage source,” IEEE
Trans. Ind. Electron., vol. 62, no. 6, pp. 3448–3459, 2015.
F. Wu, X. Li, F. Feng, and H. B. Gooi, “Modified cascaded multilevel
grid-connected inverter to enhance European efficiency and several
extended topologies,” IEEE Trans. Ind. Informatics, vol. 11, no. 6, pp.
1358–1365, 2015.
N. Prabaharan, K. Palanisamy, “Comparative analysis of symmetric and
asymmetric reduced switch MLI topologies using unipolar pulse width
modulation strategies” IET Power Electronics, 2016. DOI.:10.1049/iet-
pel.2016.0283.
N. Prabaharan, K. Palanisamy, “Analysis and integration of multilevel
inverter configuration with boost converters in a photovoltaic system”.
Energy Conversion and Management, Vol. 128(C), pp. 327-342, 2016.
DOI.: 10.1016/j.enconman.2016.09088.
F.Jiang, C. Tu, Z. Shuai, M. Cheng, Z. Lan, and F. Xiao, “Multilevel
Cascaded-Type Dynamic Voltage Restorer With Fault Current-Limiting
Function ” IEEE Transactions On Power Delivery, Vol. 31, No. 3, 2016.
K. Raghavendra Reddy, V. B. Borghate, P. M. Meshram, H. M.
Suryawanshi, and S. Sabyasachi, “A Three Phase Hybrid Cascaded
Modular Multilevel Inverter for Renewable Energy Environment” IEEE
Transactions On Power Electronics. DOI 10.1109/TPEL.2016.2542519.
F.Z. Peng, Y. Liu, S. Yang, S. Zhang, D. Gunasekaran, and U. Karki,
“Transformer-Less Unified Power-Flow Controller Using the Cascade
Multilevel Inverter” IEEE Transactions on Power Electronics, Vol. 31,
No. 8, 2016.