SYS 1/25

SYS 2/25
SYS 3/25
SYS 4/25
SYS 5/25
SYS 6/25
SYS 7/25
SYS 8/25
SYS 9/25
SYS 10/25
SYS 11/25
SYS 12/25
SYS 13/25
SYS 14/25
SYS 15/25
SYS 16/25
SYS 17/25
SYS 18/25
SYS 19/25
SYS 20/25
SYS 21/25
SYS 22/25
SYS 23/25
SYS 24/25
SYS 25/25
IMG 1/29
IMG 2/29
IMG 3/29
IMG 4/29
IMG 5/29
IMG 6/29
IMG 7/29
IMG 8/29
IMG 9/29
IMG 10/29
IMG 11/29
IMG 12/29
IMG 13/29
IMG 14/29
IMG 15/29
IMG 16/29
IMG 17/29
IMG 18/29
IMG 19/29
IMG 20/29
IMG 21/29
IMG 22/29
IMG 23/29
IMG 24/29
IMG 25/29
IMG 26/29
IMG 27/29
IMG 28/29
IMG 29/29
LGC 1/24
LGC 2/24
LGC 3/24
LGC 4/24
1.8V generation

LGC 5/24
LGC 6/24
24V CHK H: 24V OK L: Door open

+5VSW generation

LGC 7/24
LGC 8/24
LGC 9/24
LGC 10/24
LGC 11/24
LGC 12/24
LGC 13/24
LGC 14/24
LGC 15/24
LGC 16/24
LGC 17/24
LGC 18/24
LGC 19/24
LGC 20/24
LGC 21/24
LGC 22/24
LGC 23/24
LGC 24/24
SLG 1/18
SLG 2/18
SLG 3/18
SLG 4/18
SLG 5/18
SLG 6/18
SLG 7/18
SLG 8/18
SLG 9/18
SLG 10/18
SLG 11/18
SLG 12/18
SLG 13/18
SLG 14/18
SLG 15/18
SLG 16/18
SLG 17/18
SLG 18/18
CCD 1/3
CCD 2/3
CCD 3/3
SRAM 1/1
ADU 1/1
FIL 1/1
FAX 1/10
FAX 2/10
FAX 3/10
FAX 4/10
FAX 5/10
FAX 6/10
FAX 7/10
FAX 8/10
FAX 9/10
FAX 10/10
MDM 1/2
MDM 2/2
FAX POW 1/1
NCU-US 1/2
NCU-US 2/2
NCU-EU 1/2
NCU-EU 2/2
NCU-JP 1/2
NCU-JP 2/2
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC48

Pin Use setting of port I/O Description Connection/Use Logic Signal

1 VDD(2.5V) - -
2 CS11/PK7 O CS output 11 / General-purpose output port K Lazulite CS L: Chip selection LZCS-0T
3 VDD(3.3V) - -
4 CS9/PK5 O CS output 9 / General-purpose output port K PM-1100(K) CS L: Chip selection PMCS4-0T
Debug jig external
5 CS10/PK6 O CS output 10 / General-purpose output port K L: Chip selection DEBCS-0T
latch CS
6 GND - -
7 CS8/PK4 O CS output 8 / General-purpose output port K PM-1100(C) CS L: Chip selection PMCS3-0T
8 INTO3/PK3 I/O Interrupt output 3 / General-purpose output port K CPU INTPx H: Interrupted INT6-1T
9 INTO2/PK2 I/O Interrupt output 2 / General-purpose output port K CPU INTPx H: Interrupted INT5-1T
10 INTO1/PK1 I/O Interrupt output 1 / General-purpose output port K CPU INTPx H: Interrupted SSYSINT-1T
11 INTO0/PK0 I/O Interrupt output 0 / General-purpose output port K CPU INTPx H: Interrupted SCMDINT-1
Lockable WR output (16bit/8bitH/8bitL can be
12 MWR O NVRAM WR L: Write MWR-0T
selected with the register.)
13 CS7/PC7 O CS output / General-purpose output port C PM-1100(M) CS L: Chip selection PMCS2-0T
14 CS6/PC6 O CS output / General-purpose output port C PM-1100(Y) CS L: Chip selection PMCS1-0T
15 CS5/PC5 O CS output / General-purpose output port C Opal CS L: Chip selection OPALCS-0T
16 CS4/PC4 O CS output / General-purpose output port C IPC CS L: Chip selection IPCCS-0T
17 CS3/FRAM/PC3 O CS output / FRAMCS / General-purpose output NVRAM CS L: Chip selection NVCS-0T
CS output (SRAM address) / General-purpose
18 CS2/PC2 O SRAM CS L: Chip selection SRAMCS-0T
output port C
19 CS1/PC1 O CS output (EPROM) EPROM CS L: Chip selection DLBDCS-0T
20 CS0/PC0 O CS output (FROM) FROM CS L: Chip selection FROMCS-0T
21 TDO O ASIC test pin (NC) ASIC test pin (NC) -
22 TMS I ASIC test pin (NC) ASIC test pin (NC) -
23 TCK I ASIC test pin (NC) ASIC test pin (NC) -
24 GND(EM) - -
25 CLKIN I Input clock OSC (34 MHz） - EXCLK-1T
26 VDD(3.3V) - -
27 VDD(2.5V) - -
28 GND - -
29 TRST I ASIC test pin (NC) -
Developer unit motor
30 TO11/PD7 O Timer output (50% duty fixed) DVMCK-1T
clock
Paper feeding motor
31 TO10/PD6 O Timer output (50% duty fixed) FDMCK-1T
clock

1/9
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC48

Pin Use setting of port I/O Description Connection/Use Logic Signal

32 TO9/PD5 O Timer output (50% duty fixed) Fuser unit motor clock FSMCK-1T
33 TO8/PD4 O Timer output (50% duty fixed) Polygonal motor clock PMCK-1T
34 TO7/PD3 O Timer output / General-purpose port Preliminary output - -
Toner adhering L: When color toner
35 TO6/PD2 O Timer output / General-purpose port amount sensor K, is detected H: TNLED-0T
color switching signal When black toner is
36 INTPO5/PD1 O Interrupt output 5 / General-purpose port D CPU INTPｘ H: Interrupted INT8-1T
37 INTPO4/PD0 O Interrupt output 4 / General-purpose port D CPU INTPｘ H: Interrupted INT7-1T
D/A converter data output / General-purpose I/O
38 DACDO/PE7 I/O D/A converter DI DACOUT-1T
port E serial data output
D/A converter clock output / General-purpose I/O
39 DACCK/PE6 I/O D/A converter SK DACCLK-1T
port E clock output
40 DACLD/PE5 I/O D/A converter load output / General-purpose I/O D/A converter LD DACLD-1T
CSI for serial EEPROM / General-purpose I/O port YELLOW PU
41 EEPRMCS1/PE4 I/O L: Connected YPUCNT-0T
E connection signal
Data output for serial EEPROM / General-purpose BLACK cleaner limit
42 EEPRMDO/PE3 I/O H: Limit KCLNLT-0TA
I/O port E detection SW
Data input for serial EEPROM / General-purpose Registration motor L: Registration
43 EEPRMDI/PE2 I STMTFL-0T
I/O port E driver motor error occurs
Clock output for serial EEPROM / General- L: Backup area
44 EEPRMCK/PE1 I/O SRAM area switching AREACH-0T
purpose I/O port E H: Normal
45 EEPRMCS0/PE0 I/O CS0 for serial EEPROM / General-purpose I/O Preliminary port -
46 TDI I ASIC test pin (NC) ASIC test pin (NC) -
General-purpose I/O port / Serial communication BLACK PU connection
47 PB7/SIOCLK I L: Connected KPUCNT-0T
reference input CLK signal
CYAN PU connection
48 PB6/TI1 I General-purpose I/O port / Timer reference CLK1 L: Connected CPUCNT-0T
signal
MAGENTA PU
49 PB5/TI0 I General-purpose I/O port / Timer reference CLK0 L: Connected MPUCNT-0T
connection signal
50 RW/PB4 I R/W input signal / General-purpose I/O port CPU R/W L: Write H: Read R/W-0T
51 BUSOE/PB3 O BUS OE signal / General-purpose I/O port IPC Bus Buffer OE L: Enable H: OFF BUSOE-0T
52 VDD(3.3V) - -
53 GND - -
54 VDD(2.5V) - -
55 GND - -
56 VDD(3.3V) - -

2/9
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC48

Pin Use setting of port I/O Description Connection/Use Logic Signal

57 GND - -
BUS DIRECTION signal 0 / General-purpose I/O IMC Area Bus Buffer L: IMCP => CPU
58 BUSDIR0/PB1 O BUSDIR-0T
port Direction H: CPU => IMCP
BUS DIRECTION signal 1 / General-purpose I/O NRRAM Area Bus
59 BUSOE1/PB2 O L: Enable H: OFF BUSOE1-0T
port Buffer OE
60 GND - -
61 WR_P/PB0 O Delay WR signal / General-purpose I/O port PM-1100(YMCK) WR L: PM1100 write EXWR-0T
62 TEST3 I ASIC test pin (NC) ASIC test pin (NC) -
↑: Latch operation
63 PIFCKB/PJ7 I/O Output data clutch clock B PFP I/F CKB PIFCKB-1T
by external latch
↑: Latch operation
64 PIFCKA/PJ6 I/O Output data clutch clock A PFP I/F CKA PIFCKA-1T
by external latch
L: External input
65 SCSWB/PJ5 I/O Input data enable B PFP I/F SCSWB switching SCSWB-0T
H: Normal
L: External input
66 SCSWA/PJ4 I/O Input data enable A PFP I/F SCSWA switching SCSWA-0T
H: Normal
67 PIFDI11/PJ3 I PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F SIZE3 PIFDI[11]
68 PIFDI10/PJ2 I PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F SIZE2 PIFDI[10]
69 PIFDI9/PJ1 I PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F SIZE1 PIFDI[9]
70 PIFDI8/PJ0 I PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F SIZE0 PIFDI[8]
71 PIFDI7/PI7 I/O PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F DRV7/RET7 PIFDI[7]
72 PIFDI6/PI6 I/O PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F DRV6/RET6 PIFDI[6]
73 PIFDI5/PI5 I/O PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F DRV5/RET5 PIFDI[5]
74 PIFDI4/PI4 I/O PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F DRV4/RET4 PIFDI[4]
75 PIFDI3/PI3 I/O PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F DRV3/RET3 PIFDI[3]
76 PIFDI2/PI2 I/O PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F DRV2/RET2 PIFDI[2]
77 PIFDI1/PI1 I/O PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F DRV1/RET1 PIFDI[1]
78 PIFDI0/PI0 I/O PFP/LCF I/F I/O port / General-purpose I/O port K PFP I/F DRV0/RET0 PIFDI[0]
79 HT2ON/PG7 O Heater ON signal / General-purpose output port G Press Roller Heater L: LAMP ON PHON-0T
80 TMC1 I ASIC test pin (NC) ASIC test pin (NC) -
81 VDD(2.5V) - -
82 GND(EM) - -
83 VDD(3.3V) - -
84 TMC2 I ASIC test pin (NC) ASIC test pin (NC) -

3/9
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC48

Pin Use setting of port I/O Description Connection/Use Logic Signal

Heat Roller Heater
85 HT1ON/PG6 O Heater ON signal / General-purpose output port G L: LAMP ON BHSON-0T
(side) On
Heat Roller Heater
86 HT0ON/PG5 O Heater ON signal / General-purpose output port G L: LAMP ON BHCON-0T
(Center) On
Thermistor comparison (comparator) signal /
87 THCMP/PG4 I/O Unused - -
General-purpose input port G
Thermistor (comparator input) / General-purpose Transfer belt unit
88 TH2/PG3 I/O L: Connected TBCNT-0T
I/O port G connection signal
Thermistor (comparator input) / General-purpose Drawer paper feeding L: No paper H:
89 TH1/PG2 I/O CS2FEED-1T
I/O port G JAM sensor 2 Paper exists
Thermistor (comparator input) / General-purpose Drawer paper feeding L: No paper H:
90 TH0/PG1 I/O CS1FEED-1T
I/O port G JAM sensor 1 Paper exists
Heater abnormal input / General-purpose input HTERR comparator
91 HTERR/PG0 I L: Error HTERR-0C
port G input
92 GND - -
L: No paper H:
2nd transfer clinging
93 PA3/TRG3/TI1 I Trigger input enable input port (noise elimination) Paper exists L: TB2JAM-1T
detection
Paper exists / H: No
L: No paper H:
94 PA2/TRG2/TI0 I Trigger input enable input port (noise elimination) Registration sensor RGSTS-1T
Paper exists
Color registration L: Toner pattern
95 PA1/TRG1 I Trigger input enable input port (noise elimination) RGREAR-1TA
sensor R detected
Color registration L: Toner pattern
96 PA0/TRG0 I Trigger input enable input port (noise elimination) RGFRNT-1TA
sensor F detected
LCF connection
97 TRG5/PF7 I/O Trigger input 5 / General-purpose I/O port F L: Connected LCCNT-0T
detection ON/OFF
L: No paper H:
98 TRG4/PF6 I/O Trigger input 4 / General-purpose I/O port F EXIT sensor EXTSW-1T
Paper exists
A/D converter data input / General-purpose I/O A/D converter 0, 1 DI
99 ADCDI/PF5 I ADCDI-1C
port F selection input
Unused (Connection
A/D converter data output / General-purpose I/O
100 ADCSTRB/PF4 I to other than - -
port F
ADCSTRB is not
A/D converter CS1 output / General-purpose I/O A/D converter 1 CS
101 ADCCS1/PF3 I/O - -
port F preliminary output

4/9
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC48

Pin Use setting of port I/O Description Connection/Use Logic Signal

A/D converter data output / General-purpose I/O A/D converter 0, 1 DO
102 ADCDO/PF2 I/O ADCDO-1T
port F selection output
103 ADCCK/PF1 I/O A/D converter clock output / General-purpose I/O A/D converter 0, 1 SK ADCCK-1T
104 ADCCS0/PF0 I/O A/D converter CS0 output / General-purpose I/O A/D converter 0 CS ADCCS0-0T
105 VDD(3.3V) - -
106 GND - -
107 GND - -
108 GND - -
109 VDD(2.5V) - -
110 CMD0/PH7 I SYS I/F CMD signal / General-purpose I/O port SYS I/F CMD CMD-0T
111 VDD(3.3V) - -
112 CBSY0/PH5 I SYS I/F CMD BSY signal / General-purpose I/O SYS I/F CBSY CBSY-0T
113 CERR0/PH6 O SYS I/F CMD ERR signal / General-purpose I/O SYS I/F CERR CERR-0T
114 GND - -
115 CACK0/PH4 O SYS I/F CMD ACK signal / General-purpose I/O SYS I/F CACK CACK-0T
116 STS0/PH3 O SYS I/F STS signal / General-purpose I/O port SYS I/F STS STS-0T
117 SERR0/PH2 I SYS I/F STS ERR signal / General-purpose I/O SYS I/F SERR SERR-0T
118 SBSY0/PH1 O SYS I/F STS BSY signal / General-purpose I/O SYS I/F SBSY SBSY-0T
119 SACK0/PH0 I SYS I/F STS ACK signal / General-purpose I/O SYS I/F SACK SACK-0T
120 TEST2 I ASIC test pin (NC) ASIC test pin (NC) -
121 CTRI I ASIC test pin (NC) ASIC test pin (NC) -
122 STPA7/TO4 O General-purpose output port / Timer output 4 High voltage clock HVTCLK-1T
General-purpose output port / Stepping motor 0
123 STPA6/IC02 O Tilt motor C enable TILTC-0T
Power current setting output 2
General-purpose output port / Stepping motor 0
124 STPA5/IC01 O Tilt motor M enable TILTM-0T
Power current setting output 1
General-purpose output port / Stepping motor 0
125 STPA4/IC00 O Tilt motor K enable TILTK-0T
Power current setting output 0
General-purpose output port / Reset output 0 /
126 STPA3/RST0/PH0D O Stepping motor 0 Tilt motor D phase TILT1-0T
D phase output
General-purpose output port / Enable output 0 /
127 STPA2/ENBL0/PH0C O Stepping motor 0 Tilt motor C phase TILT2-0T
C phase output

5/9
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC48

Pin Use setting of port I/O Description Connection/Use Logic Signal

General-purpose output port / Rotational direction
128 STPA1/DIR0/PH0B O output 0 / Stepping motor 0 Tilt motor B phase TILT3-0T
B phase output
General-purpose output port / Timer output 0 /
129 STPA0/TO0/PH0A O Stepping motor 0 Tilt motor A phase TILT0-0T
A phase output
130 STPB7/TO5 O General-purpose output port / Timer output 5 PFP/LCF clock PFPCK-1
General-purpose output port / Stepping motor 1 DRUM MOT current
131 STPB6/IC12 O DMSETI3-0T
Power current setting output 2 setting 2
General-purpose output port / Stepping motor 1 DRUM MOT current
132 STPB5/IC11 O DMSETI2-0T
Power current setting output 1 setting 1
General-purpose output port / Stepping motor 1 DRUM MOT current
133 STPB4/IC10 O DMSETI1-0T
Power current setting output 0 setting 0
General-purpose output port / Reset output 1 /
134 STPB3/RST1 O Stepping motor 1 Preliminary output
D phase output
135 GND(EM) - -
136 VDD(2.5V) - -
137 VDD(3.3V) - -
General-purpose output port / Enable output 1 /
DRUM MOT enable
138 STPB2/ENBL1 O Stepping motor 1 H: Enable DMEN-1T
output
C phase output
General-purpose output port / Rotational direction L: CW (equivalent to
DRUM MOT rotational
139 STPB1/DIR1 O output 1 / Stepping motor 1 function trial) H: DRMDIR-0T
direction
B phase output CCW
General-purpose output port / Timer output 1 /
140 STPB0/TO1 O Stepping motor 1 DRUM MOT clock DMCK-1T
A phase output
General-purpose output port / Timer output 4
141 STPC7/IC41 I/O Preliminary I/O - -
Power current setting output 1
General-purpose output port / Timer output 4
142 STPC6/IC40 I/O Preliminary I/O - -
Power current setting output 0
General-purpose output port / Stepping motor 2 TB MOT current
143 STPC5/IC21 I/O TBMSETI2-0T
Power current setting output 1 setting 1
General-purpose output port / Stepping motor 2 TB MOT current
144 STPC4/IC20 I/O TBMSETI1-0T
Power current setting output 0 setting 0

6/9
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC48

Pin Use setting of port I/O Description Connection/Use Logic Signal

General-purpose output port / Reset output 2 /
145 STPC3/RST2 I/O Stepping motor 2 Preliminary I/O -
D phase output
General-purpose output port / Enable output 2 /
146 STPC2/ENBL2 I/O Stepping motor 2 TB MOT enable output L: Enable TBMEN-1T
C phase output
General-purpose output port / Rotational direction
TBM MOT rotational
147 STPC1/DIR2 I/O output 2 / Stepping motor 2 L: CW H: CCW TBMDIR-0T
direction
B phase output
General-purpose output port / Timer output 2 /
148 STPC0/TO2 I/O Stepping motor 2 TB MOT clock output TBMCK-1T
A phase output
For K 45 cpm, clock
General-purpose output port / Timer output 5
149 STPD7/IC51 I/O switching signal VCLK45-0T
Power current setting output 1
(45 MHz ⇔ 60 MHz)
Pulse motor enable
General-purpose output port / Timer output 5 signal
150 STPD6/IC50 I/O H: Enable MTEN-1T
Power current setting output 0 (DRM-MOT, TRU-
MOT, EXIT-MOT,
General-purpose output port / Stepping motor 3
151 STPD5/IC31 I/O (ADU IC1) ADMSETI2-0T
Power current setting output 1
General-purpose output port / Stepping motor 3
152 STPD4/IC30 I/O (ADU IC0) ADMSETI1-0T
Power current setting output 0
General-purpose output port / Reset output 3/
153 STPD3/RST3 I/O Stepping motor 3 Unused - -
D phase output
General-purpose output port / Enable output 3 /
154 STPD2/ENBL3 I/O Stepping motor 3 ADU enable signal ADUEN-1T
C phase output
General-purpose output port / Rotational direction
155 STPD1/DIR3 I/O output 3 / Stepping motor 3 Unused - -
B phase output
General-purpose output port / Timer output 3 /
156 STPD0/TO3 I/O Stepping motor 3 ADU clock output ADUCK-1T
A phase output
157 PROTECT O Motor protection circuit output Unconnected -

7/9
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC48

Pin Use setting of port I/O Description Connection/Use Logic Signal

158 GND -
System CLK output (CPU synchronization,
159 SYSCLKO O CPU X'IN - -
Frequency dividing: 4)
160 VDD(3.3V) -
161 GND -
162 VDD(2.5V) -
163 GND - -
164 VDD(3.3V) - -
165 GND - -
166 GND - -
167 SDCLK I BUS control CLK CPU SDCLK - SDCLK-1TA
168 GND - -
169 A0 I Address bus CPU Address0 - A[0]
170 A1 I Address bus CPU Address1 - A[1]
171 A2 I Address bus CPU Address2 - A[2]
172 A3 I Address bus CPU Address3 - A[3]
173 A4 I Address bus CPU Address4 - A[4]
174 A5 I Address bus CPU Address5 - A[5]
175 A6 I Address bus CPU Address6 - A[6]
176 A7 I Address bus CPU Address7 - A[7]
177 A8 I Address bus CPU Address8 - A[8]
178 A9 I Address bus CPU Address9 - A[9]
179 A10 I Address bus CPU Address10 - A[10]
180 A11 I Address bus CPU Address11 - A[11]
181 A12 I Address bus CPU Address12 - A[12]
182 PL0/MON0 I/O General-purpose I/O port L / Sequence monitor 0 Preliminary I/O - -
183 PL1/MON1 I/O General-purpose I/O port L / Sequence monitor 1 Preliminary I/O - -
All ST motor reset L: Reset status
184 PL2/MON2 I/O General-purpose I/O port L / Sequence monitor 2 STMRST-0T
signal H: Normal operation
185 A16 I Address bus / General-purpose I/O port L CPU Address16 - A[16]
186 A17 I Address bus / General-purpose I/O port L CPU Address17 - A[17]
187 A18 I Address bus / General-purpose I/O port L CPU Address18 - A[18]
188 A19 I Address bus CPU Address19 - A[19]
189 GND - -
190 VDD(2.5V) - -
191 A20/PM0 I/O Address bus CPU Address20 - A[20]

8/9
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC48

Pin Use setting of port I/O Description Connection/Use Logic Signal

192 A21/PM1 I/O Address bus CPU Address21 - A[21]
193 A22/PM2 I/O Address bus CPU Address22 - A[22]
194 A23/PM3 I/O Address bus CPU Address23 - A[23]
195 D7 I/O Data bus CPU Data7 - D[7]
196 D6 I/O Data bus CPU Data6 - D[6]
197 D5 I/O Data bus CPU Data5 - D[5]
198 D4 I/O Data bus CPU Data4 - D[4]
199 D3 I/O Data bus CPU Data3 - D[3]
200 D2 I/O Data bus CPU Data2 - D[2]
201 D1 I/O Data bus CPU Data1 - D[1]
202 D0 I/O Data bus CPU Data0 - D[0]
203 TEST1 I ASIC test pin (NC) ASIC test pin (NC) -
204 CPURD I CPU read CPU Read L: Read EMRD-0T
205 CPUWRL I CPU write lower phase CPU Write L L: Write EMWR-0T
206 WAIT O Wait output CPU Wait L: Wait WAIT-0T
Chip selection input: For specifying ASIC internal
207 CSI I CPU CS0 L: Chip selection CS0-0T
register area
208 DLCS I Chip selection input: For PC downloading Fixed at H Unused -
209 BTCPUCS I Chip selection input: For boot area at power ON CPU CS2 L: Chip selection CS2-0T
210 ROM_SEL I ROM address replacement (for download jig) Download jig detection L: Jig detection ROMDT-0T
211 GND(EM) - -
212 RESET I Reset input Reset IC L: Reset MRST-0T
213 VDD(3.3V) - -
214 GND - -
215 GND - -
216 GND - -

9/9
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC49

Pin Use setting of port I/O Description Connection/Use Logic Signal

1 DVCC - VDD
2 A5 O Address Address bus - A[5]
3 A4 O Address Address bus - A[4]
4 A3 O Address Address bus - A[3]
5 A2 O Address Address bus - A[2]
6 A1 O Address Address bus - A[1]
7 A0 O Address Address bus - A[0]
FIFO over run /
8 PC5/SCK1 I/O I/O port (Schmitt input)/ LazuLite I/F under run detection YIR-0T
signal
FIFO over run /
I/O, I ,
9 PC4/SL1/SCL1 I/O port (Schmitt input)/ LazuLite I/F under run detection MR-0T
I/O
signal
FIFO over run /
I/O, O ,
10 PC3/SO1/SDA1 I/O port (Schmitt input)/ LazuLite I/F under run detection CIR-0T
I/O
signal
FIFO over run /
11 PC2/SCK0 I/O I/O port (Schmitt input)/ LazuLite I/F under run detection KIR-0T
signal
I/O, I , Monitor signal
12 PC1/SI0/SCL0 I/O port (Schmitt input)/ LazuLite I/F TSSTS-1T
I/O status detection
I/O, O , HSYNC error
13 PC0/SO0/SDA0 I/O port (Schmitt input)/ LazuLite I/F ERR-1T
I/O detection H: Error
14 P96/SDCLK O Output port / SDRAM clock SDCLK External Bus clock SDCLK-1T
Printing starts
15 P95/SDCKE O Output port / SDRAM clock enable LazuLite I/F MASIN-0T
L: Start
Forcible laser ON
16 P94/SDLUDQM O Output port / D8-D15 terminal SDRAM data enable LazuLite I/F LDON-0T
signal L: ON
Forcible laser OFF
17 P93/SDLLDQM O Output port / D0-D7 terminal SDRAM data enable LazuLite I/F LDOFF-0T
signal L: OFF
Laser enable signal
18 P92/SDCAS O Output port / SDRAM column address strobe LazuLite I/F LE-0T
L: Enabled
IC-Chip control
19 P91/SDRAS O Output port / SDRAM row address strobe LazuLite I/F EEPEN-0T
output enable L:
20 P90/SDWE O Output port / SDRAM write enable - - Preliminary port
21 DAVSS I D/A converter power terminal (0V) - -

1/7
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC49

Pin Use setting of port I/O Description Connection/Use Logic Signal

D/A output 1: D/A converter 1 analog voltage
22 DAOUT1 O - - Preliminary port
output terminal
D/A output 0: D/A converter 0 analog voltage
23 DAOUT0 O - - Preliminary port
output terminal
D/A converter power terminal and reference
24 DAVCC/DAREF - - -
voltage common terminal
25 PN3/AN11/ADTRG I Input-only port (Schmitt input)/Analog input11/ -
2nd high voltage
26 PN2/AN10 I Input-only port (Schmitt input)/Analog input10/ Analog input TR2MON-1T
electric current
27 PN1/AN9 I Input-only port (Schmitt input)/Analog input9/ K drum thermistor Analog input KDRTH-1TA
28 PN0/AN8 I Input-only port (Schmitt input)/Analog input8/ Color drum thermistor Analog input YDRTH-1TA
29 PM7/AN7/KI7 I Input-only port (Schmitt input)/Analog input7/ Auto toner sensor K Analog input KATSN-1T
30 PM6/AN6/KI6 I Input-only port (Schmitt input)/Analog input6/ Auto toner sensor C Analog input CATSN-1T
31 PM5/AN5/KI5 I Input-only port (Schmitt input)/Analog input5/ Auto toner sensor M Analog input MATSN-1T
32 PM4/AN4/KI4 I Input-only port (Schmitt input)/Analog input4/ Auto toner sensor Y Analog input YATSN-1T
1st high voltage
33 PM3/AN3/KI3 I Input-only port (Schmitt input)/Analog input3/ Analog input TR1MONK-1T
electric current
1st high voltage
34 PM2/AN2/KI2 I Input-only port (Schmitt input)/Analog input2/ Analog input TR1MONC-1T
electric current
1st high voltage
35 PM1/AN1/KI1 I Input-only port (Schmitt input)/Analog input1/ Analog input TR1MONM-1T
electric current
1st high voltage
36 PM0/AN0/KI0 I Input-only port (Schmitt input)/Analog input0/ Analog input TR1MONY-1T
electric current
A/D converter power terminal and reference power
37 AVSS/VREFL I - -
common terminal
A/D converter power terminal (0V) and reference
38 ACCC/VREFH I - -
power common terminal
39 PK7/TB3IN1/INTB I I/O port (Schmitt input)//Interrupt request B
40 PK6/TB3IN0/INTA I I/O port (Schmitt input)//Interrupt request A
FROM status signal
41 PK5/TB2IN1/INT9 I I/O port (Schmitt input)//Interrupt request 9 FROM FRMSTS-0T
L: Busy
42 PK4/TB2IN0/INT8 I I/O port (Schmitt input)//Interrupt request 8 EmeraLd I/F L: Interrupted INT8-1T
43 PK3/TB1IN1/INT7 I I/O port (Schmitt input)//Interrupt request 7 EmeraLd I/F L: Interrupted INT7-1T
44 PK2/TB1IN0/INT6 I I/O port (Schmitt input)//Interrupt request 6 EmeraLd I/F L: Interrupted INT6-1T
45 PK1/TB0IN1/INT5 I I/O port (Schmitt input)//Interrupt request 5 EmeraLd I/F L: Interrupted INT5-1T

2/7
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC49

Pin Use setting of port I/O Description Connection/Use Logic Signal

Secondary scanning
46 PK0/TB0IN0/INT4 I I/O port (Schmitt input)//Interrupt request 4 LazuLite I/F direction line match UHSCTCP-1TA
signal (K)
47 PJ7/TB3OUT1/TB5OUT I/O, O, I/O port (Schmitt input)//Interrupt request 4 LazuLite I/F L: Printing YPVDEN-0T
48 PJ6/TB3OUT0/TB5OUT I/O, O, I/O port (Schmitt input)/16-bit timer 3/5 output 0 LazuLite I/F L: Printing MPVDEN-0T
49 PJ5/TB2OUT1/TB4OUT I/O, O, I/O port (Schmitt input)/16-bit timer 2/4 output 1 LazuLite I/F L: Printing CPVDEN-0T
50 PJ4/TB2OUT0/TB4OUT I/O, O, I/O port (Schmitt input)/16-bit timer 2/4 output 0 LazuLite I/F L: Printing KPVDEN-0T
Pixel counter match
51 PJ3/TB1OUT1 I/O, O I/O port (Schmitt input)/16-bit timer 1 output 1 LazuLite I/F signal GCCTCP-1TA
H: Match
Paper exit motor
52 PJ2/TB1OUT0 I/O, O I/O port (Schmitt input)/16-bit timer 1 output 0 EXMCK-1T
control CLK
53 PJ1/TB0OUT1 I/O, O I/O port (Schmitt input)/16-bit timer 0 output 1 - Unused -
54 PJ0/TB0OUT0 I/O, O I/O port (Schmitt input)/16-bit timer 0 output 0 - Unused -
Secondary scanning
55 PF6/TA6IN/INT3 I/O, I, I I/O port (Schmitt input)//interrupt request 3 LazuLite I/F direction line match HSCTCP-1TA
signal (color)
56 PF5/TA5OUT I/O, O I/O port (Schmitt input)/ Coin Controller I/F MCRUN-0T
57 PF4/TA4IN/INT2 I/O, I, I I/O port (Schmitt input)//Interrupt request 2 PWR DOWN signal L: Normal ↑: 5V PWRDN-1TA
58 PF3/TA3OUT I/O, O I/O port (Schmitt input)/ - - Preliminary port
CMD interruption
59 PF2/TA2IN/INT1 I/O, I, I I/O port (Schmitt input)//Interrupt request 1 EmeraLd I/F SCMDINT-1T
(Set on the
Registration motor
60 PF1/TA1OUT I/O, O I/O port (Schmitt input)/ RGMCK-1T
control CLK
CMD interruption
61 PF0/TA0IN/INT0 I/O, I, I I/O port (Schmitt input)//Interrupt request 0 EmeraLd I/F SSTSINT-1T
(Set in the EmeraLd
62 DVCC - VDD - -
63 X1 I Clock input - - CPUCLK-1T
64 DVSS - GND - -
65 X2 I/O Clock input/output - -

3/7
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC49

Pin Use setting of port I/O Description Connection/Use Logic Signal

Operation mode:
(AM1/AM0)
(0/1): Fixed
external 16-bit bus
External 16-bit or 8-bit bus start operation mode start
66 AM1 I -
setting (1/0): Fixed
external 8 bit bus
start
(0/0): Fixed
prohibited
67 RESET I Reset input Reset circuit MRST-0T
68 AM0 I External 16-bit or 8-bit bus start operation mode -
69 DVSS - GND - -
70 NMI I VDD -
71 DVCC - VDD - -
Registration motor
72 PD0/HSSI0 I/O, I I/O port/ electric current setting RMSETI2-0T
signal
Reverser motor
73 PD1/HSSO0 I/O, O I/O port/ EMSETI2-0T
electric current setting
IPC connection L: Connected
74 PD2/HSCLK0 I/O, O I/O port/ IPCSW-0T
detection H: Disconnected
75 PD3/RXD2 I/O, I I/O port / Serial reception data 2 Coin Controller I/F EXTCTR-0T
L: Front cover close
76 PD4/TXD2 I/O, O I/O port / Serial transmission data 2 Front cover SW FRNTCO-1
H: Front cover open
I/O, I/O, L: During IMG
77 PD5/SCLK2/CTS2 I/O port / Serial clock I/O 2/ IMG I/F IMGCNT-0TJ
I connection
L: IMG power
78 PA0/RXD0 I/O, I I/O port (Schmitt input) / Serial reception data 0 IMG I/F abnormality IMGLIFE-1TJ
H: IMG normal
Each board
(between SLG-SYS-
79 PA1/TXD0 I/O, O I/O port (Schmitt input) / Serial transmission data 0 IMG I/F IMG-LGC） MMPI-1T
disconnection
detection L:

4/7
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC49

Pin Use setting of port I/O Description Connection/Use Logic Signal

I/O, I/O, I/O port (Schmitt input) / Serial clock I/O 0 / Serial
80 PA2/SCLK0/CTS0 Coin Controller I/F SZ0-0T
I data transmission possible 0
81 PA3/RXD1 I/O, I I/O port (Schmitt input) / Serial reception data 1 Coin Controller I/F SZ1-0T
82 PA4/TXD1 I/O, O I/O port (Schmitt input) / Serial transmission data 1 Coin Controller I/F SZ2-0T
I/O, I/O, I/O port (Schmitt input) / Serial clock I/O 1 / Serial
83 PA5/SCLK1/CTS1 Coin Controller I/F SZ3-0T
I data transmission possible 1
84 PL0/PG00/RXD3 I/O, O, I I/O port (Schmitt input) / Pattern generator output - - Preliminary port
I/O, O, I/O port (Schmitt input) / Pattern generator output Registration motor
85 PL1/PG01/TXD3 RGMEN-0T
O 01/ enable signal
Registration motor
I/O, O, I/O port (Schmitt input) / Pattern generator output
86 PL2/PG02/SCLK3/CTS3 electric current setting RMSETI1-0
I/O, I 02/
signal
I/O, O, I/O port (Schmitt input) / Pattern generator output Registration motor
87 PL3/PG03/TA7OUT RGMCW-1T
O 03/ direction signal
I/O port (Schmitt input) / Pattern generator output MasH/EX-MasH L: EX-Mash board
88 PL4/PG10/HSSI1 I/O, O, I (EXPWB-0)
10/ judgment signal H: Mash board
I/O, O, I/O port (Schmitt input) / Pattern generator output Reverse motor enable
89 PL5/PG11/HSSO1 EXMEN-0T
O 11/ signal
I/O, O, I/O port (Schmitt input) / Pattern generator output Reverse motor electric
90 PL6/PG12/HSCLK1 EMSETI1-0
O 12/ current setting signal
I/O port (Schmitt input) / Pattern generator output Reverse motor
91 PL7/PG13 I/O, O EXMCW-1T
13/ direction signal
92 P87/BusAK I/O, O I/O port / Bus acknowledge Coin Controller I/F FLCTR-0T
93 P86/BusRQ I/O, I I/O port / Bus request Coin Controller I/F MNCTR-0T
Output port / Chip selection 5 / Watchdog timer Watchdog detection L: Watchdog timer
94 P85/CS5/WDTOUT O WDT-0T
output circuit output
95 P84/CS4 O Output port / Chip selection 4 - - Preliminary port
96 P83/CS3/SDCS O Output port / Chip selection 3 / SDRAM chip Coin Controller I/F BKCTR-0T
97 P82/CS2 O Output port / Chip selection 2 EmeraLd I/F L: Chip selection CS2-0T
98 P81/CS1 O Output port / Chip selection 1 - - Preliminary port
99 P80/CS0 O Output port / Chip selection 0 EmeraLd I/F L: Chip selection CS0-0T
100 P77/WAIT I/O, I I/O port / bus wait request input terminal L: WAIT WAIT-0T
L: D8-D15 terminal
101 P76/SRLUB I/O, O I/O port / D8-D15 terminal SRAM data enable SRAM control SRLUB-0T
SRAM data enable
L: D0-D7 terminal
102 P75/SRLLB I/O, O I/O port / D0-D7 terminal SRAM data enable SRAM control SRLLB-0T
SRAM data enable

5/7
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC49

Pin Use setting of port I/O Description Connection/Use Logic Signal

103 P74/SRWR I/O, O I/O port / SRAM write enable SRAM control L: SRAM write SRWR-0T
104 P73/RW I/O, O I/O port / Read/write R/W L: Write H: Read R/W-0T
105 P72/WRLU I/O, O I/O port / Upper-level write PM1100 reset signal H (start-up): RESET SCRST-1T
106 P71/WRLL I/O, O I/O port / Write WR L: Write WR-0T
107 RD O Read RD L: Read RD-0T
108 DVSS - GND -
109 DVCC - VDD - -
110 D0 I/O Data Data bus -
111 D1 I/O Data Data bus -
112 D2 I/O Data Data bus -
113 D3 I/O Data Data bus -
114 D4 I/O Data Data bus -
115 D5 I/O Data Data bus -
116 D6 I/O Data Data bus -
117 D7 I/O Data Data bus -
118 P10/D8 I/O I/O port / Data Data bus -
119 P11/D9 I/O I/O port / Data Data bus -
120 P12/D10 I/O I/O port / Data Data bus -
121 P13/D11 I/O I/O port / Data Data bus -
122 P14/D12 I/O I/O port / Data Data bus -
123 P15/D13 I/O I/O port / Data Data bus -
124 P16/D14 I/O I/O port / Data Data bus -
125 P17/D15 I/O I/O port / Data Data bus -
126 P67/A23 I/O, O I/O port / Address Data bus -
127 P66/A22 I/O, O I/O port / Address Address bus -
128 P65/A21 I/O, O I/O port / Address Address bus -
129 P64/A20 I/O, O I/O port / Address Address bus -
130 P63/A19 I/O, O I/O port / Address Address bus -
131 P62/A18 I/O, O I/O port / Address Address bus -
132 P61/A17 I/O, O I/O port / Address Address bus -
133 P60/A16 I/O, O I/O port / Address Address bus -
134 A15 O Address Address bus -
135 A14 O Address Address bus -
136 A13 O Address Address bus -
137 A12 O Address Address bus -
138 A11 O Address Address bus -

6/7
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC49

Pin Use setting of port I/O Description Connection/Use Logic Signal

139 A10 O Address Address bus -
140 A9 O Address Address bus -
141 A8 O Address Address bus -
142 A7 O Address Address bus -
143 A6 O Address Address bus -
144 DVSS - GND -

7/7
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC60

Pin Use setting of port I/O Description Connection/Use Logic Signal

1 VSS - GND VSS
2 D7_1 I/O Data Data bus - D[7]
3 D6_1 I/O Data Data bus - D[6]
4 D5_1 I/O Data Data bus - D[5]
5 D4_1 I/O Data Data bus - D[4]
6 D3_1 I/O Data Data bus - D[3]
7 D2_1 I/O Data Data bus - D[2]
8 D1_1 I/O Data Data bus - D[1]
9 D0_1 I/O Data Data bus - D[0]
10 HVDD1 - CPU I/F power supply - 3.3V
11 VSS - GND - VSS
L: Not fixed L: Low
12 PA7_1 O Ozone exhaust fan (low speed) speed H: High OZFANL-0C
speed H: Stop
L: H: L:
13 PA6_1 O Ozone exhaust fan (high speed) OZFANH-0C
H:
L: Not fixed L: Low
14 PA5_1 O Laser unit cooling fan (front) (low speed) speed H: High PLFANL-0C
speed H: Stop
L: H: L:
15 PA4_1 O Laser unit cooling fan (front) (high speed) PLFANH-0C
H:
L: Software power
16 PA3_1 O Software power SW OFF signal MRSTSWA-0C
SW OFF
L: Polygonal motor
17 PA2_1 O Polygonal motor ON signal PMMTR-0C
ON
18 PA1_1 O Color registration (front/rear) ON signal L: LED ON RGREON-0C
19 PA0_1 O (Reserved) - (Reserved)
20 HVDD2 - PIO I/F power supply - 5V
21 LVDD - CORE power supply - 3.3V
22 PB7_1 O Download CS time limit release L: Released DLENB-0C
L: Shutter open
23 PB6_1 O Image quality sensor protect shutter solenoid A LSUSLA-0C
H: Shutter close
24 PB5_1 O (Reserved) - (Reserved)
25 PB4_1 O (Reserved) - (Reserved)
26 PB3_1 O K discharge lamp L: ON KERSLP-0C
27 PB2_1 O Pressure roller lamp OFF signal H: OFF PHOFF-1C

1/8
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC60

Pin Use setting of port I/O Description Connection/Use Logic Signal

28 PB1_1 O Auxiliary lamp OFF signal H: OFF SUBOFF-1C
29 PB0_1 O Y/M/C discharge lamp L: ON YERSLP-0C
30 VSS - GND - VSS
31 PC7_1 I/O Polygonal motor READY signal L: Ready PMRDY-0C
H: Door open (24V
32 PC6_1 I/O F&EXIT DOOR 24VCHK-1C
normal)
33 PC5_1 I/O ADU cover open detection L: Close H: Open ADUCOV-0CA
34 PC4_1 I/O Laser shutter detection LUSTSW-1CA
Front door open and
35 PC3_1 I/O Waste toner full sensor waste toner FULL USTFULL-1CA
with "H"
L: Contact H:
36 PC2_1 I/O 2nd transfer contact position detection SW TB2PS-1CA
Release
37 PC1_1 I/O Waste toner transport lock detection TNTRLK-1CA
38 PC0_1 I/O Belt contact position detection sensor 1 BTPS1-1CA
39 HVDD2 - PIO I/F power supply - 5V
40 PD7_1 I/O
41 PD6_1 I/O
42 PD5_1 I/O Waste toner mixing paddle lock detection PDLOCK-1CA
L: SRAM board
43 PD4_1 I/O PWA-F-SRAM connection detection SRAMCNT-0CJ
connection
44 PD3_1 I/O Color deviation reduction sensor 2 (K phase DRPOS2-1C
45 PD2_1 I/O Color deviation reduction sensor 1 (C phase DRPOS1-1C
46 PD1_1 I/O (Reserved) - (Reserved)
L: Door open
47 PD0_1 I/O Waste toner cover sensor TNCOV-1C
H: Door close
48 VSS - GND - VSS
49 PE7_1 O Waste toner mixing motor L: Motor ON PDLMT-0C
50 PE6_1 O (Reserved) Unused (Reserved)
L: OFF H: Release
51 PE5_1 O Releasing motor B TBLTMB-1C
L: Unused H: Brake
L: L:
52 PE4_1 O Releasing motor A TBLTMA-0C
H: H:
53 PE3_1 O Waste toner transport motor L: Motor ON TNTRMT-0C
54 PE2_1 O ADU clutch L: Clutch ON ADUCL-0C
55 PE1_1 O SFB pickup solenoid L: Solenoid ON MNTLSL-0C

2/8
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC60

Pin Use setting of port I/O Description Connection/Use Logic Signal

56 PE0_1 O SFB paper feeding clutch L: Clutch ON MNFDCL-0C
57 HVDD2 - PIO I/F power supply - 5V
L: No paper H:
58 PF7_1 I/O ADU sensor 2 ADUS2-1CA
Paper exists
L: No paper H:
59 PF6_1 I/O ADU sensor 1 ADUS1-1CA
Paper exists
60 PF5_1 I/O SFB paper detection L: Paper exists MNPEN-1CA
61 PF4_1 I/O SFB paper sensor L: Paper exists MNFDSN-1CA
62 PF3_1 I/O SFB paper size detection 3 L: ON H: OFF MNPS3-0CA
63 PF2_1 I/O SFB paper size detection 2 L: ON H: OFF MNPS2-0CA
64 PF1_1 I/O SFB paper size detection 1 L: ON H: OFF MNPS1-0CA
65 PF0_1 I/O SFB paper size detection 0 L: ON H: OFF MNPS0-0CA
66 VSS - GND - VSS
67 LVDD - CORE power supply - 3.3V
68 PG7_1 O 2nd drawer feed clutch L: Clutch ON CS2PCL-0C
69 PG6_1 O 1st drawer feed clutch L: Clutch ON CS1PCL-0C
L: OFF H: CW
(lower drawer) L:
70 PG5_1 O 1st drawer tray-up motor B CS1TUMB-1C
CCW (upper
drawer)
L: L:
71 PG4_1 O 1st drawer tray-up motor A CS1TUMA-0C
H: H:
72 PG3_1 O 2nd bridge clutch for processing L: Clutch ON MDT2CLL-0C
73 PG2_1 O 2nd bridge clutch for paper feeding L: Clutch ON MDT2CLH-0C
74 PG1_1 O 1st bridge clutch for process L: Clutch ON MDT1CLL-0C
75 PG0_1 O 1st bridge clutch for paper feeding L: Clutch ON MDT1CLH-0C
76 HVDD2 - PIO I/F power supply - 5V
L: Other positions
77 PH7_1 I/O 2nd tray-up limit sensor CS2TL-1CA
H: TOP position
L: Other positions
78 PH6_1 I/O 1st tray-up limit sensor CS1TL-1CA
H: TOP position
79 PH5_1 I/O 2nd paper near-empty L: Paper exists CS2PNEM-1CA
80 PH4_1 I/O 1st paper near-empty L: Paper exists CS1PNEM-1CA
81 PH3_1 I/O 2nd drawer detection L: Close CS2PS-0CA
82 PH2_1 I/O 1st drawer detection L: Close CS1PS-0CA
83 PH1_1 I/O 2nd paper near-empty L: Paper exists CS2PEM-1CA

3/8
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC60

Pin Use setting of port I/O Description Connection/Use Logic Signal

84 PH0_1 I/O 1st paper near-empty L: Paper exists CS1PEM-1CA
85 VSS - GND - VSS
L: Low speed
86 PI7_1 O Feed motor gain switching signal H: High speed FDMGA-0C
(default H)
87 PI6_1 O Feed motor brake signal L: Brake FDMBK-0C
88 PI5_1 O Feed motor ON signal L: Motor ON FDMON-0C
89 PI4_1 O Bridge unit gate solenoid L: Solenoid ON GASOL-0C
L: Not fixed L: Low
speed
90 PI3_1 O Fuser unit fan (low speed) HTRFNL-0C
H: High speed H:
Stop
L: H: L:
91 PI2_1 O Fuser unit fan (high speed) HTRFNH-0C
H:
L: OFF H: Shutter
92 PI1_1 O Laser shutter motor B close L: Shutter LUSTMB-0C
open H: Brake
L: L:
93 PI0_1 O Laser shutter motor A LUSTMA-0C
H: H:
94 PJ7_1 I/O High voltage control leakage detection status L: Abnormality HVTSTS-1C
L: Disconnected
95 PJ6_1 I/O Thermistor connection detection THCNT-1CB
H: Connected
L: New BAM H:
96 PJ5_1 I/O Fuser unit new BAM-supported judgment signal FUSJD-0C
Current
97 PJ4_1 I/O Bridge unit paper exit sensor H: Paper exists RLC2S-0C
98 PJ3_1 I/O Bridge unit transfer cover open detection L: Close RLCSW-0C
99 PJ2_1 I/O Bridge unit intermediate transport sensor H: Paper exists RLTRS-0C
100 PJ1_1 I/O Bridge unit machine tray full sensor H: Full RLHSW-0C
101 PJ0_1 I/O Bridge unit connection SW L: Connected RLCNT-0C
102 HVDD2 - PIO I/F power supply - 5V
103 VSS - GND - VSS
104 PK7_1 O High voltage control OUT6-C ON signal L: ON HVTECC-0C
105 PK6_1 O High voltage control OUT6-K ON signal L: ON HVTECK-0C
L: Constant electric
106 PK5_1 O High voltage control OUT5 control switch current H: TR2IV-0C
Constant voltage

4/8
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC60

Pin Use setting of port I/O Description Connection/Use Logic Signal

107 PK4_1 O High voltage control OUT5 ON signal L: ON HVTTR2-0C
108 PK3_1 O High voltage control OUT4-C ON signal L: ON HVTTR1C-0C
109 PK2_1 O High voltage control OUT4-M ON signal L: ON HVTTR1M-0C
110 PK1_1 O High voltage control OUT4-Y ON signal L: ON HVTTR1Y-0C
111 PK0_1 O High voltage control OUT4-K ON signal L: ON HVTTR1K-0C
112 LVDD - CORE power supply - 3.3V
113 PL7_1 O High voltage control first transfer electric current TR1CC-0C
L: Constant electric
114 PL6_1 O High voltage control OUT4 control switch current H: TR1IV-0C
Constant voltage
115 PL5_1 O High voltage control OUT3-C AC ON signal L: ON HVTDACC-0C
116 PL4_1 O High voltage control OUT3-K AC ON signal L: ON HVTDACK-0C
117 PL3_1 O High voltage control OUT3-C DC ON signal L: ON HVTDDCC-0C
118 PL2_1 O High voltage control OUT3-K DC ON signal L: ON HVTDDCK-0C
119 PL1_1 O High voltage control OUT1/2-C ON signal L: ON HVTMC-0C
120 PL0_1 O High voltage control OUT1/2-K ON signal L: ON HVTMK-0C
121 VSS - GND - VSS
122 PM7_1 O Developer unit drive direction signal L: CW H: CCW DVMDIR-0C
123 PM6_1 O (Reserved) (Reserved)
L: Low speed
124 PM5_1 O Developer unit drive gain switching signal H: High speed DVMGA-0C
(default H)
L: Low speed
125 PM4_1 O Fuser + bridge unit drive gain switching signal H: High speed FSMGA-0C
(default H)
126 PM3_1 O Developer unit drive brake signal L: Brake DVMBK-0C
L: CW H: CCW
127 PM2_1 O Fuser + bridge unit drive DIR signal FSMDIR-0C
(normal)
128 PM1_1 O Developer unit drive motor ON signal L: Motor ON DVMON-0C
129 PM0_1 O Fuser + bridge unit drive motor ON signal L: Motor ON FSMON-0C
130 HVDD2 - PIO I/F power supply - 5V
131 PN7_1 I/O Developer unit drive Ready signal L: READY DVMRDY-0C
132 PN6_1 I/O Fuser + bridge unit drive Ready signal L: READY FSMRDY-0C
133 PN5_1 I/O Paper feeding drive Ready signal L: READY FDMRDY-0C
134 PN4_1 I/O TBU cover open detection L: Close H: Open 2TRCOV-0CA

5/8
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC60

Pin Use setting of port I/O Description Connection/Use Logic Signal

L: No light shielding
135 PN3_1 I/O K genuine cartridge detection ON signal H: Mixing paddle KCRGSW-0CA
gear light shielding
L: No light shielding
136 PN2_1 I/O C genuine cartridge detection ON signal H: Mixing paddle CCRGSW-0CA
gear light shielding
L: No light shielding
137 PN1_1 I/O M genuine cartridge detection ON signal H: Mixing paddle MCRGSW-0CA
gear light shielding
L: No light shielding
138 PN0_1 I/O Y genuine cartridge detection ON signal H: Mixing paddle YCRGSW-0CA
gear light shielding
139 VSS - GND - VSS
L: Y L: M C
140 PO7_1 O Toner IC-Chip YMCK access switching H: C M H: K TNEPMRX1
L H L H
141 PO6_1 O TNEPMRX0
L: OFF H: To black
142 PO5_1 O Drum switching motor ON signal B and white L: To CKMMB-1C
color H: Brake
L: L:
143 PO4_1 O Drum switching motor ON signal A CKMMA-0C
H: H:
144 PO3_1 O K toner supply motor ON signal L: ON KTNMT-0C
145 PO2_1 O C toner supply motor ON signal L: ON CTNMT-0C
146 PO1_1 O M toner supply motor ON signal L: ON MTNMT-0C
147 PO0_1 O Y toner supply motor ON signal L: ON YTNMT-0C
148 HVDD2 - PIO I/F power supply - 5V
L: Not fixed L: Low
speed
149 PP7_1 O EPU cooling fan (low speed) EPUFNL-0C
H: High speed H:
Stop
L: H: L:
150 PP6_1 O EPU cooling fan (high speed) EPUFNH-0C
H:
151 PP5_1 O (Reserved) - (Reserved)
152 PP4_1 O Fuser + bridge unit drive brake signal L: Brake FSMBK-0C

6/8
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC60

Pin Use setting of port I/O Description Connection/Use Logic Signal

L: Not fixed L: Low
speed
153 PP3_1 O Toner cartridge cooling fan (low speed) CGFANL-0C
H: High speed H:
Stop
L: H: L:
154 PP2_1 O Toner cartridge cooling fan (high speed) CGFANH-0C
H:
L: Not fixed L: Low
speed
155 PP1_1 O Power supply unit cooling fan (low speed) PWFANL-0C
H: High speed H:
Stop
L: H: L:
156 PP0_1 O Power supply unit cooling fan (high speed) PWFANH-0C
H:
157 LVDD - CORE power supply - 3.3V
158 TST1_1 I ASIC test - TST1-1
159 VSS - GND - VSS
L: Power system
160 PQ7_1 I/O Watchdog enable signal control forcible OFF WDE-1T
H: Normal
161 PQ6_1 I/O Paper feeding cover open/close detection H: Open L: Close CSTCV-0C
162 PQ5_1 I/O (Reserved) Unused (Reserved)
163 PQ4_1 I/O
L: Black and white
164 PQ3_1 I/O Drum mode detection signal 1 CKMODE1-1CA
H: Color
165 PQ2_1 I/O External counter connection signal 2 (unused) - CTRCNT2-0C
166 PQ1_1 I/O Coin controller count signal L: Count CTRON-0C
167 PQ0_1 I/O Key counter count signal L: Count KCTRON-0C
168 HVDD2 - PIO I/F power supply - 5V
169 CLK_1 I Reset protection circuit clock - SDCLK-1TA
170 RSTSEL_0 I Reset protection circuit selection - OPRSTSEL-0
H: Connected L:
171 PR1_1 I/O Fuser unit connection detection FUSCNT-1C
Disconnected
Key counter / totalizer / coin controller connection
172 PR0_1 I/O L: Printing permitted KCTRC-0C
detection signal
173 HVDD1 - CPU I/F power supply - 3.3V
174 RST_0 I Rest signal L: Reset MRST-0T
175 VSS - GND - VSS

7/8
e-STUDIO2040C/2540C/3040C/3540C/4540C
LGC Board IC60

Pin Use setting of port I/O Description Connection/Use Logic Signal

176 A0_1 I Address - A[0]
177 A1_1 I Address - A[1]
178 A2_1 I Address - A[2]
179 A3_1 I Address - A[3]
180 A4_1 I Address - A[4]
181 CS_0 I Chip selection - OPALCS-0TA
182 RD_0 I Read - OPLRD-0T
183 HVDD1 - CPU I/F power supply - 3.3V
184 WR_0 I Write - OPALWR-0T

8/8
e-STUDIO5540C/6540C/6540C and e-STUDIO2040C/2540C/3040C/3540C/4540C
SLG board IC15

Pin Use setting of port I/O Description Connection/Use Logic Signal

1 3.3V - 3.3V
2 A5 OUT Address bus: A5 Address bus MAD5
3 A4 OUT Address bus: A4 Address bus MAD4
4 A3 OUT Address bus: A3 Address bus MAD3
5 A2 OUT Address bus: A2 Address bus MAD2
6 A1 OUT Address bus: A1 Address bus MAD1
7 A0 OUT Address bus: A0 Address bus MAD0
8 PC5 I/O NC
0: Hold OFF
9 PC4 OUT Motor hold OFF Motor hold OFF MOTEN-0
(electric current cut)
Motor rotation/reverse 0: Rotation, 1:
10 PC3 OUT Motor rotation/reverse rotation MOTDIR-0
rotation Reverse rotation
11 PC2 OUT Data 3 for motor Data 3 for motor MOTMD3-0
12 PC1 OUT Data 2 for motor Data 2 for motor MOTMD2-0
13 PC0 OUT Data 1 for motor Data 1 for motor MOTMD1-0
14 P96 OUT 5VSWON 5VSWON 0: Controllable 5VSWON-0
15 P95 OUT APS power ON APS power ON 1: APS power ON APSON-0
01: High speed
rotation
16 P94 OUT Fan low speed rotation Fan low speed rotation 10: Low speed FANSLW-0
rotation
11: Stop
01: High speed
rotation
Fan high speed
17 P93 OUT Fan high speed rotation 10: Low speed FANFST-0
rotation
rotation
11: Stop
LED lights during
18 P92 OUT LED lights during download 1: LED ON LED-0
download
19 P91 OUT NC
20 P90 OUT
21 GND - GND
22 NC - NC
23 OUT MOTREF
24 3.3V - 3.3V

1/6
e-STUDIO5540C/6540C/6540C and e-STUDIO2040C/2540C/3040C/3540C/4540C
SLG board IC15

Pin Use setting of port I/O Description Connection/Use Logic Signal

Lamp cooling 5V fan
25 PN3 IN Lamp cooling 5V fan connection confirmation 1: Connected 5VFANON
connection
ROM board 0: ROM board
26 PN2 IN ROM board connection ROMCNT-0
connection installed
Scanner connection 0: Control panel
27 PN1 IN Scanner connection on control panel PNCNT-0
on control panel installed
Reserved (CCD
Reserved (CCD cooling fan connection
28 PN0 IN cooling fan connection 1: Connected 24VFANAFEON
confirmation)
confirmation)
0: Originals exist
29 PM7 IN APS rear input APS rear input APSR-0
1: No originals
0: Originals exist
30 PM6 IN APS center input APS center input APSC-0
1: No originals
0: Originals exist
31 PM5 IN APS 3 input APS 3 input APS3-0
1: No originals
0: Originals exist
32 PM4 IN APS 2 input APS 2 input APS2-0
1: No originals
0: Originals exist
33 PM3 IN APS 1 input APS 1 input APS1-0
1: No originals
34 PM2 IN Platen SW input Platen SW input 0: Platen cover PLTN-1
+24V power voltage Threshold (200/255
35 AN1 IN +24V power voltage check 24VCHK
check or higher)
Home position sensor 1: Carriage home
36 PM0 IN Home position sensor input HOME-1
input position
37 GND - GND
38 3.3V - 3.3V
24VFAN2 connection
39 PK7 IN 24VFAN2 connection confirmation 1: Connected 24VFAN2ON
confirmation
24VFAN1 connection
40 PK6 IN 24VFAN1 connection confirmation 1: Connected 24VFAN1ON
confirmation
SG connection
41 PK5 IN SG connection (reserved) SG
(reserved)
42 PK4 IN For model identification For model ROMCK2
43 PK3 IN For model identification For model ROMCK1
Transmission request ACK signal from DF
44 INT6 IN Transmission request to DF serial I/F SLG DFRRQ-0
to DF serial I/F SLG to SLG

2/6
e-STUDIO5540C/6540C/6540C and e-STUDIO2040C/2540C/3040C/3540C/4540C
SLG board IC15

Pin Use setting of port I/O Description Connection/Use Logic Signal

EX-BP/EX-Mash 0: EX-BP
45 PK1 IN EX-BP/EX-Mash identification SPECIFIC
identification 1: EX-Mash
46 PK0 IN NC Pull Down
47 PJ7 OUT NC
48 PJ6 OUT (DWNLD0-0)
49 PJ5 OUT DWNLD DWNLD DWNLD0-0
Clock output for
50 PJ4 OUT Clock output for EEPROM EEMCLK-1
EEPROM
51 PJ3 OUT NC
52 PJ2 OUT NC
Reserved (CCD 0: Stop
53 PJ1 OUT Reserved (CCD cooling fan) AFEFAN-1
cooling fan) 1: Rotation
54 PJ0 OUT NC
55 PF6 IN EEPROM data input EEPROM data input EEMDTIN-1
56 PF5 OUT EEPROM data output EEPROM data output EEMDTOUT-1
1 -> 0: DF scan start
57 PF4 IN DF scan start DF scan start DFSCST-0
(↓Edge)
58 PF3 OUT EEPROM chip selection EEPROM chip EEMCS-1
HIT from STR
59 INT1 IN HIT from STR (interruption) Rising edge HIT-1
(interruption)
Scan motor reference
60 TA1OUT OUT Scan motor reference clock MOTCLK-1
clock
61 PF0 OUT NC
62 GND - GND
63 3.3V - 3.3V
64 X1 IN System clock (33 MHz) System clock (33 X1
65 GND - GND
66 IN ROMCNT-1
67 IN MRST-0
Connected with 26
68 IN ROMCNT-0
pins
69 GND - GND
70 3.3V - 3.3V
71 3.3V - 3.3V
SYS board installation 0: SYS board
72 PD0 IN SYS board installation check SYSCNT-0A
check installed
3/6
e-STUDIO5540C/6540C/6540C and e-STUDIO2040C/2540C/3040C/3540C/4540C
SLG board IC15

Pin Use setting of port I/O Description Connection/Use Logic Signal

73 PD1 I/O NC
74 PD2 IN DF connection DF connection 0: DF installed DFCNT-0
DF serial I/F DF serial I/F
75 PD3 OUT 0: ACK DFAK-0
ACK to DF ACK to DF
DF serial I/F
DF serial I/F ACK signal from DF
76 PD4 OUT Transmission request DFRQ-0
Transmission request to DF to SLG
to DF
DF serial I/F DF serial I/F
77 PD5 IN 0: ACK DFRAK-0
ACK to SLG ACK to SLG
78 RXD0 IN SYS serial I/F data input SYS serial I/F data SRXD-1A
SYS serial I/F data
79 TXD0 OUT SYS serial I/F data output STXD-1
output
SYS serial I/F scanner
80 CTS0 IN SYS serial I/F scanner reception ready 0: Reception ready SCTS-0A
reception ready
81 RXD1 IN DF serial I/F data output DF serial I/F data DFRXD-0
82 TXD1 OUT DF serial I/F data input DF serial I/F data input DFTXD-0
SYS serial I/F scanner 0: Transmission
83 PA5 OUT SYS serial I/F scanner transmission ready SRTS-0
transmission ready ready
84 PL0 I/O For debug For debug DBG0
85 PL1 I/O For debug For debug DBG1
86 PL2 I/O For debug For debug DBG2
87 PL3 I/O For debug For debug DBG3
88 PL4 I/O For debug For debug DBG4
89 PL5 I/O For debug For debug DBG5
90 PL6 I/O For debug For debug DBG6
91 PL7 I/O For debug For debug DBG7
92 P87 OUT ASIC SLEEP setting ASIC SLEEP setting 1: ASIC PLL stop SLEEP-1
Image data output
93 P86 OUT Image data output enable 1: Data output stop IOE-0
enable
1: CPU normal
94 WDTOUT OUT Watchdog timeout Watchdog timeout WDTOUT-0
0: CPU abnormal
95 CS4 OUT NC NC
FROM chip selection
96 CS3 OUT FROM chip selection during download CS3-0
during download
Program FROM chip
97 CS2 OUT Program FROM chip selection CS2-0
selection

4/6
e-STUDIO5540C/6540C/6540C and e-STUDIO2040C/2540C/3040C/3540C/4540C
SLG board IC15

Pin Use setting of port I/O Description Connection/Use Logic Signal

98 CS1 OUT Data RAM chip selection Data RAM chip CS1-0
ASIC/STR/control
99 CS0 OUT ASIC/STR/control panel decoding CS0-0
panel decoding
100 P77 OUT NC
101 P76 OUT STR judgment NG STR judgment NG 0: NG STR-0
102 P75 OUT NC
Reserved (APS power
103 P74 OUT Reserved (APS power ON/OFF) 1: APS power OFF PLTNDLY-1
ON/OFF)
Scanner control panel
104 R/W OUT Scanner control panel light PNLWR
light
105 P72 OUT NC
106 WR OUT WRITE WRITE MWR-0A
107 OUT Read Read MRD
108 GND - GND
109 3.3V - 3.3V
110 D0 I/O Data bus: D0 Data bus MDT0
111 D1 I/O Data bus: D1 Data bus MDT1
112 D2 I/O Data bus: D2 Data bus MDT2
113 D3 I/O Data bus: D3 Data bus MDT3
114 D4 I/O Data bus: D4 Data bus MDT4
115 D5 I/O Data bus: D5 Data bus MDT5
116 D6 I/O Data bus: D6 Data bus MDT6
117 D7 I/O Data bus: D7 Data bus MDT7
118 D8 I/O Data bus: D8 Data bus MDT8
119 D9 I/O Data bus: D9 Data bus MDT9
120 D10 I/O Data bus: D10 Data bus MDT10
121 D11 I/O Data bus: D11 Data bus MDT11
122 D12 I/O Data bus: D12 Data bus MDT12
123 D13 I/O Data bus: D13 Data bus MDT13
124 D14 I/O Data bus: D14 Data bus MDT14
125 D15 I/O Data bus: D15 Data bus MDT15
126 P67 OUT
127 P66 OUT Exposure lamp ON Exposure lamp ON 0: Exposure lamp LMPON-0
128 P65 OUT CCD power OFF setting CCD power OFF 0: CCD Power OFF CCDPSOFF-0
129 P64 OUT Lamp cooling fan Lamp cooling fan 1: Fan rotates LMPFAN-0
130 P63 OUT Lamp rear fan Lamp rear fan 0: Fan rotates REARFAN-1

5/6
e-STUDIO5540C/6540C/6540C and e-STUDIO2040C/2540C/3040C/3540C/4540C
SLG board IC15

Pin Use setting of port I/O Description Connection/Use Logic Signal

131 A18 OUT Address bus: A18 Address bus MAD18
132 A17 OUT Address bus: A17 Address bus MAD17
133 A16 OUT Address bus: A16 Address bus MAD16
134 A15 OUT Address bus: A15 Address bus MAD15
135 A14 OUT Address bus: A14 Address bus MAD14
136 A13 OUT Address bus: A13 Address bus MAD13
137 A12 OUT Address bus: A12 Address bus MAD12
138 A11 OUT Address bus: A11 Address bus MAD11
139 A10 OUT Address bus: A10 Address bus MAD10
140 A9 OUT Address bus: A9 Address bus MAD9
141 A8 OUT Address bus: A8 Address bus MAD8
142 A7 OUT Address bus: A7 Address bus MAD7
143 A6 OUT Address bus: A6 Address bus MAD6
144 GND - GND

6/6
3. ELECTRIC CIRCUIT DESCRIPTION

3.1 Scanner

3.1.1 Scan motor control circuit

The scan motor is a stepping motor driven by the control signal output from the scanner CPU on the
SLG board and drives carriage-1 and -2.
The scan motor is driven by the pulse signal (SCNM-A, SCNM-AB, SCNM-B, SCNM-BB) output from
the motor driver. These pulse signals are formed based on the reference clock (MOTCLK) and output
only when the enable signal (MOTEN) is a high level. Also, the rotation speed or direction of the motor
can be switched by changing the output timing of each pulse signal.

SLG board +5.1VB

+24VMT
(+24VD4)
+24VMT
(+24VD4)

MOTCLK SCNM-A

MOTEN SCNM-AB
IC15 IC1 Scan motor

Scanner CPU MOTDIR Motor driver SCNM-B

SCNM-BB

Reset signal MOTRST

generation circuit
SG +24VMTGND
(PG)

Fig. 3-1

Control signal

Status
Signal Function
High level Low level
MOTCLK Reference clock --- ---
MOTEN Enable signal ON OFF
MOTDIR Rotation direction signal CCW CW
MOTRST Reset signal Normal operation Reset
* CW: Clockwise rotation, CCW: Counter clockwise rotation viewing from the axis
* High level: Forcibly turning OFF the excitation drive output (Non-excitation state)
* Low level: Normal operation state (Excitation state)

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3-1
3.1.2 Exposure lamp control circuit

SLG board +5VSW

LMPON-0 Exposure lamp
Q1

LMPON-0

Scanner WDTOUT-0 Lighting device for

LMPON-0A
CPU exposure lamp
(Lamp inverter board)

5VSWON-0
Q8

PG

Control signal

Signal Function
LMPON-0 Exposure lamp ON signal
WDTOUT-0 Watchdog timer signal
5VSOW-0 +5 VSW ON signal
LMPEN-0 Exposure lamp enable signal

Condition

Exposur
LAMPON-0 WDTOUT-0 5VSOW-0 LMPEN-0 +5VSW Q8 State of equipment
e lamp
L H L L ON ON ON
Normal operation
H H L L ON OFF
Scanner CPU
--- L --- --- OFF OFF
overdriving
--- H H --- OFF OFF OFF Call for service
Abnormality
--- --- --- H --- OFF detected
(Check sum error)

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3-2
3.2 Laser Optical Unit

3.2.1 Polygonal motor control circuit

The polygonal motor is a DC motor rotated by a clock signal (PMCK) output from the ASIC. This motor
is controlled under PLL (Phase Locked Loop) to realize an accurate and constant rotation. Its rotation
status is converted to a status signal (PMRDY) and then output to the ASIC. PMRDY signal moves to a
low level only when the rotation status of the motor is constant. The ASIC detects the rotation status
with this signal, and emits a laser beam only when the rotation status is constant.

LGC board

+24VD1

IC48

ASIC IC84
PMCK

+5VSW Polygonal motor

PMMTR

IC60 +5.1VB

ASIC
PMRDY

Fig. 3-2

Control signal

Status
Signal Function
High level Low level
PMMTR Motor ON signal OFF ON
PMCK Reference clock --- ---
PMRDY PLL control signal Stopping or error Locked
(Rotating at a constant
speed)

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3-3
3.2.2 Mirror motor control circuit
The mirror motor is a stepping motor driven by the control signal output from the ASIC on the LGC
board and drives the tilt adjustment system of the reflection mirror.
The mirror motor is driven by each phase of the pulse signal (TILT0, TILT1, TILT2, TILT3) output from
the ASIC. The rotation speed or direction of the motor can be switched by changing the output timing of
each pulse signal.
Also, the pulse signal is used for each mirror motor of M, C and K color in common. Selecting the level
of the enable signal (TILTM, TILTC, TILTK) sends the signal only to the mirror motor to be driven.

LGC board
+5VSW +24VD1 +24VD1
F11
IC61
TILT0

TILT1
Mirror motor-M

TILT2

TILT3
TILTM

PG

+5VSW +24VD1

IC63

IC48 Mirror motor-C

ASIC

TILTC

PG

+5VSW +24VD1

IC61

Mirror motor-K

TILTK

PG

Fig. 3-3

Control signal

Status
Signal Function
High level Low level
TILT0/1/2/3 Mirror motor phase signal --- ---
TILTM/C/K Enable signal OFF ON

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3-4
Relation between enable signal and motor to be driven
Signal
TILTM TILTC
L H
H L
H H
H H
* Not available in the above combination
Motor to be driven
TILTK
H Mirror motor-M
H Mirror motor-C
L Mirror motor-K
H None (No tilt adjustment)
e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3-5
3.3 Paper Feeding System

3.3.1 Tray-up motor control circuit

The tray-up motor (M21) is a DC brush motor driven by the control signal output from the ASIC on the
LGC board and moves up the tray in each drawer.
The motor driver outputs the drive signal (CS1TUMA -0J, CS1TUMB-1J) to the motor based on the
control signal (CS1TUMA-0C, CS1TUMB-1C) output from the ASIC. The motor operates the rotation,
stop or brake according to the status of these drive signals.

LGC board

+24VD3

IC59
CS1TUMA-0C F1 CS1TUMA-0A
IC60 IC3012
Tray-up
motor
ASIC CS1TUMB-1C Motor driver CS1TUMB-1A

PG

Fig. 3-4

Control signal

Signal
ASIC output Motor driver output Motor status
CS1TUMA-0C CS1TUMB-1C CS1TUMA-0J CS1TUMB-1J
L L OFF (high impedance) Stop
L H L H CW (Tray-up of 2nd drawer)
H L H L CCW (Tray-up of 1st drawer)
H H H H Brake
* CW: Clockwise rotation, CCW: Counter clockwise rotation viewing from the axis

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3-6
3.3.2 Registration motor control circuit
The registration motor (M19) is a stepping motor driven by the control signal output from the engine
CPU on the LGC board and rotates the registration roller.
The registration motor is driven by the pulse signal (RGTMA, RGTMB, RGTMC, RGTMD) output from
the motor driver. These pulse signals are formed based on the reference clock (RGMCK) and output
only when the enable signal (RGMEN) is a high level. Also, the rotation speed or direction of the motor
can be switched by changing the output timing of each pulse signal.

LGC board +5V +5V +24VD2 +24VD2

IC37
RGMCK RGTMA

IC49
RGMEN RGTMB Registration
IC22 motor
Engine CPU
RGMCW RGTMC
Motor driver

RGTMD
(STMRST)

SG PG

Fig. 3-5

Control signal

Status
Signal Function
High level Low level
RGMCK Reference clock --- ---
RGMEN Enable signal ON OFF
RGMCW Rotation direction signal CCW CW
STMRST Reset signal Normal operation Reset
* CW: Clockwise rotation, CCW: Counter clockwise rotation viewing from the axis

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3-7
3.3.3 Feed/Transport motor control circuit
The feed/transport motor (M20), which is a brush-less DC motor driven by control signals from the
ASIC on the LGC board, drives the feed roller, pickup roller and transport roller in each drawer and the
bypass unit.

LGC board

IC48 +24VD1

ASIC IC56
FDMCK

FDMGA
Feed/transport
+5V motor
+5VSW
FDMDIR

IC60 FDMON

ASIC +5.1VB

FDMRDY

Fig. 3-6

Control signal

Status
Signal Function
High level Low level
FDMON Motor ON signal OFF ON
FDMDIR Rotation direction signal CCW CW (unused)
FDMGA Speed switching signal High speed Low speed
FDMCK Reference clock --- ---
FDMRDY Rotation lock detection signal Unlocked Locked
(Rotating at a constant
speed)
* CW: Clockwise rotation, CCW: Counter clockwise rotation viewing from the axis
* FDMDIR signal is fixed at a high level and rotates only counter clockwise.
* When thick paper or OHP sheet is used, the clock frequency of FDMCK signal is changed to reduce
the motor speed in half and lower the paper transport speed so that the fusibility of toner is
improved.
* When the rotation speed of the motor is set to a low speed, FDMGA signal is changed to a low level
to suppress the rotation fluctuation of the motor.

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3-8
3.4 Process Unit Related Section

3.4.1 Drum Temperature Detection Circuit

The drum temperature detection circuit is composed as shown in the figure below. It converts the input
voltage from the drum thermistor into a digital signal by means of the A/D converter on the LGC board.
The drum thermistor is a device whose resistance value is smaller when the temperature is higher.
Therefore, when the temperature becomes higher, the input voltage to the A/D converter becomes
lower.

LGC board
+3.3V

YDRTH

Drum thermistor-Y

IC49
SG
+3.3V Engine CPU

KDRTH

Drum thermistor-K

SG

Fig. 3-7

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3-9
3.4.2 Drum motor control circuit
The drum motor is a stepping motor driven by the control signal output from the ASIC on the LGC board
and rotates the drum.
The drum motor is driven by the pulse signal (DRMA, DRMB, DRMC, DRMD) output from the motor
driver. These pulse signals are formed based on the reference clock (DMCK) and output only when the
enable signal (DMEN) is a high level. Also, the rotation speed or direction of the motor can be switched
by changing the output timing of each pulse signal.

LGC board +5VB +5VB +24VD2 +24VD2

IC28
DMCK DRMA

DMEN DRMB
IC48 IC46 Drum motor

ASIC DMDIR Motor driver DRMC

IC5 DRMD

(STMRST)

SG PG

Fig. 3-8

Control signal

Status
Signal Function
High level Low level
DMCK Reference clock --- ---
DMEN Enable signal ON OFF
DMDIR Rotation direction signal CCW CW
STMRST Reset signal Normal operation Reset
* CW: Clockwise rotation, CCW: Counter clockwise rotation viewing from the axis

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 10
3.4.3 Drum switching motor control circuit
The drum switching motor is a DC brush motor driven by the control signal output from the ASIC on the
LGC board and moves the guide to engage/disengage the gear which transmits the driving force of the
drum motor.
The motor driver outputs the drive signal (CKMMA-0A, CKMMB-1A) to the motor based on the control
signal (CKMMA-0C, CKMMB-1C) output from the ASIC. The motor operates the rotation, stop or brake
according to the status of these drive signals.

LGC board

+24VD3

IC59
CKMMA-0C F8 CKMMA-0A
IC60 IC3011
Drum switching
motor
ASIC CKMMB-1C Motor driver CKMMB-1A

PG

Fig. 3-9

Control signal

Signal
ASIC output Motor driver output Motor status
CKMMA-0C CKMMB-1C CKMMA-0A CKMMB-1A
L L OFF (high impedance) Stop
L H L H CW (Gear engaged)
H L H L CCW (Gear
disengaged)
H H H H Brake
* CW: Clockwise rotation, CCW: Counter clockwise rotation viewing from the axis

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 11
3.5 Developer Unit

3.5.1 Temperature/humidity detection circuit

The temperature/humidity detection circuit detects the temperature and humidity inside of the
equipment by means of the corresponding sensor so that the printing quality is not changed due to their
adverse influence where the equipment is set up, and corrects the output of the auto-toner sensor or
similar according to the result.
The temperature/humidity detection circuit is composed as shown in the figure below. It converts the
voltage of each analog signal output from the temperature/humidity sensor into a digital signal by
means of the A/D converter on the LGC board. The lower the temperature and the higher the humidity,
the higher the voltage of each analog signal output from the temperature/humidity sensor becomes.

LGC board
+5.1VB +5.1VB
Temperature/
humidity sensor

TEMP-1C

RTH
(Temp) IC64 IC48
ADCDI-1C
A/D
ASIC
converter
SG

VRHV HMS-1C
+
(Hum)
-

IC65

SG

Fig. 3-10

Control signal

Signal Function
TEMP-1C Temperature detection signal (analog)
HMS-1C Humidity detection signal (analog)

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 12
3.5.2 Toner motor control circuit
The toner motor is a DC brush motor driven by the control signal output from the ASIC on the LGC
board and rotates the mixing paddle and toner supply auger in each toner cartridge.

LGC board
+24VD3
F5
+5VSW

Toner motor-Y

YTNMT
Q38
Q24

PG

+24VD3
F6
+5VSW

Toner motor-M

MTNMT
Q39
Q25

IC60 PG

ASIC
+24VD3
F7
+5VSW

Toner motor-C

CTNMT
Q40
Q26

PG

+24VD3
F4
+5VSW

Toner motor-K

KTNMT
Q37
Q18

PG

Fig. 3-11

Control signal

Status
Signal Function
High level Low level
YTNMT Toner motor-Y ON signal
MTNMT Toner motor-M ON signal
Stop Rotate
CTNMT Toner motor-C ON signal
KTNMT Toner motor-K ON signal

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 13
3.5.3 Waste toner transport motor control circuit
The waste toner transport motor is a DC brush motor driven by the control signal output from the ASIC
on the LGC board and rotates the auger in the waste toner transport unit.

LGC board

+5VSW +24VD3

Waste toner
IC60 TNTRMT Q19 transport motor

ASIC
Q36

PG

Fig. 3-12

Control signal

Status
Signal Function
High level Low level
TNTMRMT Waste toner transport motor
Stop Rotate
ON signal

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 14
3.5.4 Waste toner paddle motor control circuit
The waste toner paddle motor is a DC brush motor driven by the control signal output from the ASIC on
the LGC board and rotates the mixing paddle in the waste toner box.

LGC board

+5VSW +24VD3 +24VD3

F10
Waste toner
IC60 PDLMT paddle motor

ASIC

PG

Fig. 3-13

Control signal

Status
Signal Function
High level Low level
PDLMT Waste toner paddle motor ON
Stop Rotate
signal

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 15
3.6 Transfer Unit

3.6.1 Transfer belt motor control circuit

The transfer belt motor is a stepping motor driven by the control signal output from the ASIC on the
LGC board and rotates the drive roller.
The transfer belt motor is driven by the pulse signal (TBMA, TBMB, TBMC, TBMD) output from the
motor driver. These pulse signals are formed based on the reference clock (TBMCK) and output only
when the enable signal (TBMEN) is a high level. Also, the rotation speed or direction of the motor can
be switched by changing the output timing of each pulse signal.

LGC board +5VB +24VD2 +24VD2

+5VB

TBMCK TBMA
IC37
TBMEN TBMB Transfer belt
IC48 IC45
motor
ASIC TBMCW Motor driver TBMC

TBMD
(STMRST)

SG PG

Fig. 3-14

Control signal

Status
Signal Function
High level Low level
TBMCK Reference clock --- ---
TBMEN Enable signal ON OFF
TBMDIR Rotation direction signal CCW CW
STMRST Reset signal Normal operation Reset

* CW: Clockwise rotation, CCW: Counter clockwise rotation viewing from the axis

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 16
3.6.2 1st transfer roller cam motor control circuit
The 1st transfer roller cam motor is a DC motor driven by the control signal output from the ASIC on the
LGC board and rotates the 1st transfer roller cam to contact/release each 1st transfer roller for Y, M and
C color to/from the transfer belt.
The motor driver outputs the drive signal (TBLTM1A-0A, TBLTM1B-1A) to the motor based on the
control signal (TBLTM1A-0C, TBLTM1B-1C) output from the ASIC. The motor operates the rotation,
stop or brake according to the status of these drive signals.

LGC board

+24VD3

IC59
TBLTM1A-0C TBLTM1A-0A
IC60 IC3014
1st transfer roller
F2 cam motor
ASIC TBLTM1B-1C Motor driver TBLTM1B-1A

PG

Fig. 3-15

Control signal

Signal
ASIC output Motor driver output Motor status
TBLTM1A-0C TBLTM1B-1C TBLTM1A-0A TBLTM1B-1A
L L OFF (high impedance) Stop
L H L H Rotation
H L H L Unused
H H H H Brake

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 17
3.7 Fuser unit / Paper exit section

3.7.1 Temperature detection circuit

The thermistor is a device whose resistance varies according to the detected temperature, and the
thermopile is a device whose output voltage varies according to the detected temperature. The ASIC
detects voltages output from these devices, and judges whether the operation of the fuser unit is
normal or abnormal from the changes in voltages.
If one of the thermistors and thermopiles is broken, the control circuit judges that the temperature of the
fuser belt or pressure roller is extremely low and keeps turning the heater lamps ON. As a result, the
temperature of the fuser belt or pressure roller rises, and possibly activates the thermostat which is a
safety protection device. To prevent this in advance, the ASIC works to detect whether each thermistor
and thermopile is broken or not.
Also, the control circuit constantly checks the temperature of the heat roller and the pressure roller to
prevent them from excessive heating by circuit abnormality or thermistor abnormality, and automatically
shuts OFF the power when one of these temperatures exceeds the specified temperature.

+5VB

Fuser belt
front thermistor
BHETH

SG

+5VB
Fuser belt
center thermopile BHCTH

SG

+5VB
Fuser belt
rear thermopile BHSTH
IC64
IC48
SG A/D
ASIC
converter
+5VB

Pressure roller
center thermistor
PHCTH

SG
+5VB

Pressure roller
rear thermistor
PHETH

SG

Fig. 3-16

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 18
3.7.2 Fuser motor control circuit
The fuser motor, which is a brush-less DC motor driven by control signals from the ASIC on the LGC
board, drives the pressure roller.

LGC board

+24VD1
IC48

ASIC
IC84
FSMCK

FSMBK

FSMGA
Fuser motor
FSMDIR
IC60
+5VSW

ASIC
FSMON
+5.1VB

FSMRDY

Fig. 3-17

Control signal

Status
Signal Function
High level Low level
FSMON Motor ON signal OFF ON
FSMDIR Rotation direction signal CCW CW
FSMGA Speed switching signal High speed Low speed
FSMCK Reference clock --- ---
FSMRDY Rotation lock detection Unlocked Locked
signal (Rotating at a constant
speed)
FSMSK Motor brake signal OFF ON

* CW: Clockwise rotation, CCW: Counter clockwise rotation viewing from the axis
* FSMDIR signal is fixed at a high level and rotates only counter clockwise.
* When thick paper or OHP sheet is used, FSMGA signal moves to a low level to reduce the motor
speed in half and lower the paper transport speed so that the fusibility of toner is improved.

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 19
3.7.3 Exit motor control circuit
The exit motor is a stepping motor driven by the control signal output from the engine CPU and ASIC
on the LGC board and rotates the exit roller.
The exit motor is driven by the pulse signal (EXTMA, EXTMB, EXTMC, EXTMD) output from the motor
driver. These pulse signals are formed based on the reference clock (EXMCK) and output only when
the enable signal (EXMEN) is a high level. Also, the rotation speed or direction of the motor can be
switched by changing the output timing of each pulse signal.

LGC board +5VB +5VB +24VD2 +24VD2

IC37
EXMCK EXTMA
IC49
EXMEN EXTMB
IC23 Exit motor
Engine CPU
EXMCW EXTMC
Motor driver
EXTMD

(STMRST)

SG PG

Fig. 3-18

Status
Signal Function
High level Low level
EXMCK Reference clock --- ---
EXMEN Enable signal ON OFF
EXMCW Rotation direction signal CCW CW
STMRST Reset signal Normal operation Reset

* CW: Clockwise rotation, CCW: Counter clockwise rotation viewing from the axis

e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 20
 3.8

AC input Switching regulator

3.8.1
Breaker Main switch
F101
L 12VA
FIL AC-DC
board power supply 12VB

Noise filter
N

F211
Damp heater AC OFF 5VS
detection
5VA
F205

CN401
5VB
Cover interlock
RLY1
switch
F102 F204
Power Supply Unit

AC-DC 24VD 24VD4

power supply F201
24V 24VD1

Noise filter
F202
24VD2

5VD

3 - 21
F203

Fig. 3-19
CN402 ~ CN407

24VD3
Configuration of Power Supply Unit

RLY-ON
SYS-EN
PWR-EN

CN409
LAMP1ON
Center heater lamp LAMP2ON
Heater lamp
LAMP3ON
Side heater lamp control circuit
LAMP4ON

CN408
Pressure roller lamp PWR-DN
FAN ON_H
Sub heater lamp* FAN
CN5

control FAN ON_L

circuit
CN6

*:e-STUDIO4520C only

ELECTRIC CIRCUIT DESCRIPTION

e-STUDIO2040C/2540C/3040C/3540C/4540C
e-STUDIO2040C/2540C/3040C/3540C/4540C
ELECTRIC CIRCUIT DESCRIPTION
3 - 22