Solutions to Assignments for Week 1

1. Which of the following does not represent a behavioral

representation for the function f=A.B+C?
a. The truth table of the function with output column
(01010111)
b. A Verilog specification: “assign f = (A & B) | C;”
c. A netlist consisting of one 2-input AND and one 2-input OR
gate
d. None of the above

Correct answer is (c).

Option (a) provides the output behavior of the specified
function. Option (b) describes the description of the specified
function using HDL. Option (c) represents the netlist which is
the original gate level description of the function. Therefore,
option (c) is the correct answer.

2. Which of the following statements is false?

a. Floorplanning and placement represent the same problem
in FPGA design style.
b. In standard cell design style, floorplanning fixes the sizes
of flexible blocks.
c. In full-custom design style, floorplanning typically precedes
placement.
d. Standard cell based design leads to faster circuit
realizations as compared to FPGA based design.

Correct answer is (b).

In FPGA as the LUTs are predesigned, Floorplanning and
placement represent the same problem and the Option (a) is
true. In standard cell design the sizes of each cell is fixed
depending on the foundry specification and the flexible blocks
sizes are fixed during the placement. So, Option (b) is false. In
full-custom design style, floorplanning typically precedes
placement Option (c) is true. Standard cell based design leads
to faster circuit realizations as compared to FPGA based
design option (d) is also true statement.

3. Given a gate-level netlist represented by a graph, which of the

following is not true for 4-input LUT mapping in a typical
FPGA?
 a. The 4-input LUT is typically realized using a 16x1 SRAM
unit.
b. Any subgraph with up to 4 input edges and 1 output edge
can be mapped to a LUT irrespective of the number of
vertices included therein.
c. In SRAM-based LUTs, the function of the LUT can be
changed by downloading appropriate bit patterns in the
associated RAM locations.
d. None of the above

Correct answer is (d).

In FPGA the 4-input LUT is typically realized using a 16x1
SRAM unit and the Option (a) is true. Option (b) is true as in
FPGA consisting of 4-input LUT any sub-graph with up to 4
input edges and 1 output edge can be mapped to a LUT
irrespective of the number of vertices included therein. Option
(c) is also true as the field created by the bit patterns helps in
realizing the desired function inside the FPGA by changing the
value of the SRAM cell. Therefore option (d) is the correct
answer.

4. For which design style, the following statement is true?

“The fabrication cost of a chip is C = C1 + C2, where C1
represents a cost that is shared among several customers,
while C2 represents a cost that is to be separately borne by
every customer.”
a. Gate array
b. FPGA
c. Standard cell
d. Full custom

Correct answer is (a).

5. Which of the following is not true for standard cell based

design?
(i) The heights of the cells are fixed but the widths can be
different.
(ii) Any number of cells can be placed in a row.
(iii) Feedthrough cells make the inter-row routing more
complex.
(iv) All the fabrication steps are followed to manufacture a
chip.
a. (ii) and (iii)
b. (ii) only
 c. (ii) and (iv)
d. (iii) only

Correct answer is (a).

In a standard cell each heights is fixed and width is different

for different blocks. Therefore this statement (i) is true. In a
row the number of cell can be determined by the size of the
chip divided by the widths of the cell used on that particular
row. Therefore this statement (ii) is false. Feedthrough cells
are basically used for the inter-row routing simpler which
makes the statement (iii) false. All the fabrication steps are
followed to manufacture a chip this statement is true.

6. Which of the following represents the correct ordering with

respect to speed of circuits (fastest to slowest)?
a. Full custom, Gate array, Standard cell, FPGA
b. Full custom, Standard cell, FPGA, Gate array
c. Full custom, Gate array, FPGA, Standard cell
d. None of the above

Correct answer is (b).

The ordering is Full custom, standard cell, FPGA, gate array. So
option (b) is correct.

7. What is the main objective of partitioning?

a. Divide a netlist into m almost equal parts such that the
worst-case delay of every partition is minimized.
b. Minimize the number of interconnection lines that are cut
by the partition boundaries, while dividing the netlist into
m almost equal parts.
c. Divide the critical path into m equal parts and then add the
remaining gates to the closest clusters.
d. All of the above.

Correct answer is (b).

This is the objective of partitioning.

8. The main objective of clock routing is:

a. To minimize the total interconnection length
b. To minimize the worst-case delay
c. To minimize the clock skew
d. None of the above
 Correct answer is (c).

Methods like H-tree, MMM, etc. aim to provide uniform clock

skews to all the sinks.

9. Match the following.

A. Partitioning
B. Floorplanning
C. Placement
D. Routing
(i) Takes a set of blocks of defined shapes and pin
locations, and assigns the blocks to exact locations on
the layout surface.
(ii) Takes the netlists in some particular order, and provides
interconnection among them.
(iii) Tries to define exact shapes of the blocks to minimize
layout area.
(iv) Breaks a netlist into several pieces that can be laid out
separately on the layout surface.
a. A-(iv), B-(iii), C-(i), D-(ii)
b. A-(iv), B-(i), C-(iii), D-(ii)
c. A-(iv), B-(ii), C-(i), D-(iii)
d. None of the above

Correct answer is (a).