Vous êtes sur la page 1sur 44

2.

1 8051 Microcontroller Pin Configuration

2
2.1.1 Power Connection Pins

• The 8051 operates from a single +5V supply (Vcc).

• Vcc connection is on pin 40, and the

• Vss (GND) connection is on pin 20.


3
2.1.2 On-chip Oscillator Input

C1
XTAL2 [Pin 18]

C1, C2 = 30 pF  10 pF
C2
XTAL1 [Pin 19]

• Typically driven by a crystal connected to pins 18


(XTAL2) and 19 (XTAL1).
• The nominal crystal frequency is 12MHz for most ICs in
MCS-51TM family.
• TTL clock source may also be connected to XTAL1 and
XTAL2.
4
2.1.3 Control Pins

• Program Store Enable (PSEN): Read strobe to external program


memory.
• Activated (held low) when executing code from the external program
memory.
• Not activated during internal program memory fetching.
• Address Latch Enable (ALE): An output pulse for latching the low byte
of the address during accesses to external memory.
• External Access (EA): Must be externally held low (ground) to enable
the device to fetch code from external program memory. If EA is held
high (+5V), the device executes program from internal program
memory.
• Reset (RST): Whenever this pin output is high for two machine cycles
while the oscillator is running, it will reset the device.
5
2.1.4 I/O Pins
• The 8051 has 32 pins of I/O port lines. However, 24 of these
lines are dual-purpose.
• Each of the lines may operate as I/O, or as a control line, or
part of the address or data bus.
• The 8 lines in each port can be treated as a unit in interfacing
with parallel devices such as printers, digital-to-analog
converters and etc.
• The lines can be also treated independently in interfacing to a
single-bit device such as switches, LEDs, transistors, motors
and loudspeakers.
• There are four I/O ports in 8051 microcontroller, they are:
i. Port 0
i. Port 1
ii. Port 2
iii. Port 3
6
i) Port 0
o A dual-purpose port on pins 32 – 39.
o For small design, it is used as general
purpose I/O port.
o For larger designs with external memory,
this port becomes a multiplexed low-byte
address and data bus to access the external
program and data memory.

ii) Port 1
o A dedicated I/O port on pins 1 – 8.
o No alternate function are assigned to this
port, thus they are solely for interfacing
with external devices.

7
iii) Port 2
o A dual-purpose I/O port on pins
21 – 28.
o For designs with external
memory, this port serves as the
high-byte address bus.

iv) Port 3
o A dual-purpose I/O port on pins
10 – 17.
o This pins are multifunctional,
with each having an alternate
purpose related to special
features of the 8051.

8
Alternate pin functions for Port 3

Bit Name Bit Address Alternate Function

P3.0 RXD B0H Receive data for serial port


P3.1 TXD B1H Transmit data for serial port
P3.2 INT0 B2H External interrupt 0
P3.3 INT1 B3H External interrupt 1
P3.4 T0 B4H Timer/counter 0 external input
P3.5 T1 B5H Timer/counter 1 external input
P3.6 WR B6H External data memory write strobe
P3.7 RD B7H External data memory read strobe

9
2.2 8051 Memory Organization
• 8051 implements a separate address space for programs (code)
and data memory.
• Both code and data memory may be internal, however both may
be expand using external memory components to a maximum of
64K code memory and 64K data memory.
8051

Program Data
Memory Memory

[ROM] [RAM]
10
2.2.1 8051 Memory Structure
Data Program FFFF
Memory FFFF Memory External
Code
(Read/Write) (Read Only) Memory
(ROM)
External
Data
Memory
Enabled via
On-chip (RAM)
PSEN
(Internal)
Data Memory
FF
(RAM) Enabled via 1000
WR and RD
Upper
part
SFR 0FFF

7F
On-chip External
4Kb ROM ROM
128 Lower
bytes part
00 0000 (EA=1) (EA=0)
0000
64K bytes

11
• The on-chip RAM contains of arrangements of general-purpose storage, bit-
addressable storage, register banks, and special function register (SFR).
7F FF

General-purpose
RAM

FF

On-chip 30 Special Function


RAM

Upper
Lower
2F Register
00 (SFR)
Bit-addressable
Locations
20
1F Bank 3
Bank 2
Bank 1
Bank 0 80
00
12
2.2.2 Register Banks
• The bottom 32 locations of internal memory contain the register banks.
• The instruction set supports 8 registers, R0 through R7.
• By default (after a system reset), Bank 0 at addresses 00H – 07H is used.

1F
Bank 3 R7 R6 R5 R4 R3 R2 R1 R0

Bank 2 R7 R6 R5 R4 R3 R2 R1 R0

Bank 1 R7 R6 R5 R4 R3 R2 R1 R0

Bank 0 R7 R6 R5 R4 R3 R2 R1 R0
00

• The active register bank may be altered by changing the register bank
select bits in the program status word (PSW) in SFR.
• The advantage of having register banks is to permit fast and effective
context switching.

13
2.2.3 Bit Addressable RAM

• The 8051 contains 210 bit-addressable locations, where 128 are at byte
addresses of 20H to 2FH, and the rest are in the SFR.
• All bits in this area can be set (1), cleared (0), ANDed, ORed, and so on
with a single instruction.
27 3F 3E 3D 3C 3B 3A 39 38 2F 7F 7E 7D 7C 7B 7A 79 78

26 37 36 35 34 33 32 31 30 2E 77 76 75 74 73 72 71 70
2F
25 2F 2E 2D 2C 2B 2A 29 28 2D 6F 6E 6D 6C 6B 6A 69 68

Bit-addressable 24 27 26 25 24 23 22 21 20 2C 67 66 65 64 63 62 61 60
Locations 23 1F 2E 2D 1C 1B 1A 19 18 2B 5F 5E 5D 5C 5B 5A 59 58

22 17 16 15 14 13 12 11 10 2A 57 56 55 54 53 52 51 50
20
21 0F 0E 0D 0C 0B 0A 09 08 29 4F 4E 4D 4C 4B 4A 49 48

20 07 06 05 04 03 02 01 00 28 47 46 45 44 43 42 41 40

• These bit-addressable location may also be accessed as bytes,


depending on the instruction.
14
• For example, to set bit 3 in byte address 25H, we use the instruction:

SETB 2BH

27 3F 3E 3D 3C 3B 3A 39 38 2F 7F 7E 7D 7C 7B 7A 79 78

26 37 36 35 34 33 32 31 30 2E 77 76 75 74 73 72 71 70
2F
25 2F 2E 2D 2C 2B 2A 29 28 2D 6F 6E 6D 6C 6B 6A 69 68

Bit-addressable 24 27 26 25 24 23 22 21 20 2C 67 66 65 64 63 62 61 60
Locations 23 1F 2E 2D 1C 1B 1A 19 18 2B 5F 5E 5D 5C 5B 5A 59 58
22 17 16 15 14 13 12 11 10 2A 57 56 55 54 53 52 51 50
20
21 0F 0E 0D 0C 0B 0A 09 08 29 4F 4E 4D 4C 4B 4A 49 48
20 07 06 05 04 03 02 01 00 28 47 46 45 44 43 42 41 40

• To access these location by bytes instruction, i.e. to set only bit 3 of


byte address 2BH (i.e. 5BH), we may use the instruction as follows:

MOV 2BH, #08H

15
2.2.4 General-purpose RAM

• General-purpose RAM occupies 80 bytes of RAM location from


addresses 30H to 7FH.
• Any location in this area can be accessed freely using direct or
indirect addressing modes (discussion on addressing mode will be on
Chapter 3).

7F
Direct Addressing Mode:
MOV A, 5FH
General-purpose
RAM
Indirect Addressing Mode:
MOV @R0, 5FH
MOV 34H, #R1
30

16
2.2.5 Special Function Registers (SFR)
• The 8051 has 21 SFRs as shown in the
figure. Note that some of the SFRs are
not defined.
• Some of the SFR may not be bit-
addressable, while some are both byte-
addressable and bit-addressable.
• For example, the instruction
SETB 0E0H
sets the bit 0 in the accumulator, ACC at
address E0H whereas the instruction
MOV A, #01010101B
will write the accumulator with the
value 01010101B or in hex, 55H.
• Also notice that all I/O ports are in SFR,
at addresses 80H (Port 0), 90H (Port 1),
A0H (Port 2) and B0H (Port 3).
17
Following sections will discuss the functions of each SFRs.

2.2.5.1 Program Status Word (PSW)

• PSW internal address D0H with reset value 00H.


• It is bit addressable: i.e. PSW.0 - PSW.7
• Contains several status bits that reflect the current state of CPU as
summarized below:
BIT SYMBOL ADDRESS BIT DESCRIPTION

PSW.7 CY D7H Carry Flag


PSW.6 AC D6H Auxiliary Carry Flag
PSW.5 -- D5H Undefined
PSW.4 RS1 D4H Register Bank Select 1
PSW.3 RS0 D3H Register Bank Select 0
PSW.2 OV D2H Overflow Flag
PSW.1 -- D1H Undefined
PSW.0 P D0H Parity Flag
18
• Carry Flag (C or CY) is used for arithmetic operations where it will be
set when:
o there’s a carry out of bit 7 during addition (ADD) operation
o there’s a borrow into bit 7 during a subtract (SUB) operation
• For example,
Ex:
Result:
MOV R5, #55H
ACC =
MOV A, #0AAH
ADD A, R5 C=
ACC =
ADD A, #1
C=
• CY flag is also the “Boolean Accumulator”, serving as a 1-bit register for
Boolean instruction operation operating on bits.
• For example, the following instruction ORs bit 24H with the CY and
places the result back in the CY flag.

ORL C, 24H
19
• Auxiliary Carry Flag (AC) is set in BCD addition when:
o there’s a carry out of bit 3 into bit 4, or
o the result in the lower nibble is in the range of 0AH – 0FH.
• If the values added are BCD, then the ADD instruction must be
followed by DA A (decimal adjust accumulator) to bring results
greater than 910 back into range.
• For example, (with initial ACC = 0)
Result:
MOV R5, #1 ACC =
MOV A, #9 AC =
ADD A, R5

• AC = 1 as the lower nibble (10102 = A 16 ) is greater than 910.


• Flag 0 is a general purpose flag bit for user applications. Example:
Results:
SETB, F0 PSW.5 =
20
• Register Bank Select Bits (RS1 and RS0) determine the active
register bank.
• Default register bank used is Bank 0, where RS1 and RS0 are cleared
after a system reset.
RS1 RS0
Bank 0 0 0
Bank 1 0 1
Bank 2 1 0
Bank 3 1 1

SETB RS1 1FH


SETB RS0 Bank 3
MOV R7, #1 18H
SETB RS1 17H
CLR RS0 Bank 2
MOV R7, #1 10H
CLR RS1 0FH
SETB RS0 Bank 1
MOV R7, #1 08H
07H
Bank 0
00H
21
• Overflow Flag (OV) is set after an addition or subtraction if there was an
arithmetic overflow.
• For unsigned number addition operation, OV is set to 1 when there is a
carry out of bit 7.
• For signed number addition operation, OV is set to 1 when:
o There’s a carry out of bit 6 to bit 7 and no carry out of bit 7
o There’s a carry out of bit 7 and no carry out from bit 6 to bit 7
• OV is also used in multiplication (MUL AB) and division (DIV AB)
operation.
• For division operation, OV will be set when the division is invalid (B=0).
• For multiplication operation, OV will be set when the product of the
operation is greater than FFH. For example:
Result:
MOV R7, #0FH ACC =
MOV A, #7FH
OV =
ADD A, R7
22
• Parity (P) bit is automatically set or cleared to establish even parity
with the accumulator.
• This bit is set when the number of 1’s in accumulator is odd.
• If the number of 1’s in the accumulator is even, then P = 0. For example,
Result:
MOV A, #10101101B P=

2.2.5.2 B Register (B)


• B register, or accumulator B is used along with the accumulator [Acc]
for multiplication and division process.
• The B register can also be treated as a general-purpose register. It is
bit-addressable through bit addresses F0H to F7H.
• For example:
MOV A, #55H ACC =
MOV B, #22H
B =
MUL AB 23
2.2.5.3 Stack Pointer (SP)

• SP is an 8-bit register at address 81H. It contains the address of the data


item currently in the top of the stack.
• Stack operations include ‘pushing’ data on the stack and ‘popping’ data
off the stack.
o Pushing increments the SP before writing data.
o Popping reads data and decrement s the SP.
• The default value of SP upon system reset is 07H. For example, to
reinitialize the SP with the stack begin at 60H:
7F
MOV SP, #5FH .
.
PUSH A .
.
PUSH PSW .
.
POP PSW 62
61 PSW
POP A 60 A
5F 24
2.2.5.4 Data Pointer (DPTR)
• DPTR is used to access external code or data memory. It is 16-bit
register at addresses 82H and 83H. 82H is for DPL (low-byte) and
83H for DPH (high-byte)
Ex:
MOV A, #01H write 01H into
MOV DPTR, #0FF38H external device
MOVX @DPTR, A location FF38H

2.2.5.5 Port Registers (P0, P1, P2, P3)

• The 8051 consist of Port 0 at address 80H, Port 1 at address 90H,


Port 2 at address A0H and Port 3 at address B0H.
• Port 0 and Port 2 may not be available for general-purpose I/O if
external memory is used.
• Port 3 may also not available for general-purpose I/O if some of
8051 special features, such as interrupts and serial port are used.
• All ports are bit-addressable.
25
Example:

SETB P1.7 [97H ] = 1

MOV P2, #01H [A0H] = 00000001

2.2.5.6 Timer Registers (TMOD, TCON, TH0, TL0, TH1, TL1)

• The 8051 contains two 16-bit timer registers for timing intervals or
counting events.
• Timer 0 is at addresses 8AH (TL0, low-byte) and 8CH (TH0, high-
byte)
• Timer 1 is at addresses 8BH (TL1, low-byte) and 8DH (TH1, high-
byte)
• Timer operation is set by the timer mode register (TMOD) at address
89H and the timer control register (TCON) at address 88H.
26
2.2.5.7 Serial Port Registers

• Used for communicating with serial devices as terminals or modems,


or for interfaces with other ICs with a serial interface.
• Serial data buffer (SBUF) at address 99H, holds both the transmit data
and receive data.
• Modes of operation are programmable through the bit-addressable
serial port control register (SCON) at address 98H.

2.2.5.8 Interrupt Registers

• Interrupts are disabled after a system reset and then enabled by


writing to the interrupt enable register (IE) at address A8H.
• Priority level for each interrupts can be set through interrupt priority
register (IP) at address B8H.
• Both register are bit-addressable.

27
2.2.5.9 Power Control Registers (PCON)

• The PCON register at address 87H contains miscellaneous control bits.

SMOD -- -- -- GF1 GF0 PD IDL


7 6 5 4 3 2 1 0

• The SMOD bit doubles the serial port baud rate when set

• GF1 and GF0 are available for general-purpose flag bits for user
applications.

• The power control bits, power down (PD) and idle (IDL), were
originally available in all MCS-51™ family ICs but are now
implemented only in CMOS versions.

• PCON is not bit-addressable.

28
2.3 Memory Mapping
• The MCS-51™ architecture provides memory expansion capability, in the
form of 64K external code memory and 64K external data memory.
• Extra ROM and RAM can be added as desired. Peripheral interface ICs
can also be added to expand the I/O capability.
• When external memory is used:
o Port 0 is unavailable as an I/O port. It becomes a multiplexed
address (A0 – A7) and data (D0 – D7) bus.
o Port 2 is usually employed for the high-byte of address bus.

2.3.1 Accessing External Code Memory

• External code memory is read-only memory (ROM) enabled by PSEN


signal.
• The hardware connections for external ROM memory are shown in the
next slide.
29
8051 ROM

Port 0 D0 – D7

74HC373

EA D G A0 – A7

ALE G

Port 2 A8 – A15

PSEN OE

30
Read Timing Diagram [From External ROM]

One machine cycle


State 1 State 2 State 3 State 4 State 5 State 6 State 1
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

Oscillator

ALE

PSEN

Port 0 PCL Op PCL Byte 2


code

Port 2 PCH PCH

31
Connections to be remembered:

i) PSEN  OE
ii) EA  Grounded
iii) ALE  G of Latch
iv) Port 0  Lower Address Bus (A0 – A7)
v) Port 2  Upper Address Bus (A8 – A15)

2.3.2 Accessing External Data Memory


• External data memory (RAM) is accessed by read/write memory
enabled (RD and WR) pin on P3.7 and P3.6.
• The only access to external data memory is with the MOVX instruction,
either using the 16-bit DPTR, R0 or R1 as the address register.
• RAMs maybe interfaced to the 8051 the same way as ROMs except:
o the RD line connects to the RAM’s output enable, OE line
o the WR line connects to the RAM’s write enable, WE line.
32
8051 RAM
Port 0 D0 – D7

VCC 74HC373

D Q A0 – A7
EA

ALE
G

Port 2
A8 – A15

RD
OE

WR WE

33
MOVX A, @DPTR [Reading from External Data Memory]

Machine cycle 1 Machine cycle 2

State State State State State State State State State State State State State
1 2 3 4 5 6 1 2 3 4 5 6 1

ALE

PSEN

RD

Port 0 Op Data
PCL DPL
code in

Port 2 PCH DPH

34
MOVX @DPTR, A [Writing onto External Data Memory]

Machine cycle 1 Machine cycle 2

State State State State State State State State State State State State State
1 2 3 4 5 6 1 2 3 4 5 6 1

ALE

PSEN

WR

Port 0 Op Data out


PCL DPL
code

Port 2 PCH DPH

35
2.3.3 Address Decoding
• If multiple ROMs and/or RAMs are interfaced to an 8051, address
decoding is required.
• A decoder IC, such as 74HC138 is used with its outputs connected
to the chip select (CS) inputs on the memory ICs. The 8051 can
accommodate up to 64K each of ROM and RAM.

A15-A13 (CS)
74HC138
A15 C 0 000 RAM #1
A14 B 1
001 RAM #2

A13 A 2 010 RAM #3


3

4 100 ROM #1

5
101 ROM #2
110 ROM #3
6

7
36
Address bus

Data bus

ROM RAM
(8K bytes) (8K bytes)
D0 – D8 D0 – D8
PSEN RD OE
OE
WR W
A0 – A12 A0 – A12
CS CS
CS CS
CS CS
74HC138
0
C 1
B 2
A
3
4
5
6
7

37
2.3.4 Design Problem 1
Design an 8051-based system with 8Kbytes of external data RAM.
(4K*8 bit Memory IC’s are available. Assume internal ROM is used)

Solution
Step 1- Find number of memory blocks needed..
• Target = 8 Kbytes
• Available = 4KBytes
• Needed = 2 blocks of 4KBytes* 8 bits
Step 2- Find the total address line needed to accommodate memory
space given.. 2n = Memory Space
2n = 4K
log2 2n = log2 4K
n log2 2 = log2 4K
n = log2 4K
log2 2
=
P0 to accommodate 8 lines P2 to accommodate another 4 lines
38
(P0.0 – P0.7) (P2.0 – P2.3)
Step 3- Determine number of data bus
• 8 bit= 8 data buses.

Step 4- Determine any control signals used..


• RD  OE, WRWE (As it involved RAM blocks )
• EA  Vcc (Used internal ROM)
• ALE; for latching the lower bytes address
Step 5- Memory Space Allocation and Chip Select
• 2 blocks needed  1 bit address line required as CS
• A12 as CS
Chip Select Upper Bytes Address Lower Bytes Address
(A12 <-> P2.4) (A8-A11 <-> P2.0-P2.3) (A0-A7 <-> P0.0-P0.7)
1111 2 1111 1111 2
12
0000 2 0000 0000 2
1111 2 1111 1111 2
02
0000 2 0000 0000 2
39
Step 3- Draw the connections between 8051 and external RAM

8051 4 K RAM
Port 0 D0 – D7

VCC 74373
D Q A0 – A7
EA
ALE G
4 K RAM
P2.0 – P2.3 A8 – A11

A12
P2.4 CS D 0 – D7
RD OE A 0 – A7
WR WE
A8 – A11
PSEN
CS
Not connected
OE
WE

40
2.3.5 Design Problem 2
Design an 8051-based system with 32Kbytes of ROM
(32Kb ROM & RAM ICs are available)

Solution

Step 1- Find number of memory blocks needed..


• Target =32Kbytes
• Available = 32KBytes
• Needed =
Step 2- Find the total address line needed to accommodate memory
space given..
2n = Memory Space
2n = 32K
2n = 25 * 210
2n = 215
n=
P0 to accommodate 8 lines P2 to accommodate another 7 lines
41
(P0.0 – P0.7) (P2.0 – P2.6)
8051 32 K ROM

42
2.3.6 Design Problem 3
You are given 32Kb ROM & RAM ICs. Design an 8051-
based system with 32Kbytes of ROM and 32Kbytes of RAM

Solution
8051 32 K x 8 ROM
D0 – D7
74373
D Q
A0 – A7
G
A8 – A14 32 K x 8 RAM
P2.0 – P2.6
D0 – D7
PSEN OE
A15 A0 – A7
P2.7 CS
A8 – A14

CS
RD OE
WR WE 43
2.3.7 Reset Operation

• The 8051 is reset by holding RST high for at least two machine cycles
and then returning it to low. RST may be activated by a switch, or it may
be activated upon power-up using RC (resistor-capacitor) network.
• The content of on-chip RAM is not affected by a reset operation. The
state of all the 8051 registers after a system reset summarized as:

REGISTER(S) CONTENTS
Program Counter (PC) 0000H
Accumulator (ACC) 00H
B Register 00H
PSW 00H
Stack Pointer (SP) 07H
Data Pointer (DPTR) 0000H
P0, P1, P2 and P3 FFH
Interrupt Priority (IP) XXX00000B
Interrupt Enable (IE) 0XX00000B
Timer Registers 00H
SCON 00H
SBUF 00H
PCON (CMOS) 0XXX0000B 44