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High-Performance Three-Stage Single-Miller
CMOS OTA with no Upper Limit of CL
A. D. Grasso, Senior Member, IEEE, D. Marano,
G. Palumbo, Fellow, IEEE, and S. Pennisi, Fellow, IEEE
Abstract— This paper presents a low-power, area-efficient
three-stage CMOS Operational Transconductance Amplifier
(OTA) suitable for very large capacitive loads, CL. A single Miller
capacitor and an inverting current buffer embedded in the input
stage are exploited to implement the frequency compensation
network. Additional feed-forward path and a slew rate enhancer
are also utilized to improve the large-signal transient response.
Detailed small-signal analysis reveals that the proposed one does
not exhibit an upper limit of drivable CL. The OTA is fabricated
in a standard 0.35-m technology and occupies 0.0027 mm2 of die
area. Under 1.4-V supply and 6.36-A quiescent current
consumption, it provides a DC gain greater than 110 dB and is
stable for any CL larger than 5 nF. Comparison with the state of
the art shows remarkable improvement of both small- and large-
signal performance.
Index Terms— operational transconductance amplifiers, large
capacitive loads, Miller compensation, multistage amplifiers.
I. INTRODUCTION
F EEDBACK amplifiers driving capacitive loads as large as
tens nanofarads are required in many modern applications
such as low-dropout regulators, peak detectors, MEMS,
headphone and LCD drivers [1]-[5]. These amplifiers, often
satisfying low-voltage and low-power constraints, should
exhibit large DC gain, speed and voltage swing. Multi-stage
OTA architectures are widely used in this framework owing to
their inherent high DC gain and linearity, rail-to-rail output
swing and easy class AB behavior [6]-[17]. Of course, to
ensure closed-loop stability, frequency compensation is
mandatory. Serving this purpose, several techniques exploiting
a single Miller capacitor have been recently proposed
demonstrating superior gain-bandwidth product and large-
signal performance as compared to conventional nested Miller
and reversed nested Miller techniques, for a given power
consumption [6]-[13]. Nonetheless, all reported frequency
compensation strategies ensure adequate stability margins
only for a limited range of load capacitor, CL [9], [12]-[13].
Actually, for small CL values, complex and conjugate poles
with high quality factor may arise, causing large peaking in
the frequency response and degrading the gain margin. For
large CL values, non-dominant poles move closer to the OTA’s
unity gain frequency, degrading the phase margin [9]-[12].
Recently, two high-gain two-stage OTAs targeting nF-loads
have been reported. Adaptive output impedance of the first
stage is implemented in [14] along with a gain booster to
achieve a pseudo-single stage amplifier with a wide range of
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1
drivable loads. The solution exhibits excellent performance,
but at the expense of circuit complexity. Moreover, a pole-
zero doublet below the unity gain frequency may arise
increasing settling time. Using the same strategy adopted in
[1], another two-stage OTA is proposed in [15]. Again, it is
found that the circuit complexity and design effort are quite
intricate. In summary, the above mentioned two-stage OTAs
are complex and suffer from phase margin reduction for
increasing values of CL.
True single-stage OTAs offer potential replacement of
multistage architectures. Indeed, frequency compensation is
achieved through the dominant pole associated to CL and,
consequently, unconditional stability for any CL greater than a
suitable minimum value is achieved. However, true single
stage OTAs provide limited DC gain which cannot be
increased by conventional vertical transistor stacking,
especially if operated under low supply voltages.
To overcome this drawback multiple small gain stages have
been added to a simple differential pair in order to achieve an
equivalent single-stage OTA [1]. Although no passive
components are used, circuit complexity and area occupation
are remarkable and, besides, careful choice of circuit
parameters should be performed to render negligible the effect
of parasitic poles. Finally, although not explicitly investigated
in the paper, noise is expected to be much larger as compared
to a simple differential pair. Another alternative solution
exploits nested-current mirrors added to a differential pair for
gain and speed enhancement [16]. The resulting OTA is stable
over a wide range of capacitive loads but shows limited slew
rate. Using a similar approach, slew rate has been enhanced at
the expense of the minimum drivable value of CL in [17]. In
both cases, however, noise is expected to increase
considerably as compared to a single differential pair and even
to a two-stage OTA [18].
With the aim of simplifying circuit topology, while
maintaining superior performance in a wide range of CL, this
paper presents a high-gain three-stage OTA capable of driving
tens of nanofarad. Owing to its very simple topology made up
of a folded-cascode input stage and two cascaded common
source stages, frequency compensation is achieved through a
single Miller capacitor and transistors embedded in the first
and last stage. A slew rate enhancer circuit is also included to
improve large signal response. The solution is prototyped in a
0.35-m CMOS technology and is powered from 1.4-V
supply. It provides DC gain higher than 100 dB and has no CL
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upper limit, being stable for loads greater than 5 nF. taken into account through gmf which, however, has a
Compared to previous OTAs for high-CL applications, the negligible role in the frequency compensation.
proposed one shows a significant improvement in both small- Assuming that gmiri≫1 and CL>>ci, CL>>CC, and neglecting
and large-signal performance metrics as well as reduced area two high-frequency zeros, the simplified transfer function of
occupation. the diagram shown in Fig. 2 is expressed by
A0 1  s z1 
AV ( s )   (1)
II. PROPOSED AMPLIFIER 1  s p  2

1  1  a1s  a2 s 1  s p4 
A. Schematic where
Fig. 1 shows the simplified schematic of the proposed OTA. A0   g m1 g m 2 g m3r1r2 r3 (2)
The first stage is made up of transistors M1-M8 implementing
2g
a folded-cascode differential stage. Simple common source z1  mc (3)
CC
configurations are used for the second and third stage
implemented through M9-M10 and M11-M12, respectively. 1
p1  (4)
The gate of the load transistor of the last stage, M12, is g m 2 g m3r1r2 r3CC  r3CL
connected to the gate-drain of M7 to implement, in
CL  CC g mc  r1c1  r2 c2 
combination with M11, a push-pull output stage with a1  (5)
improved driving capability. Frequency compensation is CL  g m 2 g m3 r1r2CC
achieved through Miller capacitor CC connected between the
 r c  r c C 
output and the source of M5 which, in conjunction with M7- CL  1 1 2 2 C  r1r2 c1c2  (6)
M8, implements an inverting current buffer. Using this a2   g mc 
approach, the gain of the second and third stage can be both CL  g m 2 g m 3r1r2CC
inverting, thus saving (at least) two transistors as compared to
conventional topologies that need an extra non-inverting stage. p4 
 r1c1  r2c2  CC  gmc r1r2c1c2
r1r2c1c2CC (7)
Small-signal transconductances of active transistors are
highlighted by dashed boxes. Hence, the gain-bandwidth product from (2) and (4) is
An additional slew rate enhancer (SRE) is also added to g m1 (8)
GBW 
increase further the current driving capability as required by CL
CC 
large CL values. It is shown within the gray box of Fig. 1. Let g m 2 g m3 r1r2
us briefly explain its operation. In standby condition It is worth noting that  reduces to the usual expression
transistors MN1-MP1 and MN2-MP2 are dimensioned in gm1/CC for CL  g m 2 g m3 r1r2CC . However, since the design targets
order to get at their drains a voltage almost equal to VDD and capacitive loads in the order of several nanofarads, this latter
0, respectively, i.e. MP1 and MN2 are in triode region. condition is not easily met. Finally, phase margin, PM, is
Consequently, MP3 and MN3 are off. When a positive expressed by
(negative) large signal is applied at the non-inverting input,
the output voltage of the first stage, V1, goes high (low). If the
amplitude of the input signal is high enough, MP1 (MN2)
turns into the saturation region and the voltage on its drain
lowers (increases). Consequently, MP3 (MN3) switches on
and provides an additional charging (discharging) current to
CL. It can be noted that MP3 and MN3 do not cause additional
quiescent current consumption since they are OFF in standby
condition (i.e., the SRE operates in class B) and, accordingly,
their influence to the small-signal transfer function of the OTA
is neglected in the analysis to come.
The noise performance of the amplifier is similar to that of a
Fig. 1. Schematic diagram of the proposed amplifier with slew-rate enhancer.
Miller two-stage OTA with current buffer frequency
compensation [18].
B. Small-signal analysis
The simplified block diagram of the proposed three-stage
OTA is shown in Fig. 2. Parameters ri, ci and gmi represent the
i-th stage equivalent-node resistance, lumped capacitance and
active transconductance, respectively. The block diagram of
the first stage clearly shows the embedded nature of the
current buffer, represented with its transconductance, gmc, and
its input resistance, 1/gmc. The feedforward path due to M12 is Fig. 2. Block diagram of the proposed amplifier.

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1  a2GBW
2
  (9) by exploiting a degree of approximation that allows including,
PM  tan 1  tan 1 GBW  tan 1 GBW
a1GBW p4 z1 unlike [19], the stability limits coming from gain margin, as
shown in Fig. 3.
C. Design and simulation results The OTA in Fig. 1 was designed in a 0.35-m CMOS
Analysis of prior art shows that a multi-stage OTA provides technology, for a nominal target load capacitor and DC current
closed loop stability with adequate phase and gain margins in consumption of 30 nF and 6 A, respectively and powered
a limited range of capacitive loads, comprised between CL,min from 1.4-V supply. OTA device sizes and small-signal
and CL,max [6]-[14]. Indeed, for CL<CL,min non-dominant parameters are calculated according to the design guidelines
complex and conjugate poles with high quality factor, Q, reported above, and are summarized in Table I and Table II,
cause large peaking in the loop gain frequency response, respectively. The behavior predicted by (10)-(14) is confirmed
reducing the gain margin [9], [13]. As suggested in [13], CL,min by Fig. 3 where the theoretical phase margin (9) and the
can be estimated by setting Q equal to 1. On the other hand, simulated one, versus CL, are compared. The simulated value
for CL>CL,max non-dominant poles are shifted to lower of gain margin (GM) is also plotted in the same figure. The
frequencies, reducing the phase margin [12]. Thus, CL,max can minimum value of CL yielding Q=1 is from (14) almost equal
be evaluated by setting the phase margin greater than 45° (e.g. to 11 nF. The minimum phase margin is 56° and is achieved
70°). when CL=28 nF which is very close to the value expressed by
As a distinctive feature of the proposed OTA, rising values (10) of 33 nF
of phase margin are observed for sufficiently high values of TABLE I. TRANSISTOR SIZES
CL. Let us briefly demonstrate this feature by introducing stage device size (µm/µm) stage device size (µm/µm)
some analytical approximations in the small-signal model of M0 2/0.5 MN1 1/0.35
the previous sub-section. Assuming that CL>>CL,lim, being first M1,M2 2/0.35 MP1 0.5/1
stage M3,M4 1.5/0.5 slew-rate MN2 0.5/0.5
CL,lim  g m 2 g m3 r1r2CC (10) M5,M6,M7,M8 1/0.5 enhancer MP2 0.5/0.35
equations (5), (6) and (8) can be respectively approximated as second M9 1/0.35 MN3 35/2
stage M10 1.5/0.5 MP3 35/3
C
a1  C  c1r1  c2 r2 (11) third M11 4/0.35
g mc stage M12 4/0.5
 r1c1  r2 c2  CC
a2   r1r2 c1c2 (12) TABLE II. CIRCUIT PARAMETERS
g mc
first stage second stage third stage
g m1 g m 2 g m3 r1r2
GBW  (13) gm1=5.2µA/V gm2=12.0µA/V gm3=54.2µA/V
CL gmc=8.8µA/V r2=5.6M gmf=35.1µA/V
therefore, once CC is set, the non-dominant poles are fixed r1=17.7M c2=7.2fF r3=1.3M
while GBW decreases for increasing CL and, consequently, the c1=7.1fF CC=0.5pF

phase margin increases. It can be concluded that the amplifier

is stable over a virtually unlimited range of load capacitors
higher than CL,min. This latter value can be obtained by solving
equation Q = a2 / a1  1 [13], which yields
g m 2 g m3 g mc r1r2CC CC  r1c1  r2 c2   g mc r1r2 c1c2 
CL, min  (14)
CC2  g mc CC  r1c1  r2 c2   g mc
2

r12 c12  r1r2 c1c2  r22 c22 
It can be argued that a minimum value of phase margin is
present. In principle, the value of CL yielding this minimum
phase margin can be analytically evaluated by setting the
derivative of (9) with respect to CL equal to 0. Unfortunately,
the closed-form expression cannot be found. Nonetheless, Fig. 3. Predicted and simulated phase margin versus CL.
neglecting the effect of z1 and p4, the worst-case phase margin
can be (under)estimated by searching the value of CL that III. EXPERIMENTAL RESULTS AND COMPARISON
minimizes the ratio n/ GBW, where n  1 a2 being the The micrograph of the fabricated OTA is shown in Fig. 4.
natural frequency of the complex and conjugate poles. This The occupied area is 2.510-3 mm2. Figs. 5 and 6 show the
calculation yields CL,lim/2. On the other hand, simulations measured AC open-loop frequency response and unity-gain
showed that CL yielding the minimum phase margin is almost step response, respectively, for different CL values. Table III
equal to the value given by (10). summarizes the main measured amplifier performance which
The presence of a phase margin minimum under high values is compared in detail with that of other recent three-stage
of CL has been already reported for a two-stage OTA in [19], amplifiers in Table IV. Widely-accepted figure-of-merits for
where, despite using a strong approximation of the transfer small-signal and large-signal responses, i.e., FOMS, FOML,
function, the amplifier is designed for the worst-case phase LC-FOMS, and LC-FOML [1], [8]-[9], [12], [15], are adopted.
margin. In this work, we extend this idea to a three-stage OTA It is apparent that the proposed OTA outperforms all the other

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solutions. In particular, even comparing the 30-nF load, which

represents the target CL of the proposed design, with the best
case of all the other OTAs, improvements of 4.27, 3.51,
8.55 and 7.16 of FOMS, FOML, LC-FOMS, and LC-FOM,
respectively, are achieved. Performance improvement is more
noticeable for CL=100 nF since the figures of merit are
roughly proportional to CL for three-stage OTAs [7].
A further comparison including other three-stage OTAs, [6],
[8], a four-stage OTA [11] and also recent high-capacitive-
load single-stage OTAs [1], [16]-[17] and two-stage amplifiers
[14]-[15] is illustrated in Fig. 7. In this case four other figures
of merit were adopted, namely IFOMS, IFOML, [1], [6] [9]-
[10], [12], [15], [17] and AFOMS, AFOML [1], [10], [14],
[16]. Considering only three-stage OTAs [6]-[10], [12] and
CL=30 nF for the proposed solution, the performance
improvement is 4.72, 3.20, 8 and 5.44 for IFOMS,
IFOML, AFOMS and AFOML, respectively.

Fig. 6. Unity-gain transient response for different load capacitors (Xdiv: 4s,
Ydiv: 100mV).

Fig. 4. Chip micrograph of the proposed three-stage OTA.

TABLE III. MEASURED PERFORMANCE PARAMETERS

CL (nF) 5 10 30 100
Idd (A) 6.36
DC Gain (dB) 113
UGB (MHz) 2.88 1.70 0.91 0.43
PM (degrees) 46 48 51 59
GM (dB) 3.4 7.4 13.2 20.3
SR+/SR- (V/s) 0.31/-0.52 0.23/-0.38 0.10/-0.13 0.04/-0.05
1%-Ts+/Ts- (s) 1.8/2.3 1.9/2.1. 2.4/2.6 8.3/7.1

Fig. 7. Benchmarks with the state-of-the-art high-CL amplifiers.

When including single-stage [1], [16]-[17] and two-stage

topologies [14]-[15], a 2.99 and 2.41 increase of IFOMS
and AFOMS is observed. By inspection of Fig. 7b,d it is
apparent that IFOML is only lower than [14] for CL>1 nF,
while AFOML is comparable with [17] and again lower than
[14]. However, from Fig. 7a,c it is evident that [14] shows
poor small-signal performance. Indeed, the average 1-%
settling time in [14] is equal to 2.4 s@15 nF, which is almost
Fig. 5. Measured open-loop AC response for different load capacitors, a:
equal to 2.5 s@30 nF of the proposed solution.
gain, b: phase.

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TABLE IV. MEASURED PERFORMANCE COMPARISON OF RECENT PRIOR-ART HIGH-CAPACITIVE-LOAD THREE-STAGE AMPLIFIERS

Yan [9] Tan [7] Marano [10] Qu [12]

Benchmark This work
(2013) (2015) (2016) (2017)
Load Capacitance (pF) 1,000 5,000 10,000 15,000 680 10,000 15,000 1,500 18,000 10,000 30,000 100,000
UGB (MHz) 1.37 1.24 1.06 0.95 3.37 2.72 2.38 3.46 1.18 1.70 0.91 0.43
Phase Margin (degrees) 83.2 69.8 57.2 52.3 45 55.42 47 75.5 59.6 48 51 59
Average SR (V/s) 0.59 0.50 0.30 0.22 0.67 0.53 0.30 1.46 0.22 0.305 0.115 0.045
Average 1% TS (s) 1.28 1.71 3.66 4.49 1.2 0.49 0.93 0.57 4.1 2 2.5 7.7
Total Current (A) 72 10.5 24.49 58 6.36
Power (W) 144 12.7 48.98 69.6 8.904
Total Capacitance, CT (pF) 2.6 0.587 1 1.524 0.5
Total Resistance (k) 171.4 247.56 – 459.6 –
Chip Area (mm2) 0.016 0.0032 0.00297 0.013 0.0025
CMOS Technology (m) 0.35 0.13 0.35 0.18 0.35
FOMS=GBWCL/Power 9,514 43,056 73,611 98,958 180,441 546,185 716,867 74,569 305,172 1,909,254 3,066,038 4,829,290
[(MHz)·(pF)/(mW)]
FOML= SRCL/Power 4,097 17,361 20,833 22,917 35,874 110,442 90,361 31,466 56,897 342,543 387,466 505,391
[(V/s)·(pF)/(mW)]
LC-FOM S  GBW Power  CL CT 3,659 16,560 28,311 38,061 307,395 557,982 716,867 48,930 200,244 3,818,509 6,132,075 9,658,850
[(MHz)/(mW)]
LC-FOM L  SR Power  CL CT
1,576 6,677 8,013 8,814 61,114 108,207 90,361 20,647 37,334 685,085 774,933 1,010,782
[(V/s)/(mW)]

IV. CONCLUSION
In this paper a three-stage OTA capable of driving very
large capacitive loads is presented. The proposed solution
exploits a single-Miller capacitor and an inverting current
buffer embedded in the first (folded-cascode) stage to achieve
frequency compensation. Exploiting simple common source
configurations for the second and third stage, the amplifier
shows a very compact circuit topology. Small-signal analysis
demonstrates that the OTA is stable for capacitive loads higher
than a minimum value, like a single-stage OTA. Moreover, the
transient response is boosted through a push–pull output
configuration and a class-B slew rate enhancer circuit.
The OTA is implemented in a 0.35-m CMOS technology
and experimentally tested. It achieves the highest figure of
merits (both in small signal and large signal conditions) as
compared to all previously published three-stage OTAs and
most single- and two-stage OTAs as well.
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