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INTRODUCTION
The Fermi-FET technology brings the Fermi level nearer to the gate.
This technology merges the mobility and low drain current leakage of BCA
devices as well as the higher short channel effect immunity of SCI devices.
This paper highlights aspects of the technology in a non-mathematical
presentation to give a sound general understanding of why the technology is
the most promising avenue for advanced very short devices.
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Fermi-FET Technology
channel technology to overcome the known shortcomings of buried channel
while maintaining large improvements in channel mobility.
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Figure (a)
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BASIC FET
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Modern Complementary MOS (CMOS) processes incorporate
polysilicon gate structures less than 0.25 micron long, with the most common
process being 0.15µm. At this geometry, and the standard 1.8 volt Vdd, oxide
spacers and drain extensions are common. Most processes also make use of the
oxide spacer to form salicide on the gate and diffusions to reduce the sheet
resistance and to control the polytime constant on wide transistors.
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Fermi-FET Technology
Most short channel CMOS processes create SCI type transistors for
both P and N-Channel devices. This decision has evolved as line widths
attained shorter dimensions primarily due to the reduced short channel effect
sensitivity of the SCI devices over the BCA transistor, traditionally used for the
PMOS. Its because of the widely known control problems with deep buried
channel transistor (BCA) technology that most short channel processes
incorporate both n-type and p-type polysilicon gates to create surface channel
inversion (SCI) devices for both transistor polarities.
SCI STRUCTURE
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SCI OPERATION
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Device scaling has forced the gate oxide to become ever thinner and
the average doping in the well region to increase. These lead to reductions in
carrier mobility; the ease with which charges can move through the transistor
producing drive current.
Figure 3 – The same region as in Fig. 2, but the gate bias is now just
above the threshold. The depletion region has reached its maximum depth and
a thin region of “inverted” silicon (n-type carriers in p-type silicon) exists just
below the gate oxide. The arrows represent the vertical field and consist of two
parts. The first part supports the depletion region and the second part reflects
the carriers in the inversion layer.
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The thin gate oxide and high vertical electric fields have caused a new
challenge not previously large enough to cause difficulties; polysilicon
depletion. Polysilicon depletion occurs when free carriers are swept away from
the bottom of the poly gate due to high vertical fields. In an SCI type of device,
this occurs when the transistor is fully turned on. As can be seen in Figure 3,
this depletion causes the gate dielectric to appear thicker than it actually is,
reducing transistor performance.
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Fermi-FET Technology
At longer channel widths, the BCA architecture was widely used for
the P-Channel transistor in CMOS processes. This was primarily done because
the BCA transistor would use the same n-type polysilicon gate used by the N-
Channel device, greatly simplifying the process. Recently it became apparent
to most manufacturers that the BCA architecture was incapable of scaling to
the very fine line widths in development today. The added process complexity
of using both n-type and p-type poly was offset by the better SCE immunity of
the SCI transistor.
BCA STRUCTURE
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Fermi-FET Technology
BCA OPERATION
………….(1)
This potential causes carrier depletion on either side of the
metallurgical junction. The widths of these depletion regions are proportional
to the relative doping of the p and n regions. In traditional BCA architectures,
the “channel” region is more highly doped than the well region beneath it. The
arrows in Figure 6 show the vertical electric fields present with the gate
electrode at zero bias.
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Fermi-FET Technology
The dashed line depicts the location of the p-n junction and depleted
silicon is shown as a white area. The arrows represent the vertical field
direction. Note that the junction potential is not high enough to fully deplete
the entire channel region. There is another field due to the gate work function
that also depletes the surface part of the channel region.
…………..(2)
This potential also causes some depletion of charge near the
bottom surface of the gate. Since the gate doping is usually very high the
depletion width in the gate is small, but as channel lengths shrink, this can
become an important effect in the subthreshold region.
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Fermi-FET Technology
Figure 6 shows the vertical electric field in the wafer with the gate
electrode at zero bias (as in Fig. 5). Note that the field reverses direction within
the channel region where the depletion from the junction Wjn meets the
depletion induced from the gate electrode Wpn.
As the gate electrode bias is moved from zero towards V dd , the field
from the gate initially decreases reaching zero at Vt . The gate field then
reverses and begins to climb as more charge is injected into the channel at the
source electrode. Figure 7 shows the conduction channel forming just above
the junction depletion region.
Figure 7 – The channel region from Fig. 5 above, with the gate bias at
just above the threshold voltage. The channel begins to open near the edge of
the junction depletion region and widens toward the surface as neutral silicon
until the surface is reached. High-level injection begins after this point.
ADVANTAGES OF BCA
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Fermi-FET Technology
• First, the vertical field within the channel is substantially lower in a BCA
device. This is because the gate does not have to deplete majority carriers away
from the interface to form a channel. The gate supplied vertical field is due only
to the mobile conduction charge.
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Another benefit of this type of device is that the poly depletion occurs
at the off state. Poly depletion negatively affects leakage but not drive current.
This is in itself a rather important development and hence needs to be
optimized further to suit growing demands on semi-conductor technology.
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improves the 2D degradation, but the mobility reduction with the added doping
removes the drive current advantage.
The problems associated with BCA devices all spring from the fact
that the channel opens from the bottom, significantly removed from the gate.
This lack of “gate coupling” leads to the poor subthreshold swing and limits
the minimum attainable channel length. These problems can b esummarised as
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Fermi-FET Technology
The channel of a BCA device first opens at the edge of the channel
side depletion region caused by the p-n junction (see Figure 7). If the doping
density in the channel layer is lowered, or the layer is made thinner, the
channel will open closer to the gate oxide interface. Eventually there will not
be enough dopant in the channel layer to completely satisfy the space-charge
requirement of the junction below it. With less dopant in the channel than the
junction requires, the conduction path will open at the silicon surface similar to
a SCI device, but the conduction in this type of transistor will be majority
rather than minority carriers. Hence the name Surface Channel Accumulation
or SCA transistors.
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THE FERMI-FET
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small amount of DIBL penalty for this device, but even at the BCA end of the
threshold spectrum it is still a reasonable amount. Higher operating voltages
allow an even greater performance improvement due to increased overdrive,
but lower operating voltages (further scaling) require threshold voltage
lowering techniques.
FERMI-FET OPERATION
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Fermi-FET Technology
With the junction depletion using most or all of the dopant in the n-
channel, an interesting aspect of SCA devices occurs. Equation 2 defines a
built-in potential associated with a gate electrode added above the oxide in
Figure 13. Movement of charge between the polysilicon gate and the silicon
must balance this potential, but there is not enough charge left within the
channel region to deplete and satisfy the potential difference.
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A B
Note that the current flow while at the surface near the source is not
tightly bound to the interface by a strong vertical field as in a SCI device. At
the drain end of the channel, the current flow actually moves significantly
away from the interface due to the relatively high drain bias. The low vertical
field is one of the main contributors to the significant increase in channel
mobility of this type of transistor.
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Fermi-FET Technology
At this gate bias, the channel region contains many more free
electrons than holes, but the electron concentrations are still far short of the
ionized donor atom population. Charge neutrality has not yet been reached, so
no carrier accumulation in the channel has occurred. We define threshold of
SCA or Fermi-FET devices as the point at which the channel carrier
concentration exceeds the net chemical dopant concentration; the onset of
strong accumulation.
The Figure ‘C’ shows still higher gate bias with a dashed white line
representing the electron concentration of 1017 cm-3 at the source diffusion. 1017
is roughly the net dopant concentration in the channel so the line roughly
represents the boundary between strong and weak accumulations. The
transistor has not yet reached Vt , although the channel charge and drain current
are both rising rapidly. The high threshold is a potential drawback of this type
of device. If it were not possible to overcome this limitation, it would be
unusable for low voltage applications.
C D
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Fermi-FET Technology
in the channel. This can be seen in the high gm values (about 3X higher than
SCI) near threshold. Figure 17 shows a Fermi-FET transistor in saturation
along with a surface channel device of identical size for comparison.
PERFORMANCE COMPARISON
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Fermi-FET does not permit enough overdrive to match the saturation current
seen in the inversion device.
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threshold voltage is dropped by increasing the channel doping or making the
channel deeper, the device will move into the BCA mode of classical buried
channel transistors with it’s poor short channel performance.
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……(3)
• V 2 quantifies the voltage induced across the depletion region below the
fermi-tub:p-well junction.
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• V 3 represents the voltage across the fermi-tub itself. This is made up of
the depletion region above the fermi-tub:p-well junction and depletion between
the junction induced depletion region and the silicon surface due to the gate
field.
• V 4 quantifies the voltage developed across the gate oxide due to the field
from the polysilicon gate terminating on charge in the region defined as V 3 .
………….(4)
With the tub fully depleted by the junction in a Fermi-FET, there will
be virtually no vertical gate field at threshold, so V4 reduces to zero. This
means that the threshold voltage of a Fermi- FET transistor using a polysilicon
gate reduces to just V 1 +V 2 +V 3 .
……….(5)
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Equation 5 shows that lowering the threshold voltage of a Fermi-FET
is best accomplished by changing the first term. Large changes to the second
term would move the device away from the Fermi-FET region. This is opposite
to the traditional methods of threshold control.
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same material would serve for both the P-Channel and N-Channel transistors.
Such materials are Tungsten, Titanium Nitride, Tungsten Silicide, and several
others not shown in the graphic.
APPLICATIONS
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Fermi-FET Technology
• DSP - Due to the increasing ASSP nature of the DSP market, in contrast
to the MPU market, designs are introduced based upon specific market
demands. This allows easier introduction of a new device or process technology
into the product line. An existing CMOS line may be run in parallel with a new
Fermi-FET line to support existing products, while existing products are
redesigned, if feasible, and new products are being introduced. The technical
benefits to be derived from the Fermi-FET technology for DSP products are
expected as follows:
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• MPU - For standard MPU products which are more performance-driven,
rather than price- driven, the Fermi-FET must be introduced at an appropriate
point in the technology roadmap. The MPU products require the highest
performance possible, but are also very sensitive to time-to-market requirements
and need design information which is timely and as accurate as possible.
Technology scalability is also extremely important. Scaling the device to very
deep-submicron linewidths, while retaining the performance advantages at
longer linewidths is possible. Thunderbird is currently working on methods to
extract Fermi-FET design information from measured data and/or simulations in
a way that is compatible with existing commercial EDA tool sets. This is
critically important. Product designers need to learn how to design with the
Fermi-FET as quickly as possible, and the device characteristics need to be
incorporated within the design methodology as smoothly and efficiently as
possible.
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need to be redesigned, to take advantage of the expected performance increase.
It would be reasonable to expect to be able to shrink die size based upon the
device performance, for a given linewidth. This of course leads to lower
manufacturing costs.
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FURTHER DEVELOPMENT
• SRAM products
Of course the list above is not exclusive, and there are many more
areas which could benefit from a high performance device architecture such as
the Fermi-FET.Significant manufacturing advantages may surface as well, but
this is simply a reasonable expectation since not enough silicon has been run to
compile a statistical database for any of the Fermi-FET variants made to date.
The expectation is based upon the limited silicon to date, and an intuitive
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understanding of the device sensitivities. Other advantages may surface as
well, particularly with respect to the path-breaking low-threshold technology.
CONCLUSION
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BIBLIOGRAPHY
4. www.thunderbirdtechnologies.org
5. www.commweb.com
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ABSTRACT
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CONTENTS
1. INTRODUCTION 01
2. THE TRANSISTOR STRUCTURE 04
BASIC FET
3. SURFACE CHANNEL INVERSION DEVICES 06
SCI STRUCTURE
SCI OPERATION
PROBLEMS WITH SCI
4. BURIED CHANNEL ACCUMULATION DEVICES 10
BCA STRUCTURE
BCA OPERATION
ADVANTAGES OF BCA
PROBLEMS WITH BCA
5. SURFACE CHANNEL ACCUMULATION 19
6. THE FERMI–FET 20
FERMI-FET OPERATION
PERFORMANCE COMPARISON
FERMI-FET BUILT-IN POTENTIALS
7. APPLICATIONS 32
8. FURTHER DEVELOPMENT 36
9. CONCLUSION 37
10. BIBLIOGRAPHY 38
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