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ABSTRACT
For an electronic product or chip if functional faults that is committed to upgrading the system
exist, then the product or chip is of no use. Therefore, performance. To help PDT, the issues of:
if we take a cache memory, a secondary memory for
high-speed
speed retrieval of data stored where functional The fraction of PDEF in the target design
faults exist. These functional faults in the data stored The induced performance loss by PDEF should be
in the cache can be converted into performance faults addresses
so that the caches can still be marketable. In
processors, caches are designed as Level 1(L1), Level Despite the fact that in it has been demonstrated that
2(L2),, and the least hard disk. If the processor wants the idea of PDEF is relevant to the branch directing
the data from/to memory it checks cks the availability of indicator, this may not continuously be the situation
sit
data in upper-level cache L1 and if the data is found for other execution improvement modules in a
it sends to the processor. If the data is not found in L1, processor design. For instance, the cache design that
it checks in lower level cache L2 and next in L3 and involves a bigger area in recent processors is normally
at the least in slow memory or hard disk. So, in this used to quicken the instructions/data get to process by
process, manyy functional faults may exist which leads replicating a subset of the instructions/data
instructio stored in
to making the processor faulty. So, to protect the slow speed main memory to the small size and fast
cache memory ECC and BIST are used. For a cache memory.
redesign, a PDT cache is used where functional faults
are converted into performance faults. We propose a 2. MEMORY ORGANIZATION
new PDT way ay tagged cache design which leads to
increased performance. This reduces fault rate with 2.1 Basic types and parameters of memory
small hardware overhead by applying BIST or ECC devices in computers
method. Computer memories constitute a common unique
system for execution of the program. Memory devices
Keywords: Cache memory, PDT,, Memory Hierarchy, in computers are utilized for putting away unique
BIST, fault types of data, for example, information, programs,
addresses, literary records and status data on the
1. INTRODUCTION
processor and other Computer devices. Data put away
Recently, performance degradation tolerance (PDT)
in memory devices can be separated into bits,
bits bytes,
has been proposed as another approach to outline and
words, pages, and other bigger information structures,
test a reliable system. The focal point of PDT is on the
which have their own identifiers. In primary memory,
specific performance shortcomings that actuate some
data is put away in memory cells or memory areas.
execution corruption of a system without bri bringing
Memory areas contain data to which an entrance can
about any mistakes for the computational outcomes. It
occur. To read or write data in a memory
memo location, a
has been demonstrated that this thought is appropriate
single memory access task must be executed, which
to numerous segments in a superior processor outline
requires independent control signs to be provided to
the memory.
Memories addressed by address are again classified A register memory takes the nearest position in regard
into three: to the processor ALU. It is an arrangement of
1. Random access memories processor registers. It includes a low access time, little
2. Sequential access memories volume, high cost/bit and fast.
3. Cyclic access memories.
The various levels of the memory hierarchy are shown Because of these localities, the data stacked to the
below in figure 2.2. cache memory is utilized a few times and the
execution time of programs is highly diminished. The
cache can be executed as a multi-level memory.
Contemporary PCs, for the most part, have two levels
of cache storage. In old PC models, a cache memory
was introduced outside a processor. The access to it
was composed over the processor outer system bus. In
the present PCs, the primary level of the cache
memory is introduced in the same IC as the processor.
It altogether accelerates processor's co-operation with
the cache. Few chips have the second level of cache
memory put additionally in the processor's circuit.
The volume of the primary level cache is from a few
thousand to a few a huge number of bytes. The second
level has the volume of several hundred thousand
bytes. A cache memory is kept up by an exceptional
processor subsystem called cache controller.