Data Transfer Instructions Data Transfer Instructions

S. Mnemonic Opcode No. of Comments S. Mnemonic Opcode No. of Comments

No. Bytes No. Bytes
1. IN: - Input data to accumulator from a port 31. MOV D, A 57 1
IN Port- with 8-bit address. The contents of the 32. MOV D, B 50 1
DB 2 33. MOV D, C 51 1
address input port designated in the operand are
read and loaded into the accumulator. 34. MOV D, D 52 1
2. Load accumulator:-This instruction copies 35. MOV D, E 53 1
LDA 36. MOV D, H 54 1
3A 3 the data from a given 16 bit address to the
Address 37. MOV D, L 55 1
accumulator
38. MOV E, A 5F 1
3. Load accumulator indirect: - The contents
LDAX B 0A 1 39. MOV E, B 58 1 MOV: - This instruction is used to copy the data
of the designated register pair point to a
40. MOV E, C 59 1 from one place to another.
4. memory location. This instruction copies
41. MOV E, D 5A 1
LDAX D 1A 1 the contents of that memory location into
42. MOV E, E 5B 1
the accumulator.
43. MOV E, H 5C 1
5. Load H and L register direct: - This instruction Eg: - MOV Rd, Rs (This instruction copies the
LHLD 44. MOV E, L 5D 1
2A 3 loads the contents of the 16- bit memory content of Rs to Rd)
Address 45. MOV H, A 67 1
location into the HL register pair.
6. Load register pair immediate: - The instruction 46. MOV H, B 60 1
LXI B 1 3 47. MOV H, C 61 1
loads 16-bit data in the register pair designated
7. LXI D 11 3 in the operand.Eg: - LXI H,8500H (8500H is 48. MOV H, D 62 1
8. LXI H 21 3 stored in HL pair so that it act as memory 49. MOV H, E 63 1
9. pointer) 50. MOV H, H 64 1
LXI SP 31 3 51. MOV H, L 65 1
10. MOV A, A 7F 1 52. MOV L, A 6F 1
11. MOV A, B 78 1 53. MOV L, B 68 1
12. MOV A, C 79 1 54. MOV L, C 69 1
13. MOV A, D 7A 1 55. MOV L, D 6A 1
14. MOV A, E 7B 1 56. MOV L, E 6B 1
15. MOV A, H 7C 1 57. MOV L, H 6C 1
16. MOV A, L 7D 1 58. MOV L, L 6D 1
17. MOV B, A 47 1 MOV: - This instruction is used to copy the data 59. MOV A, M 7E 1
18. MOV B, B 40 1 from one place to another. 60. MOV B, M 46 1
19. MOV B, C 41 1 61. MOV C, M 4E 1 MOV M,Rs (This instruction copies the content
20. MOV B, D 42 1 62. MOV D, M 56 1 of register Rs to memory location pointed by
63. MOV E, M 5E 1 HL Register)
21. MOV B, E 43 1
22. MOV B, H 44 1 Eg: - MOV Rd, Rs (This instruction copies the 64. MOV H, M 66 1
23. MOV B, L 45 1 content of Rs to Rd) 65. MOV L, M 6E 1
24. MOV C, A 4F 1 66. MOV M, A 77 1
25. MOV C, B 48 1 67. MOV M, B 70 1
26. MOV C, C 49 1 68. MOV M, C 71 1 MOV Rd, M (This instruction copies the
27. MOV C, D 4A 1 69. MOV M, D 72 1 content of memory location pointed by the HL
70. MOV M, E 73 1 register to the register Rd.)
28. MOV C, E 4B 1
29. MOV C, H 4C 1 71. MOV M, H 74 1
30. MOV C, L 4D 1 72. MOV M, L 75 1
 Data Transfer Instructions Branch Instructions
S. Mnemonic Opcode No. of Comments S. Mnemonic Opcode No. of Comments
No. Bytes No. Bytes
73. MVI A, Data 3E 2 1. CALL This instruction is used to call the function.
CD 3
74. MVI B, Data 6 2 Label
75. MVI C, Data 0E 2 MVI: - move immediate date to a register or 2. JMP: -(unconditionally jump) The program
76. MVI D, Data 16 2 memory location. sequence is transferred to the memory location
JMP Label C3 3
77. MVI E, Data 1E 2 specified by the16-bit address given in the
Eg: - MVI Rd, 30H (30h is stored in register Rd) operand.
78. MVI H, Data 26 2
3. JC Label DA 3 JC (conditional jump) Jump on Carry (C = 1)
79. MVI L, Data 2E 2
80. MVI M, 30H(30h is stored in memory location pointed
4. JM Label FA 3 Jump on Minus (S = 1)
MVI M, Data 36 2 5. JNC Label D2 3 Jump on No Carry (C = 0)
by HL Reg)
81. OUT: - Output data from accumulator to a port with 8- 6. JNZ Label C2 3 Jump on Not Zero (Z = 0)
OUT Port-
D3 2 bit addresses. The contents of the accumulator are 7. JP Label F2 3 Jump on Plus (S = 0)
Address
copied into the I/O port specified by the operand. 8. JPE Label EA 3 Jump on Parity Even (P = 1)
82. XCHG: - Exchange H and L with D and E. The
9. JPO Label E2 3 Jump on Parity Odd (P = 0)
contents of register H are exchanged with the contents
XCHG EB 1 10. JZ Label CA 3 Jump on Zero (Z = 1)
of register D, and the contents of register L are
exchanged with the contents of register E. 11. JNZ C2 3 Jump on No Zero (Z = 0)
83. Store H and L register direct: - The contents of register 12. PCHL: - Load program counter with HL contents.
L are stored into the memory location specified by the PCHL E9 1 The contents of registers H and L are copied into
SHLD
22 3 16-bit address in the operand and the contents of H the program counter.
Address
register are stored into the next memory location by
incrementing the operand. 13. RST 0 C7 1
84. SPHL: - This instruction copies H and L register to the 14. RST 1 CF 1 RST: - The RST instruction is equivalent to a 1-
SPHL F9 1 15. RST 2 D7 1 byte call instruction to one of eight memory
stack pointer.
85. STA: - the content of accumulator are copied into the 16. RST 3 DF 1 Locations depending upon the number. The
STA Address 32 3 instructions are generally used in conjunction
memory location. 17. RST 4 E7 1
86. STAX B 2 1 Store accumulator indirect: - The contents of the with interrupts and inserted using external
18. RST 5 EF 1
87. accumulator are copied into the memory location hardware.
STAX D 12 1 specified by the contents of the operand (register pair). 19. RST 6 F7 1
88. XTHL: - This instruction exchanges H and L with top 20. RST 7 FF 1
of stack. The contents of the L register are exchanged 21. This instruction is used to return to the program
XTHL E3 1
with the stack location pointed out by the contents of RET after doing some manipulation for a program to
the stack pointer register. succeed.
Machine Control Instructions
Machine Control Instructions S. Mnemonic Opcode No. of Comments
S. Mnemonic Opcode No. of Comments No. Bytes
No. Bytes 5. NOP 0 1 NOP: - No operation is performed. The
1. DI F3 1 DI (Disable Interrupt): - The interrupt enable instruction is fetched and decoded. However no
flip-flop is reset and all the interrupts except the operation is executed.
TRAP are disabled. 6. POP: - This instruction pop off stack to register
2. EI FB 1 EI (Enable Interrupt): - The interrupt enable flip- pair. The contents of the memory location pointed
flop is set and all interrupts are enabled. POP B C1 1 out by the stack pointer register are copied to the
3. HLT 76 1 HLT (Halt): - The CPU finishes executing the low-order register (C, E, L, status flags) of the
current instruction and halts any further operand.
execution. 7. PUSH H
E5 1
PUSH: - This instruction pushes the register pair
4. SIM 30 1 Set interrupt mask onto stack.
 Arithmetic Instructions Arithmetic Instructions
S. Mnemonic Opcode No. of Comments S. Mnemonic Opcode No. of Comments
No. Bytes No. Bytes
1. ACI Data CE 2 ACI: - Add immediate to accumulator with carry. 36. INR A 3C 1
2. ADC A 8F 1 37. INR B 4 1 INR: - The contents of the designated register or
3. ADC B 88 1 38. INR C 0C 1 memory are incremented by 1 and the result is
4. ADC C 89 1 39. INR D 14 1 stored in the same place. If the operand is a
5. ADC D 8A 1 40. INR E 1C 1 memory location, its location is specified by the
Add Register to Accumulator with Carry contents of the HL registers.
6. ADC E 8B 1 41. INR H 24 1
7. ADC H 8C 1 42. INR L 2C 1
8. ADC L 8D 1 43. INR M 34 1
9. ADC M 8E 1 44. INX B 3 1
10. ADD A 87 1 45. INX D 13 1 INX: - Increment register pair by 1
11. ADD B 80 1 Add Reg./Memory to Accumulator 46. INX H 23 1
12. ADD C 81 1 47. INX SP 33 1
13. ADD D 82 1 The content of operand are added to the content of 48. SBB A 9F 1
14. ADD E 83 1 the accumulator and the result is stored in 49. SBB B 98 1
Accumulator. SBB: - substract with borrow.
15. ADD H 84 1 50. SBB C 99 1
16. ADD L 85 1 51. SBB D 9A 1 Eg: - SBB B
17. ADD M 86 1 52. SBB E 9B 1
18. ADI: - Add immediate value with the content of 53. SBB H 9C 1 SBB M
ADI Data C6 2
accumulator and it is stored in accumulator. 54. SBB L 9D 1
19. DAA 27 1 DAA: - Decimal adjust accumulator. 55. SBB M 9E 1
20. DAD B 9 1 DAD: - Add register pair to HL register. The 16-bit 56. SBI: - Substract immediate from the content of the
contents of the specified register pair are SBI Data DE 2
21. DAD D 19 1 accumulator and the result is stored in Acc.
22. DAD H 29 1 Added to the contents of the HL register and the 57. SUB A 97 1 SUB: - Substract the content of a register or a
23. DAD SP 39 1 sum is stored in the HL register. 58. SUB B 90 1 memory location form the content of accumulator
24. DCR A 3D 1 59. SUB C 91 1 and the result is stored in the accumulator.
25. DCR B 5 1 60. SUB D 92 1
26. DCR C 0D 1 DCR: - The contents of the designated register or 61. SUB E 93 1 Eg: - SUB B
27. DCR D 15 1 memory are M decremented by 1 and the result is 62. SUB H 94 1
stored in the same place. If the operand is memory SUB M
28. DCR E 1D 1 63. SUB L 95 1
29. DCR H 25 1 location, its location is specified by the contents of 64. SUB M 96 1
30. the HL registers. 65. SUI Data D6 2 SUI: - Substract immediate from accumulator.
DCR L 2D 1
31. DCR M 35 1
32. DCX B 0B 1 DCX: - decrement the register pair by 1. Logical Instructions
33. 57. RC 7 1 Return on Carry CY=1
DCX D 1B 1
Eg: DCX H ( it decreases the memory location 58. RM F8 1 Return on minus S=1
34. DCX H 2B 1 pointed by HL pair by 1. 59. RNC D0 1 Return with No Carry CY=0
35. DCX SP 3B 1 60. RNZ C0 1 Return on No Zero Z=1
61. RP F0 1 Return on positive S=0
 Logical Instructions Logical Instructions
S. Mnemonic Opcode No. of Comments S. Mnemonic Opcode No. of Comments
No. Bytes No. Bytes
1. ANA A A7 1 35. CNC: - (conditional call) The program sequence is
2. ANA B A0 1 CNC Label D4 3 transferred to a particular level or a 16-bit address
3. ANA C A1 1 ANA: - logical AND operation is performed with if C=0 (or carry is 0)
4. ANA D A2 1 the specified register or memory with accumulator. 36. CNZ: - (conditional call) The program sequence is
5. ANA E A3 1 CNZ Label C4 3 transferred to a particular level or a 16-bit address
6. ANA H A4 1 if Z=0 (or zero flag is 0)
7. ANA L A5 1 37. CP: - (conditional call) The program sequence is
8. ANA M A6 1 CP Label F4 3 transferred to a particular level or a 16-bit address
if S=0 (or sign is 0)
9. ANI: - (AND operation with immediate data) AND
38. CPE: - (conditional call) The program sequence is
ANI Data E6 2 operation is performed between accumulator and
specified immediate data.
CPE Label EC 3 transferred to a particular level or a 16-bit address
if P=1 (or parity is 1)
10. CC: - (conditional call) The program sequence is
CC Label DC 3 transferred to a particular level or a 16-bit address 39. CPI Data FE 2 CPI: - (compare immediate with accumulator)
if C=1 (carry) 40. CPO: - (conditional call) The program sequence is
CPO Label E4 3 transferred to a particular level or a 16-bit address
11. CM: - (conditional call) The program sequence is
CM Label FC 3 transferred to a particular level or a 16-bit address if P=0 (or parity is 0)
if S=1 (sign) 41. CZ: - (conditional call) The program sequence is
CZ Label CC 3 transferred to a particular level or a 16-bit address
12. CMA: - The content of accumulator is
CMA 2F 1 if Z=1 (or zero flag is 1)
complemented.
42. ORI: - Logical OR operation is performed between
13. CMC 3F 1 CMC: - The carry flag is complemented. ORI Data F6 2
accumulator and immediate data.
14. RPE E8 1 Return on Parity Even P=1
43. RAL: - Each binary bit of the accumulator is
15. RPO E0 1 Return on Parity Odd P=0 RAL 17 1
rotated left by one position through the Carry flag.
16. RRC 0F 1 Return on
44. RAR: Each binary bit of the accumulator is rotated
17. RZ C8 1 Return on Zero Z=0 RAR 1F 1
right by one position through the Carry flag.
18. STC 37 1 STC: - This instruction sets the carry flag. 45. RC: - (conditional call) The program sequence is
19. CMP A BF 1 CMP: -The contents of the operand register or RC D8 1 transferred to a particular level or a 16-bit address
20. CMP B B8 1 memory are compared with the contents of the if C=1 (or carry is 1)
21. CMP C B9 1 accumulator. The result of the comparison is 46. RET C9 1 RET: - Return from subroutine unconditionally
22. CMP D BA 1 shown by setting the flags of the PSW as follows:
47. RIM (Read Interrupt Mas): - This is multipurpose
23. CMP E BB 1 if (A) < reg/mem: carry flag is set.
RIM 20 1 instruction used to read the status of interrupts 7.5,
if (A) = reg/mem: zero flag is set.
24. CMP H BC 1 6.5, 5.5 and read serial data input bit.
if (A) > reg/mem: carry and zero flags are reset.
25. CMP L BD 1 48. XRI: - The content of accumulator are exclusive
XRI Data EE 2
26. CMP M BD 1 OR with the immediate data.
27. ORA A B7 1 49. XRA A AF 1 XRA: - The content of accumulator are exclusive
28. ORA B B0 1 50. XRA B A8 1 OR with specified register or memory location.
29. ORA C B1 1 Logical OR operation is performed between 51. XRA C A9 1
accumulator and specified register and memory 52. XRA D AA 1 Eg: - XRA B
30. ORA D B2 1
31. ORA E B3 1 location. 53. XRA E AB 1 XRA M
32. ORA H B4 1 54. XRA H AC 1
33. ORA L B5 1 55. XRA L AD 1
34. ORA M B6 1 56. XRA M AE 1