FPGA Based SVM Comtroller Report Final

DESIGN AND IMPLEMENTATION OF FPGA BASED SPACE VECTOR
MODULATION CONTROLLER
CHAPTER-1
INTRODUCTION
1.1 INTRODUCTION
Nowadays an inverter is commonly used in variable speed AC motor drives to produce a

variable, three-phase, from a constant DC voltage to AC output voltage. For induction motor
drive it is necessary to control both magnitude and frequency of AC voltage, inverter output
voltage (AC) can be controlled by using PWM technique by varying modulation index. There are
various PWM techniques that is SPWM, SVPWM, among various PWM technique, SVPWM is
used to generate a balanced AC voltage with controlled magnitude and frequency. The eight
feasible states of an inverter are represented as two null-vectors (V0=000 and V7=111) and six
active-state vectors forming a hexagon. SVPWM now approximates the rotating reference vector
in each switching cycle by switching between the two nearest active-state vectors and the null-
vectors. The null vectors are used for freewheeling purpose only. They produce zero voltage
freewheeling path for the line currents in case of inductive loads. At a minimum state to maintain
the effective switching frequency of the power devices, the series of toggling between these
vectors is structured such that only one leg is affected in each step.
In order to impose generated voltage references the implementation of current control in

the rotating reference frame requires an appropriate Pulse Width Modulation (PWM) method.
ramp-comparison method can also be used for this purpose. The trend in digital control of AC
drives to used for space vector PWM. The motor drive described in this work is seen as
particularly well suited to applications requiring independent control of a large power motor for
main motion control and a small power motor for auxiliary motion control. The future for the
proposed motor drive is seen in traction and Electric Vehicle/Hybrid Electric Vehicle (EV/HEV)
applications and also seen in electric ship propulsion. The six-phase high power machine would
be used as the main source of propulsion power. The main objective of this work is to describe a
Space Vector PWM (SVPWM) method appropriate for the six-phase VSI that supplies a six-
phase AC machine. By the SVPWM method the problem that has to be overcome is generation
of unwanted low-order harmonics of the order 6k  1 (k = 1, 3, 5, ...). In other words, the
Dept. of E&EE, SSIT, Tumakuru 2017-18 Page 1

SVPWM method has to produce only required essentials for the AC machine, without any
production of unwanted low-order harmonics. It has been shown recently that if appropriate
SVPWM schemes are used a six-phase VSI can generate practically pure sinusoidal output
voltages(Correa et al., 2003a, b, and c; and Drazen et al., 2006). The SVPWM technique,
proposed in Correa et al. (2003a, b, and c), and Drazen et al. (2006) for sinusoidal output voltage
generation, constitutes the starting point here for the growth of the SVPWM method for the
series-connected, two motor drive.
FPGA is a new key technology used in modern control hardware implementation. Modern
manufactures began to apply there technologies in their applications instead of traditional one’s,
due to widely available features in there controllers. In this work the SVPWM method is realized
in FPGA to control speed of three phase induction motor.

CHAPER 2
PROBLEM STATEMENT
2.1 PROBLEM STATEMENT

PWM controlled power electronic devices find increasing applications in many new
industrial processes involving more stringent performance specifications. This is particularly true
in case of high performance drive systems, uninterruptible power supply and programmable AC
power sources. Since PWM inverters play an important role in each of these applications, the
whole system is dependent on the algorithm controlling the PWM inverter. In recent years, Field
Programmable Gate Arrays have drawn much attention due to its short design cycle, low cost
and high flexibility in terms of programmability. The Field Programmable Gate Arrays (FPGAs)
offer significant advantages over microprocessors and DSPs for high performance, low volume
applications, particularly for applications that can exploit customized bit-widths and massive
instruction-level parallelism. in other hand SVPWM has more significant advantages like
effective elimination of lower order harmonics composed to other PWM techniques. Realisation
of SVPWM using FPGA to drive VSI for control speed of induction motor has more significant
advantages over convention technique.
2.2 OBJECTIVE:
The main objective of the work is to use Space Vector Modulation (SVM) as another
alternative modulation technique which was known to be better than SPWM techniques in
certain areas. Space Vector Pulse Width Modulation (SVPWM) has become the successful
techniques to construct three phase sine wave Voltage Source Inverter (VSI) parallel to control
three-phase motor using vector control method. The VSI have three legs for the three-phase
induction motor and six switching sequences has to be simulated in MATLAB / SIMULINK.
The simulation result will ensure the feasibility of the modulation techniques used on this work
to drive three-phase induction motor. Realization of SVPWM using FPGA through hardware
implementation to control the inverter output voltage and frequency will ensure the better
performance of the system used in this work composed to other conventional system.

2.4 METHEDOLOGIES
The main goal of this work are summarized below
 Good understanding the concepts of three phase Inverter & three phase induction motor
drives.
 Study of various PWM techniques.
 Design and Simulation of Space vector Modulation controller based three phase AC
motor drive using MATLAB/SIMULINK.
 Study of FPGA controller.
 Realization SVPWM using FPGA control of inverter output voltage magnitude and
frequency.
2.5 BLOCK DIAGRAM

In this work single-phase, 230V, 50HZ supply is used as input source which is fed to the
three phase controlled rectifier. The rectifier converts single phase AC supply to DC supply and
is fed to three phase inverter. The three phase inverter converts DC supply to AC supply of
desired magnitude and frequency and output which is used as input to the AC motor drive.
SVPWM technique is used to control the magnitude and frequency as per requirement of AC
motor as shown below.
Fig 2.1 Block Diagram of FPGA based SVM controller for Three-Phase Induction Motor
Analysis of simulation results and hardware results ensures better performance of the system
used in this work.

CHAPTER 3
CIRCUIT DIAGRAM AND OPERATIONS
3.1 THREE-PHASE INVERTER
Inversion is the conversion of DC power to AC power at a desired output current or

voltage and frequency. The terms voltage-fed and current-fed are used in association with the
output from inverter circuits.
A voltage-source inverter (VSI) is one in which the dc input voltage is fundamentally stable and
independent of the load current drawn. The inverter specifies the load voltage while the drawn
current shape is dictated by the load.
A current-source inverter (CSI) is one in which the source, hence the load current is predestined
and the load impedance determines the output voltage. The supply current cannot change
quickly. This current is restricted by series dc supply inductance which prevents sudden changes
in current. The load current magnitude is controlled by varying the input dc voltage to the large
inductance, hence inverter answer to load changes is slow. Being a current source, the inverter
can endure an output short circuit thereby offering fault ride-through properties.
Voltage organize may be necessary to uphold a fixed output voltage when the dc input voltage
parameter is poor, or to control power to a load. The inverter output can be single-phase, three-
phase or multi-phase. for ac motor speed control the variable output frequency may be required
where, in conjunction with current control or voltage, constant motor flux can be maintained.
Inverter output waveforms (either voltage or current) are frequently square wave in nature and
contain harmonics which may lead to compact load efficiency and performance.higher order
harmonics can be reduced by using filters at the output of the inverter and lower order harmonics
can be reduced by using pulse width modulation technique.

Fig 3.1 Three-phase Inverter
Fig 3.2 Gating signal and phase voltages

Table 3.1 Three phase voltage source inverter conducting modes
Voltage
Interval Three Conducting Switches Leg State Vector
1 T1 T2 T3 101 V5
2 T2 T3 T4 001 V1
3 T3 T4 T5 011 V3
4 T4 T5 T6 010 V2
5 T5 T6 T1 110 V6
6 T6 T1 T2 100 V4
Fig 3.3 Eight switching sequence of inverter

The line-to-load neutral voltage Fourier coefficients of inverter is given by

𝑛𝜋 2𝑛𝜋
2 (2+cos −cos )
3 3
VL-LN=3𝜋 𝑉1 (1)
𝑛
The line to load neutral voltage is

2 sin 𝑛 𝜔𝑡
VL-LN=𝜋 𝑉1 ∑𝑛𝑛=1,6𝑟+1 𝑟 = 1,2,3 … .. (2)
𝑛
That is
2 1 1 1
VBN=𝜋 𝑉1 [sin 𝜔𝑡 + 5 sin 5𝜔𝑡 + 7 sin 7𝜔𝑡 + 11 sin 11𝜔𝑡 … … … … .] (3)
Similarly for Vyn and Vbn where ωt is substituted by ωt+2/3 𝜋 and ωt-2/3 𝜋respectively.
The line to line voltage from the equation () with ᾳ=1/3 𝜋, gives Fourier coefficients defined by
𝑛𝜋
4 (cos 𝑛𝜋 )
6
Vn L-L= v1 (4)
𝜋 𝑛
The line to line voltage is thus

2√3 𝑛𝜋 𝑛𝜔𝑡
Vn L-L = 𝑉1 ∑𝑛𝑛=1,6𝑟+1 ‖cos ‖ sin 𝑟 = 1,2,3 (5)
𝜋 6 𝑛
That is
2√3 1 1 1
VRB = 𝑉1 [sin 𝜔𝑡 − sin 5𝜔𝑡 − sin 7𝜔𝑡 + sin 11𝜔𝑡 + ⋯] (6)
𝜋 5 7 11
A six-pulse inverter is composed of six switches S1 through S6 with each phase output
associated to the middle of each inverter leg as shown in Fig 3.1. The output of the comparators
in Fig 3.1 forms the control signals for the three legs of the inverter. Two switches are used in
each phase to form one leg switches in one leg open and close in a corresponding fashion. That
is, when one switch is open, the other is closed and vice-versa. The output pole voltages Va0,

Vb0, and Vc0 of the inverter switch between -Vdc≠2 and +Vdc≠2 voltage levels Where Vdc is
the total DC voltage.
In the Fig 3.2 shows inverter bridge quasi-square output voltage waveforms for a 180° switch
conduction outline. Each switch conducts for 180°, such that no two series associated (leg or
arm) semiconductor switches across the voltage rail perform at the same time. Six patterns
survive for one output cycle and the rate of sequencing these patterns specifies the bridge output
frequency. during the six distinct intervals the conducting switches are shown and can be
summarized as in Table 3.3.
By analyzing a balanced resistive Inductive load the three output voltage waveforms can be
derived as shown in fig 3.1 and considering eight switching sequence, as shown in fig 3.3 using
the matrix in figure 3.3. Effectively the resistors representing of the three-phase load are
consecutively cycled anticlockwise one at a time, being alternately associated to each supply rail.
As it is for all voltage source inverters the output voltage is independent of the load, For the
three-phase system following techniques are used-
 Sinusoidal pulse width modulation technique.
 3rd harmonic pulse width modulation technique.
 Space vector modulation technique.

3.2 PULSE WIDTH MODULATION

In power electronic converters, PWM is used extensively as a means of powering alternating
current (AC) devices with an available direct current (DC) source or for advanced DC/AC
conversion. Variation of duty cycle in the PWM signal to provide a DC voltage across the load in
a specific pattern will appear to the load as an AC signal, or can control the speed of motors that
would otherwise run only at full speed or off. The pattern at which the duty cycle of a PWM
signal varies can be created through simple analog components, a digital microcontroller, or
specific PWM integrated circuits.
Analog PWM control requires the generation of both reference and carrier signals that feed into a
comparator which creates output signals based on the difference between the signals. The
reference signal is sinusoidal and at the frequency of the desired output signal, while the carrier
signal is often either a saw tooth or triangular wave at a frequency significantly greater than the
reference. When the carrier signal exceeds the reference, the comparator output signal is at one
state, and when the reference is at a higher voltage, the output is at its second state. This process
is shown in figure 4.1 with the triangular carrier wave in red, sinusoidal reference wave in blue,
and modulated and unmodulated sine pulses.
Fig.3.4 sinusoidal Pulse width modulation

This is a method in which fixed dc input voltage is given to an inverter and the output is a controlled ac
voltage. This is done by adjusting the on and off periods of the inverter components.
The advantages of PWM control are:

 No additional components are required with this method.

Lower order harmonics are eliminated or minimized along with its output voltage control.
Hence, the filtering requirements are minimized since higher order harmonics can be
filtered easily.
Fig.3.5 Three-Phase Sinusoidal PWM:

a) Reference Voltages (a,b,c) and Triangular Wave
b). Va0, c) Vb0, d) Vc0 e) Line-to-Line voltages
As seen in Figure 3.5 the pulse widths depend on the intersection of the triangular and sinusoidal
waveforms. The inverter output voltages are determined as follows:
if
Va>VT then Va0 = 0.5Vdc
Vbc>VT then Vb0 = 0.5Vdc
Vca>VT then Vc0 = 0.5Vdc
And if
Va<VT then Va0 = -0.5Vdc
Vbc<VT then Vb0 = -0.5Vdc
Vca<VT then Vc0 = -0.5Vdc.
The inverter line-to-line voltages are obtained from the pole voltages as:

Vab = Va0-Vb0
Vbc = Vb0-Vc0
Vca = Vc0-Va0
The rms output voltage can be varied by varying the modulation index M. Modulation
index, M can be defined as-
𝐴𝑀𝑃𝐿𝐼𝑇𝑈𝐷𝐸 𝑂𝐹 𝑆𝐼𝑁𝐸 𝑊𝐴𝑉𝐸

MODUALATION INDEX =
𝐴𝑀𝑃𝐿𝐼𝑇𝑈𝐷𝐸 𝑂𝐹 𝐶𝐴𝑅𝑅𝐼𝐸𝑅 𝑊𝐴𝑉𝐸
3.3 SPACE VECTOR MODULATION TECHNIQUE

Space vector modulation (SVM) for three-leg VSI is based on the representation of the three
phase quantities as vectors in a two-dimensional (a,b ) plane.
Considering the Fig 3.6 we see that the line voltages Vab, Vbc, and Vca are given by
Vab= Vg
Vbc = 0
Vca = -Vg
This can be represented in the a,b plane as shown in Fig. 3.7, where voltages Vab, Vbc, and Vca
are three line voltage vectors displaced 120° in space. The effective voltage vector generated by
this topology is represented as V1(pnn) in Fig. 3.7. Here the notation ‘pnn’ refers to the three
legs/phases a, b, c being either connected to the positive dc rail (p) or to the negative dc rail (n).
Thus ‘pnn’ corresponds to ‘phase a’ being connected to the positive dc rail and phases b and c
being connected to the negative dc rail

Fig 3.6 V1(pnn) of a voltage source inverter
Vab = Vg (1)
Vbc = 0 (2)
Vca = -Vg (3)
Fig. 3.7. Representation of a,b plane.
Proceeding on similar lines the six non-zero voltage vectors (V1 - V6) can be shown to assume
the positions shown in Fig.3.8 The tips of these vectors form a regular hexagon (dotted line in
Fig. 3.8. We define the area enclosed by two adjacent vectors, within the hexagon, as a sector.
Thus there are six sectors numbered 1 - 6 in Fig.3.8

Fig. 3.8 Non-zero voltage vectors in the a,b plane
Considering the Fig.3.9 for the sake of convenience we see that the output line voltages
generated by this topology are given by
Vab = 0
Vbc = 0
Vca = 0
These are represented as vectors which have zero magnitude and hence are referred to as zero-
switching state vectors or zero voltage vectors. They assume the position at origin in the a,b
plane as shown in Fig. 3.10. The vectors V1-V8 are called the switching state vectors (SSVs).
Fig. 3.9. Zero output voltage topologies.

Fig.3.10. Representation of the zero voltage vectors in the a,b plane
The desired three phase voltages at the output of the inverter could be represented by an
equivalent vector V rotating in the counter clock wise direction. The magnitude of this vector is
related to the magnitude of the output and the time this vector takes to complete one revolution is
the same as the fundamental time period of the output voltage.
3.3.1 Mathematical Model and Analysis:

A three-phase full bridge inverter is considered. The structure of a typical three phase VSI is
shown in fig. 3.11As shown in fig.3.11, Va, Vb and Vc are the output voltages of the inverter.
Q1 through Q6 are six power transistors that shape the output, which are
Fig.3.11 Three-Phase VSI

Controlled by a, a', b, b', c and c', When an upper transistor is switched on (i.e., when a, b or c is
I), the corresponding lower transistor is switched off (i.e., the corresponding a', b' or c' is 0), the
upper switches of the inverter are labelled with odd numbers whereas the lower switches are
labelled with even numbers. The switches Q1, Q4 are assigned for phase A, Q3, Q6 for phase B
and Q5, Q2 for phase C respectively. The concept of space vectors is used to represent a set of
three phase voltages. The reference voltage vector at the nth sampling instant v*(n) is defined by
The concept of space vectors is used to represent a set of three phase voltages. The reference
voltage vector at the nth sampling instant v*(n) is defined by
v*(n)=2/3[v*a(n)+av*b(n)+a2v*c(n)] ` (1)
a=ej2∏/3
v*a(n)= Em sin(ύnTs)
v*b(n)=Emsin((ύnTs-2∏/3) (2)
v*c(n)= Emsin((ύnTs-4∏/3)
where v*a(n),v*b(n) and v*c(n) are the reference voltages for phases A, B and C respectively.
Taking v*a(n) as the reference, the voltage vector can be resolved in direct and quadrature axes
components as follows:
v*(n)=2/3[v*a(n)+v*b(n){cos2∏/3+jsin 2∏/3}+v*c(n) ){cos4∏/3+jsin 4∏/3}] (3)
or,
v*(n)=2/3[v*a(n)-0.5{v*b(n)+ v*c(n)}+j√3/2{v*b(n)- v*c(n)}] (4)
since the reference voltages for the three phase are balanced, then
v*a(n)+ v*b(n)+ v*c(n)=0 (5)
hence, equation (4) can be further simplified as
v*(n)=2/3[1.5v*a(n)+ j√3/2{v*a(n)+2v*b(n)}]
=v*a(n)+ )+ j1/√3{v*a(n)+2v*b(n)}] (6)
The inverter can generate eight different voltage vectors in the complex plane as shown in fig.
2.2. There are six active vectors(V1 to V6) and two null voltage vectors(V0 and V7).SVPWM
approximates the rotating reference vector in each switching cycle by switching between the two
nearest active-state vectors and the null-vectors.

3.3.2 Modulation process
The voltage vector v*(n) is used for the modulation process to establish the switching table and
their duration. The modulation process needs amplitude and phase angle of the vector v*(n) that
can be considered as
|V(n)|= √R{V(n)}2+J{V(n)}2 (7)
∟V(n)=tan-1J{V(n)}/R{V(n)} (8)
The conduction time of inverter switches are modulated according to the amplitude and angle of
v*(n).The angle of v*(n) evaluated from (8) permits determination of the sector of the complex
vectors in any sector, it is necessary to know the location of the revolving voltage vector from
the adjacent right arm inverter vector. This angular location of the rotating space vector is called
modulation angle α as shown in fig. 2.3. and is considered from
Fig.3.12 Voltage vectors in a three phase inverter and their position in the complex plane
Fig.3.13. Output line voltages in time domain

Fig. 3.14 Resolving voltage vector V(n) on inverter vectors V1, V2, having magnitudes of Vx and Vy.
∟V(n)=(p-1)∏/3+ α (9)
Or,
α=∟V(n)-(p-1)∏/3 (10)
where ‘p’ is the sector number as recognized in fig. 2.2.the active voltages and switches
for modulation are resolute from table 1.since the inverter can take one of the eight conduction
states, pulse width modulation can be used to set the preferred voltage vector in the armature. in
the pattern shown in fig. 2.3, the inverter is switched from V1 to V2 with the duty cycle resolute
by the values of Vx and Vy. by referring to fig. 2.3
Vy=2/√3|Vn|sinα (11)
Vx=|Vn|cosα-0.5Vy (12)
For two level PWM, Vx and Vy can have highest magnitude of 2Vs/3. Hence the time
duration of the state’s V1,V2 and V0 are given by
tax=1.5(Vx/Vs)*Ts (13)
ty=1.5(Vy/Vs)*Ts (14)
tz =Ts-tax-ty (15)
where Vs is the dc input voltage. With the conduction (tx+ty+tz=Ts), the available voltage
vector resides within the hexagon created by the six active voltage vectors consequent to six
active states of the inverter
The degrees of freedom we have in the selection of a given modulation algorithm are:

 The choice of the zero vector -whether we would like to use V7 (ppp) or V8 (nnn) or
both.
 Sequencing of the vectors
 Splitting of the duty cycles of the vectors without introducing supplementary
commutations.
Four such SVM algorithms are measured in the next segment, namely:
 The right aligned sequence ( SVM1)
 The symmetric sequence (SVM2)
 The alternating zero vector sequence ( SVM3)
 The highest current not switched sequence (SVM4).
The modulation schemes are described for the case when the orientation vector is in segment 1:
all other cases are circularly symmetric. These modulation schemes are analyzed and their
comparative presentation with respect to switching loss, THD and the peak-to-peak current
ripple at the output is assessed. The analysis is performed above the complete range of
modulation index and for load power factor angle unstable from –90o to 90o.
All space vector modulation schemes accessible here imagine digital performance and hence,
regular sampling, i.e. all duty cycles are pre calculated at the opening of the switching cycle,
based on the value of the reference voltage vector at that moment.
3.4 Space Vector Modulation Schemes

3.4.1 Right Aligned Sequence (Svm1)
A easy way to produce the output voltage vector is to turn-on all the bottom (or top) switches at
the start of switching cycle and then to turn them off sequentially so that the zero vector is split
between V7 (ppp) and V8 (nnn) uniformly. This switching system is shown in Fig. 3.11 for two
sampling periods. The signals in the outline symbolize the gating signals to the upper legs of the
inverter. The method has three switches turn-on and three switch turn-off within a switching
cycle. The presentation of the left associated sequence, where the sequence of vectors is

accurately reverse to the right aligned sequence, is predicted to be related to the right aligned
sequence.
Fig. 3.15.Phase gating signals in SVM1
3.4.2 Symmetric Sequence (Svm2)

This format has been shown in previous works to have the lowest THD. This is because of the
symmetry in the switching waveform can be seen in Fig. 3.12. The number of commutations in
one sampling period is six. Since this system has the similar number of switching’s as SVM1,
with three switch turn-on and three switch turn-offs, their switching losses are estimated to be
similar.
Fig. 3.16 Phase gating signals in SVM2
3.4.3 Alternating Zero Vector Sequence (Svm3)

In this system, known as DI sequence in literature, the zero vectors V7(ppp) and V8(nnn) are
used instead in adjacent cycles so that the valuable switching frequency is halved, as shown in
Fig. 3.13
Fig. 3.17 Phase gating signals in SVM3.

However, the sampling period is still Ts, same as in the further schemes. The switching losses
for this system are projected to be ideally 50% as compared to those of the earlier two schemes
and THD significantly higher due to the existence of the harmonics at half of the sampling
frequency.
3.4.4 Highest Current Not-Switched Sequence (Svm4)

This scheme, known as DD sequence in literature, is based on the information that the switching
losses are approximately proportional to the magnitude of the current being switched and hence
it would be beneficial to avoid switching the inverter leg moving the highest instantaneous
current. This is feasible in most cases, because all adjacent SSV’s differ in the state of switches
in only one leg. Hence, by using only one zero vector, V7(ppp) or V8(nnn) within a given sector
one of the legs does not have to be switched at all, as shown in Fig. 3.14.

Fig. 3.18 Phase gating signals in SVM4.
However, since the choice of the non-zero SSVs is based on the preferred output voltage vector
and the magnitude and phase of the current are determined by the load, it is not all the time
possible to avoid switching the phase carrying the maximum current. In such a case the phase
carrying the second maximum current is not switched and the switching losses are still reduced.
3.5 Field Programmable Gate Array (FPGA)

Field Programmable Gate Array or FPGA, as it is more widely called, is a type of
programmable device. Programmable devices are a class of general-purpose chips that can be
configured for a wide variety of applications. The first programmable device, which achieved a
widespread use, was the PROM (programmable Read-Only Memory). PROMs, a onetime
programmable device comes in two basic versions:
1) The Mask-Programmable Chip programmed only by the manufacturer

2) The Field programmable Chip programmed by end-user.
FPGAs are increasingly being used in motor control applications due to their robustness and
customizability. Microcontrollers have typically been used to implement motor controls, with
computation algorithms executed by software. Some of the challenges in this implementation are
response time, a fixed number of PWM channels, limited communication interfaces and pre-
determined analog triggering. The solution is to use an FPGA. Since, the performance of the
FPGA has not been fully utilized. The FPGA acts as a buffer for PWM generation unit.

The functions taken by FPGA include-generating the PWM signals, calculating of motor
rotational speed, generating the phase conversion control signals.
PWM generation using FPGA
PWM signals are generated from the Spartan-3A process or by writing VHDL program to control
the inverter switches. The switching signal parameters namely switching frequency, the duty ratio
and the number of pulses are easily controlled via VHDL programming language.
HDL Code Generation:

Writing VHDL is tedious and the hand written code still needs to be verified with Simulink and
Simulink HDL coder, once we have simulated the model we can generate VHDL directly and
prototypean FPGA. It also saves a lot of time and the generated code contains optimizations we
hadn’t thought of.
A. Xilinx ISE Software Overview
The ISE Design Suite is the Xilinx design environment which allows us to take the design from
design entry to Xilinx device programming.
The figure shows the flowchart to FPGA design and embedded in a single chip for generating
gate signals to drive the three-phase inverter.
Fig.3.19.Flow chart of FPGA design and Embedded Single chip

The corresponding VHDL program code is generated from the Simulink HDL Coder after
verification and simulation of the design. The VHDL program is verified and simulated using
Xilinx-ISE14.1software.
The FPGA design flow comprises the following steps:
1. Design entry: It should assign constraints such as timing, pin location, and area
constraints, including user constraints (UCF) file.
2. Design synthesis-Synthesize the project design.
3. Design implementation Implement the design which includes the Translate, Map, Place
and Route.
4. Design verification-includes both functional verification (also known as RTL
simulation) and timing verification.
5. Xilinx® device programming-Create a programming BIT file program debugging or to
download to target device of XILINX/SPARTAN-3A process or kit.
Once the program is dump to FPGA kit, it acts as a controller and generates gate signal.

CHAPTER 4
SIMULINK MODELS, HARDWARE AND RESULTS
4.1 MATLAB SIMULINK
In this work MATLAB/SIMULINK is used as a simulation tool. Matlab stands for ‘‘MATRIX
LABORATORY’’ it is developed by mathworks. It is a high-level technical computing language
and interactive environment for algorithm development data visualization, data analysis and
numeric computation. SIMULINK (simulation and link) is a graphical extension to MATLAB
for modeling and simulation of the systems. In SIMULINK, systems are drawn on screen as
block diagrams.
Key features of MATLAB tool.
 Extensive and expandable libraries of predefined blocks.

 Ability to manage complex designs.
 Model explorers to navigate, create, configure, and search all signals, parameters, and
properties of the model.
 Option to run fixed or variable-step simulations of time varying systems.
 Graphical debugger to examine simulation results and diagnose unexpected behavior in
the design.
A Sim-power system extends Simulink with tools for modeling and simulating the generation,
transmission, distribution, and consumption of electrical power. It provides models of many
components used in these systems, including thee phase machines, electric drives, and libraries
of application specific models such as FACTS and wind power generation, harmonic analysis,
calculation of Total Harmonic Distortion (THD), load flow, and other key power system
analyses are automated.

4.2 COMPARISION OF SIMULATION RESULTS OF DIFFERENT PWM

TECHNIQUES
SIMULATION MODEL:
Fig.4.1 Simulink Model of 3-Phase Inverter
Fig 4.1 shows SIMULINK model of three-phase inverter. The following are the parameters used
in the SIMULINK model: Input dc voltage vs=539V, R=10.53Ω, L=0.032H. RMS output voltage
obtained from simulation results is V0 (rms) = 441V, and I0 (rms) = 16.4A.
4.3 SIMULATION RESULTS:

Fig.4.2 Output voltage Waveform of 3-Phase Inverter without Pulse Width Modulation
Fig 4.2 is the output voltage of inverter without Pulse Width Modulation waveform which is
square wave in nature hence harmonics will be more.
Fig.4.3 THD of 3-Phase Inverter without Pulse Width Modulation
The THD analysis of three-phase inverter output voltage is as shown in Fig 4.3. In that we can
observe that the 3rd Harmonic has been eliminated at 150Hz we can observe that the THD
percentage is 29.17%.

Fig.4.4 Output voltage Waveform of 3-Phase Inverter with SPWM technique

Fig 4.4 shows the output voltage of inverter using Sinusoidal PWM technique. In this method
Gate pulses are generated by comparing the Triangular carrier wave and Sinusoidal reference
wave. Here the frequency of carrier wave is 1080Hz, in order to eliminate the harmonics up to
21st Harmonic. Here we can observe that the output voltage is not a pure square wave and each
phase is phase shifted by 1200.
Fig.4.5 THD of 3-Phase Inverter with SPWM technique
Fig 4.5 shows the THD analysis for three-phase inverter output voltage using sinusoidal pulse
width modulation this method and we can observe that the THD percentage is reduced to 23.11%
by eliminating harmonics upto 21st harmonic

Fig.4.6 Output voltage Waveform of 3-Phase Inverter with SVPWM technique
Fig 4.6 shows the output voltage of inverter using Space vector PWM technique that is our
proposed work. Here the pulses are generated based on the Voltage vector sequence.
Fig.4.7 THD of 3-Phase Inverter with SVPWM technique
Fig 4.7 shows the THD analysis of this method and it is having lesser THD percentage i.e.
17.20%, which is suitable for our work.

The simulation results are tabulated in the as shown in table 4.1

Table.4.1 COMPARISON OF SIMULATION PARAMETERS
Sl.No I/P Voltage Resistance Per Inductance per O/P Voltage THD
Phase Phase
Without pulse 539V 10.53Ω 0.032H 441.2 29.17%
width
modulation
With 539V 10.53Ω 0.032H 402.4 23.11%
sinusoidal
pulse width
modulation
With space 539V 10.53Ω 0.032H 426.1 17.20%
vector pulse
width
modulation
By these simulation results we can observe that SVPWM generates lesser THD compared to
without PWM and SPWM, So SVPWM technique is preferred.
4.4 SIMULATION MODEL OF SVPWM
Figure 8.2 shows the typical Simulink model of the speed control of induction motor by
SVPWM technique using MATLAB/Simulink. From simulation result we can observe that speed
controlled is achieved from 1500 rpm to zero by varying voltage from 220V to zero and
frequency from 50 to zero. Simulation result ensures smooth control of speed using SVPWM
technique. Induction motor specification are given in table 8.4

Fig.4.8 simulation model of speed control of induction motor by SVPWM technique
4.4.1 LINE VOLTAGE AND LINE CURRENT
Fig.4.9 is line voltage and line current
4.4.2 SPEED, LINE VOLTAGE, FREQUENCY, TORQUE

Fig.4.10 is speed, line voltage, frequency, torque
4.5 INDUCTION MOTOR SPECIFICATION
Table.4.2 COMPARISON OF SIMULATION PARAMETERS
Parameter Values
Power P0 5.5HP
Voltage V 440V
Frequency 50HZ
Stator resistance 0.435
Rotor resistance 0.816
Stator inductance 2.0e-3
Rotor inductance 2.0e-3
Mutual inductance 69.31e-3

CHAPTER 5
ADVANTAGES AND APPLICATIONS
5.1 ADVANTAGES
1. SVPWM has greater flexibility to reduce switching losses.

2. SVPWM reduces the THD of output voltage.
3. Advantages in FPGA is reprogramming and parallel operation.
4. The THD is reduced to 17.28% by using SVPWM technique.
5.2 APPLICATIONS
The main industrial applications are:
1. In Paper mills
2. Cement industries
3. In Hybrid vehicles

CHAPTER 6
CONCLUSION AND FUTURE SCOPE
6.1 Conclusion
In this Work, Space Vector Modulation (SVM) can be used as another alternative
modulation technique which is known to be enhanced than SPWM techniques in some areas.
Space Vector Pulse Width Modulation (SVPWM) is the successful techniques to build three
phase sine wave Voltage Source Inverter (VSI) parallel to control three-phase motor using vector
control method. For the three-phase induction motor the VSI have three legs, and six switching
sequences have been simulated in MATLAB / SIMULINK. The simulation result shows the
possibility of the proposed modulation techniques to drive three-phase induction motor.
This work consist of rectifier and PWM inverter, in order to keep the ratio stable the
supply voltage and also the supply frequency can be varied and as well the flux remains constant
too. So it is feasible to get a variety of operating zone for diverse speed and torque and also it is
feasible get a variety of synchronous speed with in the region of same torque. Hence the motor
can have a high-quality range of speed control and it is fully utilized
Also from the SIMULINK model for the preliminary of an induction motor with
unsteady parameters, it is reduced that the stator resistance has to be kept low as possible so to
decrease the steady state time during starting and to obtain a smoother start. Increasing the rotor
resistance leads to boosting in the starting torque (maximum torque occurs at a lesser speed)
though, it leads to a rough start. Declining the inductance (either rotor or stator) leads machine to
achieve its steady state faster with a little smaller jerks.
6.2 FUTURE SCOPE

1. By using MATLAB/SIMULINK 2018 the Real-Time control of Induction motor can be
achieved.
2. FPGA can be interfaced with MATLAB 2018 which is not available at present but this
can be utilized in future.

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DESIGN AND IMPLEMENTATION OF FPGA BASED SPACE VECTOR

Nowadays an inverter is commonly used in variable speed AC motor drives to produce a

In order to impose generated voltage references the implementation of current control in

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2.1 PROBLEM STATEMENT

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2.5 BLOCK DIAGRAM

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Inversion is the conversion of DC power to AC power at a desired output current or

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Fig 3.1 Three-phase Inverter

Fig 3.2 Gating signal and phase voltages

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Table 3.1 Three phase voltage source inverter conducting modes

Fig 3.3 Eight switching sequence of inverter

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The line-to-load neutral voltage Fourier coefficients of inverter is given by

The line to load neutral voltage is

The line to line voltage is thus

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3.2 PULSE WIDTH MODULATION

Fig.3.4 sinusoidal Pulse width modulation

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 No additional components are required with this method.

Fig.3.5 Three-Phase Sinusoidal PWM:

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𝐴𝑀𝑃𝐿𝐼𝑇𝑈𝐷𝐸 𝑂𝐹 𝑆𝐼𝑁𝐸 𝑊𝐴𝑉𝐸

3.3 SPACE VECTOR MODULATION TECHNIQUE

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Fig 3.6 V1(pnn) of a voltage source inverter

Fig. 3.7. Representation of a,b plane.

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Fig. 3.8 Non-zero voltage vectors in the a,b plane

Fig. 3.9. Zero output voltage topologies.

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Fig.3.10. Representation of the zero voltage vectors in the a,b plane

3.3.1 Mathematical Model and Analysis:

Fig.3.11 Three-Phase VSI

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v*(n)=2/3[v*a(n)+v*b(n){cos2∏/3+jsin 2∏/3}+v*c(n) ){cos4∏/3+jsin 4∏/3}] (3)

v*(n)=2/3[v*a(n)-0.5{v*b(n)+ v*c(n)}+j√3/2{v*b(n)- v*c(n)}] (4)

v*a(n)+ v*b(n)+ v*c(n)=0 (5)

hence, equation (4) can be further simplified as

=v*a(n)+ )+ j1/√3{v*a(n)+2v*b(n)}] (6)

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3.3.2 Modulation process

|V(n)|= √R{V(n)}2+J{V(n)}2 (7)

Fig.3.13. Output line voltages in time domain

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3.4 Space Vector Modulation Schemes

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Fig. 3.15.Phase gating signals in SVM1

3.4.2 Symmetric Sequence (Svm2)

Fig. 3.16 Phase gating signals in SVM2

3.4.3 Alternating Zero Vector Sequence (Svm3)

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Fig. 3.17 Phase gating signals in SVM3.

3.4.4 Highest Current Not-Switched Sequence (Svm4)

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Fig. 3.18 Phase gating signals in SVM4.

3.5 Field Programmable Gate Array (FPGA)

v(n)=2/3[va(n)+vb(n){cos2∏/3+jsin 2∏/3}+vc(n) ){cos4∏/3+jsin 4∏/3}] (3)

v(n)=2/3[va(n)-0.5{vb(n)+ vc(n)}+j√3/2{vb(n)- vc(n)}] (4)

va(n)+ vb(n)+ v*c(n)=0 (5)

=va(n)+ )+ j1/√3{va(n)+2v*b(n)}] (6)