Académique Documents
Professionnel Documents
Culture Documents
discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/255484200
CITATIONS READS
0 3,779
4 authors, including:
Mohamed Orabi
Aswan University
186 PUBLICATIONS 1,325 CITATIONS
SEE PROFILE
Some of the authors of this publication are also working on these related projects:
Small Wind Turbines in the Rural and urban environment View project
All content following this page was uploaded by Mohamed Saad on 31 May 2014.
Abstract—nowadays, manufacturers of power management problems - when using the driver as a part on a synchronous
integrated circuits (PMICs) are producing devices that integrate buck converter - have been highlighted.
many of the functional blocks required in power supplies in single
tiny chips. This paper highlights the design considerations for
power MOSFET's gate drivers as a part of highly integrated, high II. MOSFET SWITCHING BEHAVIOR
switching frequency (few MHz range) PMICs optimized to be Usually, power MOSFET is modeled using its terminal
fabricated using CMOS fabrication technologies.
capacitances as shown in Fig.1. These non-linear and voltage
The paper is also focused on the effect of parasitic elements
dependent capacitances in addition to the gate–drive circuit
associated with integration of the driver and the power MOSFET
gate parasitic elements on the performance of an integrated buck
output impedance determine the device switching speed.
converter and its effect on the switching time and loss in power
MOSFETs. Finally, a driver has been tested using spice
simulations to validate the theory and the results have been
presented.
Figure.2: Simplified MOSFET turn on transition. Figure.3: Simplified MOSFET turn off transition.
ln (1)
(3)
_ _
Period 2 (t2):
In this period, the gate voltage goes from Vth to miller voltage Where: VF is darin to source voltage when MOSFET is 'ON'
VGP, the gate current continues charging the gate capacitances VDS is drain to source voltage when MOSFET is 'OFF'
the modest delay in rise time and fall time are expected due to
the Miller effect. On the other hand, BJTs that can be
implemented using CMOS fabrication technologies have poor
characteristic and can only provide one type of BJTs [7].
To facilitate higher switching frequency operation and faster
switching, the P and N channel complimentary pair MOSFET
driver is usually used. MOSFET Totem Pole is inverting and
offers voltage gain to improve on the pre driver rise and fall
times. Unfortunately, CMOS driver suffers from shoot through
current, caused by the threshold voltage overlap during on and
off transitions. In order to gain the benefits from CMOS based
Figure.4: Synchronous buck converter
driver, more circuits should be added to the gate driver.
Problems most often encountered with the gate drive circuit are
voltage spikes large enough to breakdown the gate oxide,
oscillation, ringing or false turn-on. Usually, these problems
can be solved by a proper layout and the electrical design of
the driver circuit. To minimize these problems, the following
design rules and precautions should be followed when
designing and laying out driver circuits [8].
Figure.5: Minimizing gate driver impedance.
Switching Loss
Gate Parasitic Efficiency
High Side Low Side
Figure.7: Shoot-trough problem on the low side MOSFET
Parasitic-free 88.3% 204 mW 74 mW
Another type of shoot-through occurs when the high-side RGT 81.8% 1241 mW 164 mW
MOSFET is turning on and a high dv/dt on the drain of the low 100%
RGT + LGT 82.5% 1121 mW 146 mW
side MOSFET couples charge through CGD and make it to turn
on. This phenomenon is illustrated in Fig. 7. It is clearly RGT 86.5% 501 mW 90 mW
50%
noticeable that the faster the high-side MOSFET is turned on, RGT + LGT 86.7% 446 mW 100 mW
the more susceptible the low-side synchronous MOSFET
becomes to dv/dt-induced turn-on [5]. Table.1: Simulation results for synchronous buck
Figure 12: False Turn-on on low side MOSFET caused by gate-source voltage Oscillation.