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Central
Processing
Unit (CPU) Data Bus
Data Bus
Input Registers
Address Bus
Output Address Bus Memory
Unit Control Bus Control Unit (CU)
(I/O Unit) Control Bus
Arithmetic & Logic
Unit (ALU)
Processor Bus
Co-Processor
(e.g. Floating point unit)
hardware (microprogrammed control). Both the Intel 8086 Arithmetic & Logic
Unit (ALU)
family and Motorola 68000 family use microprogrammed
controllers.
a Registers - small, fast memory which usually store data and
addresses associated with the instruction being carried out.
a ALU performs arithmetic and logic operations
ELE 3230 - Part 3 4
Instruction Execution Cycle
Two main steps in the cycle:
1. Fetch the next instruction from main memory
2. Decode and Execute the instruction
The Fetch cycle consists of
i) use the instruction pointer (IP) to set the address bus with the
address of the next instruction and increment the instruction pointer;
ii) wait (few hundred nanoseconds) for data to be transferred to the
data bus from memory; and
iii) read the data from the data bus.
The Execution Cycle consists of
i) Decode the instruction and generate the correct sequence of internal
and external signals
ii) Execute the instruction and restart the Fetch Cycle
ELE 3230 - Part 3 5
Basic Instruction Cycle
START
Fetch the
Next Fetch Cycle
Instruction
Execute
the Execute Cycle
Instruction
HALT
FI DI CO FO EI WO
Instruction 1
FI DI CO FO EI WO
Instruction 2
FI DI CO FO EI WO
Instruction 3
FI DI CO FO EI WO
Instruction 4
FI DI CO FO EI WO
Instruction 5
FI DI CO FO EI WO
Instruction 6
FI DI CO FO EI WO
Instruction 7
FI DI CO FO EI WO
Instruction 8
FI DI CO FO EI WO
Instruction 9
I: Instruction
O: Operand
Fetch Instruction – Decode Instruction – Check Operand – Fetch Operand (if needed) – Execute Instruction – Write Output
(“Operand” is defined in the Instruction Set part)
ELE 3230 - Part 3 8
Introduction to Intel 8086/8088
Microprocessors Some pins have different functions
for two different operation modes.
MAX MIN MIN MAX
{ MODE } { MODE }
MODE MODE
GND 1 40 Vcc GND 1 40 Vcc
AD14 2 39 AD15 A14 2 39 A15
AD13 3 38 A16/S3 A13 3 38 A16/S3
AD12 4 37 A17/S4 A12 4 37 A17/S4
AD11 5 36 A18/S5 A11 5 36 A18/S5
AD10 6 35 A19/S6 A10 6 35 A19/S6
AD9 7 34 BHE/S7 A9 7 34 SS0 (HIGH)
AD8 8 33 MN/MX A8 8 33 MN/MX
AD7 9 32 RD AD7 9 32 RD
10 8086 31 AD6 10 8088 31 HOLD (RQ/GT0)
AD6 RQ/GT0 (HOLD)
11 CPU 30 AD5 11 CPU 30 HLDA (RQ/GT1)
AD5 RQ/GT1 (HLDA)
AD4 12 29 LOCK (WR) AD4 12 29 WR (LOCK)
AD3 13 28 S2 (IO/M) AD3 13 28 IO/M (S2)
AD2 14 27 S1 (DT/R) AD2 14 27 DT/R (S1)
AD1 15 26 S0 (DEN) AD1 15 26 DEN (S0)
AD0 16 25 QS0 (ALE) AD0 16 25 ALE (QS0)
NM1 17 24 QS1 (INTA) NM1 17 24 INTA (QS1)
INTR 18 23 TEST INTR 18 23 TEST
CLK 19 22 READY CLK 19 22 READY
GND 20 21 RESET GND 20 21 RESET
Both have
a 16-bit wide data bus internally in microprocessor
a 20 address pins, including 16 address/data (AD0-AD15) + 4
address/status (A16/S3-A19/S7) for 8086, allowing a maximum
memory address range of 1MByte
a multiplexed address/data pins (8088 only multiplexes 8 pins, AD0-
AD7)
a 2 modes of operation (the maximum and minimum modes)
a Same instruction set
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U U U U OF DF IF TF SF ZF U AF U PF U CF