A 64-bit Decimal Floating-Point Adder
John Thompson, Nandini Karra, and Michael J. Schulte
{jdthompson, nkarra}@wisc.edu, schulte@engr.wisc.edu
Abstract
Due to rapid growth in financial, commercial, and
Internet-based applications, there is an increasing desire to
allow computers to operate on both binary and
decimal floating-point
Consequently,
specifications for decimal floating-point support are
being added to the IEEE-754 Standard for Floating-
Point Arithmetic. In this paper, we present the design
and implementation of a decimal floating-point adder
that is compliant with the current draft revision of this
standard. The adder supports operations on 64-bit (16-
digit) decimal floating-point operands. We provide
synthesis results indicating the estimated area and delay
for our design when it is pipelined to various depths.
1. Introduction
Due to the growing importance of decimal arithmetic
in commercial, financial, and
applications, specifications for decimal floating-point
arithmetic have been added to the draft revision of the
IEEE-754 Standard for Floating Point Arithmetic [1].
This revised standard specifies formats for and operations
on both binary and decimal floating-point numbers.
Formats are specified for decimal floating-point numbers
having widths of 32, 64, and 128 bits, which correspond to
significands of 7, 16, and 34 decimal digits,
respectively [1].
In this paper, we present the design
implementation of a 64-bit decimal floating-point adder
that is compliant with the current draft revision of the
IEEE-754 Standard. To our knowledge, this is the first
implementation of an IEEE-754 compliant decimal
floating-point adder. The design performs addition and
subtraction on 64-bit operands and can be pipelined to
achieve substantial improvements in its critical delay
path. It can also be extended to support operations on 32-
bit and 128-bit decimal floating-point numbers.
Related work on decimal arithmetic includes designs
for fixed-point decimal adders [2-4] and floating-point
decimal processors [5, 6]. Other hardware designs and
software tools for decimal arithmetic are presented in [7].
Our decimal floating-point adder differs from
previous decimal adders in that it is fully compliant with
Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLSI’04) 0-7695-
2097-9/04 $20.00 © 2004 IEEE
University of Wisconsin – Madison
the current draft of the revised IEEE-754 Standard, even in
terms of exception handling and special value cases.
Furthermore, when compared to previous designs, which
typically compute one digit of the result each cycle, our
adder differs in that it is capable of producing one
numbers. complete result each cycle. Additional details on the
design of our decimal adder, including novel techniques for
significand alignment and result correction, are given
in [8].
2. Design and Implementation
A block diagram of our 64-bit decimal floating-point adder
design is shown in Figure 1. Although no pipeline registers
are shown, the adder can be pipelined to best
match the cycle time of a particular system. In Figure 1,
two input operands, an operation specifier, and a
rounding mode specifier flow through the adder as
indicated by the arrows marked in the diagram.
First, the two IEEE-754 decimal encoded numbers
Internet-based
(Operand A and Operand B) are unpacked into their
corresponding sign bits (SA1 and SB1), 10-bit biased
binary exponents (EA1 and EB1), and 16-digit binary
coded decimal (BCD) significands (CA1 and CB1). Next,
the two unpacked operands are ordered according to their
exponent values. Specifically, the operand ordering
requires that the two operands be exchanged if EB1 >
EA1. The potentially exchanged significands and
exponents are denoted with subscripts of two in Figure 1,
while the signs have subscripts of four.
and While the effective operation is determined based on the
operands’ signs (SA4 and SB4) and the operation specifier,
the two unpacked BCD significands are aligned
so that they have the same exponent (ER2). This is
followed by a conversion of the significands from
standard BCD to an excess-3 decimal encoding, an
inversion of the appropriate operand in the case that the
effective operation is subtraction, and expansion of the
sticky bit to a 4-bit digit based on its value and the
effective operation.
At this point the two significands (CA5 and CB5) are
passed into the binary adder, which performs the
necessary addition. The flag bits (Flag), which are used
by the correction unit, are computed in parallel with the
addition.
 with five stages has a critical path delay of 0.98 ns. In
comparison, a 64-bit Kogge-Stone binary adder has an
area of 0.063 mm2 and a critical path delay of 0.60 ns
when implemented using the same design constraints and
standard cell library.

Table 1: Area and delay estimates

Pipeline Area Delay Latency
Depth (mm2) (ns.) (ns.)
1 0.148 3.83 3.83
2 0.154 2.10 4.20
3 0.169 1.46 4.38
4 0.174 1.17 4.68
5 0.199 0.98 4.90

4. Conclusions

In this paper, a hardware implementation for a 64-bit

decimal floating-point adder that is compliant with the
draft revision of the IEEE-754 Standard has been
introduced. A five stage pipelined version of the decimal
floating-point adder has an estimated critical path delay
Figure 1. Decimal floating-point adder design
of 0.98 ns and area of 0.199 mm2 when implemented
using a 0.11 micron CMOS standard cell library.
Next, the computed sum (CR1) undergoes

based on the flag bits, the effective

operation, and the digit carry-outs of the addition. If the
a correction, which is
References
corrected sum exceeds sixteen digits, it is shifted and
rounded. Finally, the result and its sign, which is [1] Draft IEEE Standard for Floating-Point Arithmetic, IEEE,
inc., New York, 2003. Available from:
determined in parallel in the sign unit, are encoded in http://754r.ucbtest.org/drafts/754r.pdf.
accordance with the IEEE-754 decimal encoding [2] M.S .Schmookler and A.W. Weinderger, “High Speed
specification, completing the decimal floating-point Decimal Addition”, IEEE Transactions on. Computers, vol.
operation. C-20, pp. 862-867, August 1971.
[3] W. Bultmann, W. Haller, H. Wetter, and A. Worner,
3. Simulation and Synthesis Results “Binary and Decimal Adder Unit," U.S. Patent
#6,292,819, September 2001.
[4] F. Y. Busaba, C. A. Krygowski, W. H. Li, E. M. Schwarz,
Our implementation was modeled in Verilog at the and Steven R. Carlough, “The IBM z900 Decimal
register transfer level. Functional testing was performed on Arithmetic Unit”, Conference Record of the 35th Asilomar
several corner cases, to uncover uncommon bugs in Conference on Signals, Systems and Computers, Vol. 2, pp.
the design, as well as on over one million pseudo-random test 1335-1339, IEEE, November 2001.
cases. Initial synthesis testing and evaluation have [5] G. Bohlender and T. Teufel, “A Decimal Floating-Point
been performed using Synopsys Design Compiler and LSI Processor for Optimal Arithmetic”, Computer arithmetic:
Logic’s Gflxp 0.11 micron CMOS standard cell Scientific Computation and Programming Languages, pp.
library. Using this library, we have evaluated several 31-58, 1987.
pipelined implementations of our decimal adder, all of [6] M. S. Cohen, T. E. Hull, and V. Carl Hamacher, “CADAC: A
Controlled-Precision Decimal Arithmetic Unit”, IEEE
which are optimized for delay. More specifically, the
design has been synthesized with pipelines depths of one Transactions on Computers, Vol. 32, No. 4, pp. 370-377,
IEEE, April 1983.
(no pipelining) to five in order to explore the tradeoffs
[7] M. F. Cowlishaw, “Decimal Floating-Point: Algorism for
between area, critical path delay, and latency.
Computers,” Proceedings of the 16th IEEE Symposium on
Table 1 show the estimated area, critical path delay, and Computer Arithmetic, pp. 104-111, June 2003.
latency for each pipeline depth. These results show that a [8] J. Thompson, N. Karra, and M. J. Schulte, “A 64-bit
purely combinational decimal floating-point adder Decimal Floating-Point Adder: Extended Version,”
has a critical path delay of 3.83 ns and one pipelined available from http://mesa.ece.wisc.edu.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLSI’04) 0-7695-
2097-9/04 $20.00 © 2004 IEEE