ISSN 2319-8885

Vol.03,Issue.01,
January-2014,
Pages:0066-0072
www.semargroup.org,
www.ijsetr.com

Implementation of ECC with Fault Tolerant System in MLC NAND Flash

Memories
P. PAVANI KUMARI1, VENUGOPAL BASANI2
1
PG Scholar, Dept of ECE, Kaushik College of Engineering, Visakhapatnam, Andhrapradesh-India,
E-mail: pavani.polinati@gmail.com.
2
Asst Prof, Dept of ECE, Kaushik College of Engineering, Visakhapatnam, Andhrapradesh-India.
E-mail: basanigopal2@gmail.com.

Abstract: Error control coding (ECC) is essential for correcting soft errors in Flash memories. Memory cells were the only
circuitries susceptible to transient faults. The supporting circuitries around the memory were assumed to be fault-free. Due to
the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become
susceptible to soft errors as well and must be protected. The key novel contribution of this paper is identifying and defining a
new class of error-correcting codes whose redundancy makes the design of a reliable memory system that can tolerate multiple
errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry. ECC algorithm
correction strength (number of bit errors that can be corrected) depends on the ECC algorithm used to correct the soft errors.
Simple Hamming codes can only correct single bit errors. Reed-Solomon code can correct more errors but limited to multiple
bit errors only. While these schemes have slightly larger latency and require additional parity bit storage, they provide an easy
mechanism to increase the lifetime of the Flash memory devices and achieve higher reliability and reduced hardware overhead.
In this work, efficient fault tolerant memory system architecture can capable of lossless transmission of data and sophisticated
error correction capability is achieved by implementing product code schemes which can reduce different types of soft errors in
the flash memory. This architecture is authorized in Verilog. Behavior simulation is done by using the ISE simulator and
synthesis can be done by using the synthesis Xilinx ISE 9.2i.

Keywords: ECC, NAND Flash Memories, MLC, Fault Tolerant System.

I. INTRODUCTION
Flash memory is a non-volatile computer storage device
that can be electrically erased and reprogrammed. It is
used in memory cards, USB flash drives and solid-state
drives in application platforms such as personal digital
assistants, laptops, computers, digital audio players, digital
cameras and mobile phones. NAND Flash memories are
not preferred over NOR since they have lower erase
times, less chip area per cell which allows greater storage
density, and lower cost per bit and increase maximum
chip capacity so that flash memory could compete with
magnetic storage devices like hard disks. But there are
some limitations of NAND Flash memories.
There are some inherent limitations of NAND Flash
memories. These include write/read d istur bs , data
retention errors, bad block accumulation, limited number
of writes, and stress-induced leakage current. In recent
years, due to cell size scaling, these issues have become
critical. In particular, re-liability of MLC memory
significantly degrades due to reduced gap between
adjacent threshold levels. To enhance the reliability of
NAND Flash memories and support longer lifetimes,
combinations of hardware and software techniques are
used. These include wear levelling, bad block
management and garbage collection. Wear leveling
distributes the data to different physical locations so that all
memory blocks are used approximately the same number
of times. Bad block management marks blocks once they
show unrecoverable errors and avoids mapping data to
the same bad block. While these F l a s h management
techniques increase the life time of Flash memories,
they are not good at correcting soft errors. Error
correction code (ECC) techniques, w h i c h can detect
and correct errors by storing and processing extra
parity bits, have now become an integral part of Flash
memory design
II. NAND FLASH MEMORY, SLC & MLC
NAND Flash memories are accessed much like block
memory devices such as hard disks or memory cards.
A NAND Flash memory bank consists of several
blocks, where each block consists of a number of pages.

Copyright @ 2014 SEMAR GROUPS TECHNICAL SOCIETY. All rights reserved.

 P. PAVANI KUMARI, VENUGOPAL BASANI

The organization of a NAND Flash memory is shown

in Fig. 1. Typical page size for a NAND Flash
memory is around 2 to 16 kB (for multiple bit storage
devices). We assume that each page includes both
information bits and parity bits of ECC. Almost all
NAND Flash memories rely on ECC to detect and
correct errors caused by failures during normal device
operation. The smallest unit that can be programmed or
read simultaneously is a page; for erase operation, the
smallest unit is a block. A page is formed by memory
cells whose gates are connected to the same word line.
Each page is independently encoded/decoded in the
ECC block. There is a page buffer located between
ECC block and memory that temporarily holds the data.
During write, data from I/O bus is serially encoded by
ECC, and written to the desired page location from page
buffer. During read, ECC block processes data in page Fig.2.Conceptual representation of threshold voltage
buffer serially and transfers it to the I/O bus. distributions for (a) SLC and (b) 3-bit MLC in Flash
memory cells.

III.IMPLEMENTATION OF FAULT TOLERENT

SYSTEM
An overview of proposed reliable memory system is
shown inFig.3 and is described in the following. The
information bits are fed into the encoder to encode the
information vector, and the fault secure detector of the
encoder verifies the validity of the encoded vector. If the
detector detects any error, the encoding operation must be
redone to generate the correct codeword. The codeword is
then stored in the memory. During memory access
operation, the stored codewords will be accessed from the
memory unit. Code words are susceptible to transient
faults while they are stored in the memory; therefore a
corrector unit is designed to correct potential errors in the
retrieved codewords. In our design (see Fig. 1) all the
memory words pass through the corrector and any
potential error in the memory words will be corrected.
Similar to the encoder unit, a fault-secure detector
monitors the operation of the corrector unit. All the units
shown in Fig.3are implemented in fault-prone, nanoscale
Fig.1. NAND Flash memory architecture

The structure of a storage cell in a Flash memory is

similar to a regular MOS transistor except that there is an
extra polysilicon strip, referred to as floating gate,
between the gate and channel. Threshold voltage of this
transistor is controlled by adjusting the number of
electrons trapped in the floating gate. In order to improve
the storage capacity of NAND Flash memories, multiple
threshold levels are employed on a single cell, where
each threshold level corresponds to multiple bits of data.
For instance, levels of threshold voltage are necessary
to store bits of data. We assume that multiple bits in a
single cell correspond to the same codeword.Fig.2
illustrates the distribution of threshold voltages for SLC Fig.3. Fault tolerant system
and MLC (3 bit) storage. As the number of storage levels
in- crease, storage density of one cell improves at an circuitry; the only component which must be implemented
expense of reduction in reliability. Today there are in reliable circuitry are two OR gates that accumulate the
devices with 4 bits per cell storage. syndrome bits for the detectors (shown in Fig.4). Data bits

International Journal of Scientific Engineering and Technology Research

Volume.03, IssueNo.01, January-2014, Pages:0066-0072
 Implementation of ECC with Fault Tolerant System in MLC NAND Flash Memories

stay in memory for a number of cycles and, during this product of information vector and a column of X, from
period, each memory bit can be upset by a transient G=[I:X]
fault with certain probability. Therefore, transient
errors accumulate in the memory words over time. In
order to avoid accumulation of too many errors in any
memory word that surpasses the code correction
capability, the system must perform memory scrubbing.
Memory scrubbing is the process of periodically.

Fig.5. Generator matrix for the (15, 7, 5) EG-LDPC

in systematic format; note the identity matrix in the
left columns.

C. Corrector
One-step majority-logic correction is a fast and relatively
compact error-correcting technique. There is a limited
class of ECCs that are one-step-majority correctable
Fig. 4 Fault-secure detector for (15, 7, 5) EG-LDPC code. which include type-I two-dimensional EG-LDPC.
A. Fault Secure Detector
D. One-Step Majority-Logic Corrector
The core of the detector operation is to generate the
One-step majority logic correction is the
syndrome vector, which is basically implementing the
procedure that identifies the correct value of a each bit
following vector- matrix multiplication on the received
in the codeword directly from the received codeword;
encoded vector c and parity-check matrix H: s = c×HT,
this is in contrast to the general message-passing error
and therefore each bit of the syndrome vector is the
correction strategy (e.g., [14]) which may demand
product of the following vector-vector multiply: si = c ·
multiple iterations of error diagnosis and trial
hi T , where hi T is the transposed of the ith row of the
correction. Avoiding iteration makes the correction
parity-check matrix. The above product is a linear binary
latency both small and deterministic. This technique
sum over digits of c where the corresponding digit in it is
can be implemented serially to provide a compact
1.This binary sum is implemented with an xor gate. Since
implementation or in parallel to minimize correction
the row weight of the parity-check matrix is P , to generate
latency. This method consists of two parts: 1) generating
one digit of the syndrome vector we need a P-input xor
a specific set of linear sums of the received vector bits
gate, or (P− 1) 2-input xor gates in a tree structure. For
and 2) finding the majority value of the computed
the whole detector, it takes n(P − 1) 2-input xor gates.
linearsums. The majority value indicates the correctness
An error is detected if any of the syndrome bits has a
of the code-bit under consideration; if the majority value
nonzero value. The final error detection signal is
is 1, the bit is inverted, otherwise it is kept
implemented by an or function of all the syndrome put of
unchanged. The circuit implementing a serial one-step
this n-input or gate is the error detector signal.
majority logic corrector for (15,7, 5) EG-LDPC code is
B. Encoder shown in Fig. 6.
An n-bit codeword, which encodes a n-bit information
Vector i is generated by multiplying the n-bit information
vector with a kXn bit generator matrix; i.e., c=i.G. EG-
LDPC codes are not systematic and the information bits
must be decoded from the encoded vector, which is not
desirable for our fault-tolerant approach due to the
further complication and delay that it adds to the
operation. However, these codes are cyclic codes. We
used the procedure to convert the cyclic generator
matrices to systematic generator matrices for all the EG-
LDPC codes under consideration shown in Fig.5.The Fig.6. Serial one-step majority logic corrector structure
encoded vector consists of information bits followed by to correct last bit (bit 14th) of 15-bit (15, 7, 5) EG-
parity bits, where each parity bit is simply an inner LDPC code.
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.01, January-2014, Pages:0066-0072
 P. PAVANI KUMARI, VENUGOPAL BASANI

E. Majority Circuit Implementation

Here majority circuit implementation gate use Sorting
Networks the majority gate has application in many other
error-correcting codes, and this compact implementation
can improve many other applications. We use binary
Sorting Networks to do the sort operation of the second
step efficiently. An input sorting network is the Structure
that sorts a set of n bits, using 2-bit sorter building blocks.
Fig. 7(a) shows a 4-input sorting network. Each of the
vertical lines represents one comparator which
compares two bits and assigns the larger one to the top
output and the smaller one to the bottom [see Fig. 7(b)].
The four-input sorting network, has five comparator
blocks, where each block consists of two two-input gates; Fig8. The serial corrector must be placed off the
overall the four-input sorting network consists of ten two- normal memory read path.
input gates in total.
This way the corrected memory words are generated
every cycle. The detector in the parallel case monitors the
operation of the corrector, if the output of the corrector is
erroneous; the detector signals the corrector to repeat the
operation. Note that faults detected in a nominally
corrected memory word arise solely from faults in the
detector and corrector circuitry and not from faults in
the memory word. Since detector and corrector circuitry
Fig.7. (a) shows a 4-input sorting network.(b) Each of are relatively small compared to the memory system, the
the vertical lines represents one comparator which failure rate of these units is relatively low.
compares two bits and assigns the larger one to the top
output and the smaller one to the bottom. IV SYNTHESIS & SIMULATION RESULTS
In this paper, the analysis obtained by synthesizing the
F. Serial Corrector Verilog coding for fault Tolerant Memory system are
As mentioned earlier, the same one-step majority-logic shown. The Advanced HDL synthesis Report- Macro
corrector can be used to correct all the n bits of the statistics shows that the Hardware overhead require for the
received codeword of a cyclic code. To correct each code- implementation of this ECC FTM architecture is very low,
bit, the received encoded vector is cyclic shifted and fed which proves that the project implements a Hardware
into to the XOR gates as shown in Fig.6. The serial complexity reduced ECC with FSD in MLC NAND flash
majority corrector takes cycles to correct an erroneous memories.
codeword. If the fault rate is low, the corrector block is
used infrequently; since the common case is error-free A. Synthesis Result of Fault Tolerant System
codewords, the latency of the corrector will not have a
severe impact on the average memory read latency. The
serial corrector must be placed off the normal memory
read path. This is shown in Fig.8 . The memory words
retrieved from the memory unit are checked by detector
unit. If the detector detects an error, the memory word is
sent to the corrector unit to be corrected, which has the
latency of the detector plus the round latency of the
corrector.

G. Parallel Corrector
For high error rates, the corrector is used more
frequently and its latency can impact the system
performance. Therefore we can implement a parallel one-
step majority corrector which is essentially copies of the
single one-step majority-logic corrector. Fig. 1 shows a
system integration using the parallel corrector. All the
memory words are pipelined through the parallel
corrector.
Fig.9. Block level diagram of FTS

International Journal of Scientific Engineering and Technology Research

Volume.03, IssueNo.01, January-2014, Pages:0066-0072
 Implementation of ECC with Fault Tolerant System in MLC NAND Flash Memories

B. Simulation result of fault tolerant system

Fig.12. Waveform of FTS

The above simulation results shows that the data given

in the input has been obtained in the output which proves
Fig.10. Internal Block Diagram of FTS that fault secure Detection Error control coding and also
achieves the Lossless Transmission of data has been by
the fault Tolerant Memory system architecture.

C. Simulation result of encoder

The above designed encoder in the Fault Tolerant
memory system which is obtained by implementing the
simple hamming code (EG LDPC code) along the
columns is programmed using Verilog and is simulated in
Xilinx ise9.2i is shown below.

Fig.11. RTL schematic of Fault tolerant system Fig.12. waveform of encoder in FTS
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.01, January-2014, Pages:0066-0072
 P. PAVANI KUMARI, VENUGOPAL BASANI
The waveforms shows that for input codeword of 7 bit
i[6:0] has given an output of 16 bit codeword c[15:0] by
appending 8 parity bits which obtained by coding the
given figure12.
D. Simulation result of Detector
The above designed Detector in the Fault Tolerant
memory system which consists of a detector circuit is
programmed using Verilog and is simulated.
Fig13. Waveform of fault secure detector in FTS
E. Simulation of Corrector
Fig14. Waveforms of corrector in FTS
F. Simulation Result of RAM
Fig15. Waveform of RAM in FTS
International Journal of Scientific Engineering and Technology Research
Volume.03, IssueNo.01, January-2014, Pages:0066-0072
F. Advanced HDL Synthesis Report
V. CONCLUSION
This project work presents the Error control coding for
MLC NAND Flash memories by using Fault Tolerant
Memory system architecture based on product code
schemes. Error detection and correction or error control is
techniques that enable reliable delivery of digital data
over unreliable communication channels or storage
medium. Error detection is the detection of errors caused
by noise or other impairments during transmission from
the transmitter to the receiver. Error correction is the
detection of errors and reconstruction of the original,
error-free data. Here the proposed Error control
coding(ECC) based on product code schemes, the no of
hardware resources require to implement is also very
much reduced. In this report, a fully fault-tolerant memory
system that is capable of tolerating errors not only in the
memory but also in the supporting logic is designed; Loss
Less transmission of data is possible. The efficient error
control schemes used which can handle both random and
MBU errors. The Designed FTM architecture is modeled
for each block in the Verilog HDL and the synthesis
results prove that the reduction of hardware complexity in
the implementation of proposed ECC in MLC NAND
Flash memories
The designed ECC is flexible, safe and secure way for
the data transmission in real time applications of Flash
memories. To support the above statements, Various
scenarios for each block of the Fault tolerant memory
system is verified effectively during the simulation with
respect to its behavior, which proves that There is no loss
of data or control information in MLC NAND Flash
Memories which can be made possible designing a 128 x
16 RAM. The design can be further extended by
developing a total system around it. For Example, we can
use this proposed ECC in the Various types of Random
Access Memories. The system can be extended further to
implement 15-bit information or data and also to achieve
higher bit error rate and to decrease latency. The system
can be extended further to achieve transistorized level
from the provided gate level design. This project work
provides an ideal platform for enhancement or further
development of the ECC in Flash Memories.
 Implementation of ECC with Fault Tolerant System in MLC NAND Flash Memories

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International Journal of Scientific Engineering and Technology Research

Volume.03, IssueNo.01, January-2014, Pages:0066-0072