Vous êtes sur la page 1sur 87

GOVERNMENT COLLEGE OF ENGINEERING

SALEM-636011

BONAFIDE CERTIFICATE
12EC706-VLSI DESIGN AND NETWORKS LABORATORY
RECORD
DEPARTMENT OF ELECTRONICSAND COMMUNICATION ENGINEERING
(Accredited by NBA)

Certified that this is the Bonafide Record of work done by

Mr/Ms…………………………………………of VII Semester of

Electronics and Communication Engineering during the academic


year 2018-2019.

DATE: STAFF IN CHARGE


Submitted for the practical examination held
on………………………………his/her University Register Number
is…………………….

INTERNAL EXAMINER EXTERNAL EXAMINER

1
VLSI LABORATORY

2
LIST OF EXPERIMENTS (VLSI)

EXP. PAGE STAFF


DATE EXPERIMENT NAME MARKS
NO. NO. INITIAL

Design of Traffic light controller using Verilog 04


1.
and above tools

Design and simulation of pipelined parallel ad- 08


2. der to add 8 number of size 12 bits each in 2’s
complement

Design and simulation of back annotated Veri- 11


log files for multiplying two signed, 8bit num-
3.
bers in 2’s complement. Design must be pipe-
lined and completely RTL compliant.

Study of FPGA board and testing on board 14


4.
LEDs and switches using Verilog codes

25
5. Testing the traffic controller

Design a Real time Clock (2digits, 7 segments 41


6. LED displays each for HRS, MTS, and SECS.)
and demonstrate its working on the FPGA
board.

3
Ex.no:1
Date: DESIGN OF TRAFFIC LIGHT CONTROLLER

AIM:
To design a traffic light controller using Verilog.

SOFTWARE USED:
Xilinx ISE 9.1i Software

THEORY:
Consider a controller for traffic at the intersection of four roads. Consider P1, P2, P3, and P4
as four roads and P5 as pedestrian. The road has following states.

• GREEN-11001
• YELLOW-01000
• RED-00100

The pedestrian
• GREEN-0000
• Red-1111

First the road p1 is green and all other roads p2, p3, p4 and P5 are red. After a some delay p1 is
turn to yellow and then red the traffic signal on p2 is green. After a delay p2 is turn to yellow and then
red the signal on p3 is green. Then p3 is changed to yellow and then red the signal on p4 is changed to
green. After a delay p4 is turn to yellow and then red the pedestrian light P5 is green after a delay P5
is turn to green then routine will continue.

PROGRAM:
module tlc( clk,reset,p1,p2,p3,p4,p5);
input clk;
input reset;
output[4:0]p1;
output[4:0]p2;
output[4:0]p3;
output[4:0]p4;
output[4:0]p5;
reg [4:0]p1;
reg[4:0]p2;
reg[4:0]p3;
reg[4:0]p4;
reg[3:0]p5;
reg[5:0]Sig;
always@(posedgeclk)
begin
if(reset==1'b0)

4
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b1111;
Sig<=6'b000000;
end
else begin
Sig <= Sig+1;
case(Sig[5:0])
6'b000000:begin
p1<=5'b11001;//GREEN
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b1111;
end
6'b000100:begin
p1<=5'b01000;//YELLOW
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b1111;
end
6’b001000:begin
p1<=5’b00100;
p2<=5’b11001;//GREEN
p3<=5’b00100;
p4<=5’b00100;
p5<=4’b1111;
end
6'b001100:begin
p1<=5'b00100;
p2<=5'b01000;//YELLOW
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b1111;
end
6'b01000:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b11001;//GREEN
p4<=5'b00100;
p5<=4'b1111;
end
6'b010100:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b01000;//YELLOW

5
p4<=5'b00100;
p5<=4'b1111;
end
6'b011000:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b11001;//GREEN
p5<=4'b1111;
end
6’b011100:begin
p1<=5’b00100;
p2<=5’b00100;
p3<=5’b00100;
p4<=5’b01000; //YELLOW
p5<=4’b1111;
end
6'b10000:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b0000;//PEDESTRAIN
end
6'b100100:Sig<=6'b000000;
default:begin
end
endcase
end
end
endmodule

6
OUTPUT:

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

RESULT:
Thus the traffic light controller was designed using verilog and simulated successfully.

7
Ex.no:2
Date: PROGRAM FOR PIPELINED PARALLEL ADDER
AIM:
Design and simulation of pipeline parallel adder to add 8 number of size 12 bits each.

SOFTWARE REQUIRED:
Xilinx ISE 9.1i Software

THEORY:
Parallel adder is an adder which adds all the n-bits of m-numbers at a time. Addition is a funda-
mental operation for any digital system, digital signal processing or control system. A fast and accu-
rate operation of a digital system is greatly influenced by the performance of the resident adders. Ad-
ders are also very important component in digital systems because of their extensive use in other basic
digital operations such as subtraction, multiplication and division. Hence, improving performance of
the digital adder would greatly advance the execution of binary operations inside a circuit compro-
mised of such blocks. The performance of a digital circuit block is gauged by analyzing its power dis-
sipation, layout area and its operating speed.

PROGRAM:
module parallel(clk,add,load,clr,data,cal,result);
inputclk,clr,cal,load;
input[2:0]add;
input[11:0]data;
outputreg[11:0]result;
reg[11:0]ram[7:0];
wire[11:0]tem;
always@(posedgeclk)
begin
if(~clr)
begin
ram[0]=12’b0;
ram[1]=12’b0;
ram[2]=12’b0;
ram[3]=12’b0;
ram[4]=12’b0;
ram[5]=12’b0;
ram[6]=12’b0;
ram[7]=12’b0;
end
else if(~load)
ram[add]=data;
end
assign tem=ram[0]+ram[1]+ram[2]+ram[3]+ram[4]+ram[5]+ram[6]+ram[7];
always@(posedgeclk)
begin
if(~load)
result=data;
else if(~cal)
result=tem;
else

8
result=ram[add];
end
end module

PIN DIAGRAM:

9
OUTPUT WAVEFORM:

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100
RESULT:
Thus the Pipelined Parallel Adder was designed by using Verilog, and then output was
verified.

10
Ex.no:3
Date: MULTIPLICATION OF TWO 8 BIT NUMBERS

AIM:
To design and simulate back annotated Verilog files for Multiplying two 8 bit numbers.

SOFTWARE REQUIRED:
Xilinx ISE 9.1i Software

THEORY:
 Assign the clock input to clock and set values to multiplier and multiplicand.
 Check the multiplier and multiplicand are positive, then do the successive addition for
the product.
 Otherwise multiplier is positive and multiplicand is negative , and then do the succes-
sive addition but in successive addition, MSB is replaced by ‘1’ instead of ‘0’.
 If multiplier is negative and multiplicand is positive, then take 2’s compliment of the
multiplicand and do the successive addition for that multiplicand.
 If both multiplier & multiplicand are negative, then take 2’s compliment of the multipli-
cand and do the successive addition, but MSB is replaced by ‘1’ instead of ‘0’.

PROGRAM:
Module multi_signed(prod,multiplicand,multiplier);
output [15:0] prod;
input [7:0] multiplicand;
input [7:0] multiplier;
wire [15:0] shift1,shift2,shift3,shift4,shift5,shift6,shift7,shift8;
wire[15:0] add1,add2,add3,add4,add5,add6,add7,add8;
wire [15:0] prod_s;
assign shift1 ={8'b0, multiplicand};
assign shift2 ={7'b0, multiplicand,1'b0};
assign shift3 ={6'b0, multiplicand,2'b0};
assign shift4 ={5'b0, multiplicand,3'b0};
assign shift5 ={4'b0, multiplicand,4'b0};
assign shift6 ={3'b0, multiplicand,5'b0};
assign shift7 ={2'b0, multiplicand,6'b0};
assign shift8 ={1'b0, multiplicand,7'b0};
assign add1 =(multiplier [0] == 1'b1)? shift1 : 16'b0;
assign add2 =(multiplier [1] == 1'b1)? shift2 : 16'b0;
assign add3 =(multiplier [2] == 1'b1)? shift3 : 16'b0;
assign add4 =(multiplier [3] == 1'b1)? shift4 : 16'b0;
assign add5 =(multiplier [4] == 1'b1)? shift5 : 16'b0;
assign add6 =(multiplier [5] == 1'b1)? shift6 : 16'b0;
assign add7 =(multiplier [6] == 1'b1)? shift7 : 16'b0;
assign add8 =(multiplier [7] == 1'b1)? shift8 : 16'b0;
assign prods = add1+add2+add3+add4+add5+add7+add8;
assign prod=prod_s;
endmodule

11
PIN DIAGRAM:

12
OUTPUT WAVEFORM:

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

RESULT: Thus the design for back annotated Verilog files for multiplying two 8 bit numbers was
simulation.

13
Ex .no:4

Date: STUDY OF FPGA BOADR AND TESTING ON BOARD LED


AND SWITCHES USING VERILOG CODES

AIM:

To study the FPGA trainer kit and testing the on board LEDs and switches using SPARTAN

REQUIREMENTS:

S. NO Item Name Quantity

1. PC 01

2. Xilinx ISE 9.1i Software 01

3 RS232C Interfacing Cable 01

4. JTAG Interface cable 01

5. Spartan III Trainer Kit 01

6. Power Adapter 01

7. Power Cable 01

THEORY:

DIP SWITCHES:

The switches connect to an associated FPGA. The switches are used to give input to the
FPGA or the design implemented on FPGA. A 4.7KΩ series resistor provides nominal input protec-
tion. When in the UP or ON position, a switch connects the FPGA pin to VCCO, a logic High. When
DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The
switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuit-
ry, although such circuitry could easily be added to the FPGA design programmed on the board.

KEY SWITCHES:

The Key switches can provide pulse input to the FPGA. The switches connect to an associated FPGA
pin. Pressing a key generates logic High on the associated FPGA pin. There is no active debouncing
circuitry on the key switches.

14
LEDS:

Test LEDs are provided for mapping output of FPGA or tracking particular stage in the design. A se-
ries current limiting resistor of 270Ω is associated with every LED. To light an individual LED, drive
the associated FPGA control signal High

15
PROGRAM:
Module test (sw, led);
Input [15:0] sw;
Output [15:0] led;
Assign led=sw;
End module

PROCEDURE:

Step 1:Start the Xilinx Project Navigator by using the desktop shortcut or by using the

Start Programs Xilinx ISE (9.1i).

Step 2: Create a new project and Select File menu and then select New project.

Step3: Specify the project name and location in pop up window and click NEXT.

Step4: Select Device. Select the required family, device, package, speed grade, Synthesis tool Simu-
lator from new project wizard pop up window. Click NEXT. Project summary will be displayed.

Step 5: Click FINISH to start Project.

Step6: To create new V file Right click on the device name and select NEW SOURCE

Step 7: Select VERILOG MODULE in NEW SOURCE WIZARD and give suitable name for the

Project. Click NEXT for the DEFINE MODULE Window Assign required ports in this Window.

Step 8: Write the Behavioural VERILOG Code in VERILOG Editor Sample code is given below for
this experiment.

Step 9: Check Syntax

Run the Check syntax  Process windowsynthesize check syntax , and remove errors if present

Step 10: Synthesize the design using XST.

Translate the design into gates and optimize it for the target architecture. This is the synthesis phase.
Again for synthesizing your design, from the source window selects synthe-
sis/Implementation from the drop-down menu. Highlight file in the Sources in Project window. To
run synthesis, right-click on Synthesize, and the Run option, or double-click on Synthesize in the Pro-
cesses for Current Source window. Synthesis will run, and

 a green check !will appear next to Synthesize when it is successfully completed.


 a red cross "indicates an error was generated and

16
 a yellow exclamation  mark indicates that a warning was generated. Check the synthesis re-
port. If there are any errors correct it and rerun the synthesis.
Step 11: After Synthesis, go to back annotate pin location in Implement Designand

double click to start back annotation. In back annotation the tool translates and routes the logic in

FPGA and generates the constraint file such that minimum delay paths are included. This helps to
make the design faster. Once back annotation is completed, constraint file is generated.

SYNTHESIS REPORT:
Reading design: leeeeeeed.prj
=======================================================================
* HDL Compilation *
=======================================================================
Compiling verilog file "leeeeeeed.v" in library work
Module <leeeeeeed> compiled
No errors in compilation
Analysis of file <"leeeeeeed.prj"> succeeded.
=======================================================================
* Design Hierarchy Analysis *
=======================================================================
Analyzing hierarchy for module <leeeeeeed> in library <work>.
=======================================================================
* HDL Analysis *
=======================================================================
Analyzing top module <leeeeeeed>.
Module <leeeeeeed> is correct for synthesis.
=======================================================================
* HDL Synthesis *
=======================================================================
Performing bidirectional port resolution...

Synthesizing Unit <leeeeeeed>.


Related source file is "leeeeeeed.v".
Unit <leeeeeeed> synthesized.
=======================================================================
HDL Synthesis Report
Found no macro
=======================================================================

17
=======================================================================
* Advanced HDL Synthesis *
=======================================================================
Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Xilinx92i.
=======================================================================
Advanced HDL Synthesis Report
Found no macro
=======================================================================
=======================================================================
* Low Level Synthesis *
=======================================================================
Optimizing unit <leeeeeeed> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block leeeeeeed, actual ratio is 0.
Final Macro Processing ...
=======================================================================
Final Register Report
Found no macro
=======================================================================
=======================================================================
* Partition Report *
=======================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=======================================================================
* Final Report *
=======================================================================
Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:


----------------------------------------
No asynchronous control signals found in this
Timing Summary:
---------------

18
Speed Grade: -4

Minimum period: No path found


Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 4.910ns

=======================================================================

Process "Synthesize" completed successfully


IMPLEMENT DESIGN PROCESS
NotUpToDate:generated file list is cmd
WARNING:ProjectMgmt - "C:/Xilinx92i/leeeeeeeed/leeeeeeed.ngr" line 0 duplicate design unit:
'Module|leeeeeeed'
ngdbuild -ise "C:/Xilinx92i/leeeeeeeed/leeeeeeeed.ise" -intstyle ise -dd _ngo -nt timestamp -uc
"led1.ucf" -p xc3s250e-pq208-4 "leeeeeeed.ngc" leeeeeeed.ngd is cmd

Command Line: C:\Xilinx92i\bin\nt\ngdbuild.exe -ise


C:/Xilinx92i/leeeeeeeed/leeeeeeeed.ise -intstyle ise -dd _ngo -nt timestamp -uc
led1.ucf -p xc3s250e-pq208-4 leeeeeeed.ngc leeeeeeed.ngd

Reading NGO file "C:/Xilinx92i/leeeeeeeed/leeeeeeed.ngc" ...

Applying constraints in "led1.ucf" to the design...

Checking timing specifications ...


Checking Partitions ...
Checking expanded design ...

Partition Implementation Status


-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "leeeeeeed.ngd" ...
Writing NGDBUILD log file "leeeeeeed.bld"...

NGDBUILD done.

Process "Translate" completed successfully


Using target part "3s250epq208-4".
Mapping design into LUTs...

19
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Logic Distribution:
Number of Slices containing only related logic: 0 out of 0 0%
Number of Slices containing unrelated logic: 0 out of 0 0%
*See NOTES below for an explanation of the effects of unrelated logic
Number of bonded IOBs: 32 out of 158 20%

Total equivalent gate count for design: 0


Additional JTAG gate count for IOBs: 1,536
Peak Memory Usage: 173 MB
Total REAL time to MAP completion: 4 secs
Total CPU time to MAP completion: 3 secs

NOTES:

Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.

Unrelated logic shares no connectivity. Map will only begin packing


unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.

Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.

Mapping completed.

20
See MAP report file "leeeeeeed_map.mrp" for details.

Process "Map" completed successfully


Constraints file: leeeeeeed.pcf.
Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Xilinx92i.
"leeeeeeed" is an NCD, version 3.1, device xc3s250e, package pq208, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing
constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically
improve the performance of all internal clocks in this design. The PAR timing summary will list the
performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For
best performance, set the effort level to "high". For balance between the fastest runtime and best per-
formance, set the effort level to "med".

Device speed data version: "PRODUCTION 1.26 2007-04-13".

Design Summary Report:

Number of External IOBs 32 out of 158 20%

Number of External Input IOBs 16

Number of External Input IBUFs 16


Number of LOCed External Input IBUFs 16 out of 16 100%

Number of External Output IOBs 16

Number of External Output IOBs 16


Number of LOCed External Output IOBs 16 out of 16 100%

Number of External Bidir IOBs 0

Overall effort level (-ol): Standard


Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard

Starting Placer
Phase 1.1
Phase 1.1 (Checksum:9896bf) REAL time: 3 secs
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 3 secs
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 3 secs
Phase 4.2
Phase 4.2 (Checksum:26259fc) REAL time: 4 secs
Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 4 secs

21
Phase 6.8
Phase 6.8 (Checksum:9950d3) REAL time: 4 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 4 secs
Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 4 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 4 secs

REAL time consumed by placer: 4 secs


CPU time consumed by placer: 3 secs
Writing design to file leeeeeeed.ncd

Total REAL time to Placer completion: 4 secs


Total CPU time to Placer completion: 3 secs
Starting Router

Phase 1: 16 unrouted; REAL time: 7 secs


Phase 2: 16 unrouted; REAL time: 7 secs
Phase 3: 2 unrouted; REAL time: 7 secs
Phase 4: 2 unrouted; (0) REAL time: 7 secs
Phase 5: 2 unrouted; (0) REAL time: 7 secs
Phase 6: 0 unrouted; (0) REAL time: 7 secs
Phase 7: 0 unrouted; (0) REAL time: 7 secs
Phase 8: 0 unrouted; (0) REAL time: 7 secs
Phase 9: 0 unrouted; (0) REAL time: 7 secs

Total REAL time to Router completion: 7 secs


Total CPU time to Router completion: 6 secs

Partition Implementation Status


-------------------------------
No Partitions were found in this design.
-------------------------------

Generating "PAR" statistics.

Timing Score: 0

Generating Pad Report.


All signals are completely routed.

Total REAL time to PAR completion: 8 secs


Total CPU time to PAR completion: 6 secs

Peak Memory Usage: 149 MB

Placement: Completed - No errors found.

22
Routing: Completed - No errors found.

Number of error messages: 0


Number of warning messages: 0
Number of info messages: 1

Writing design to file leeeeeeed.ncd

PAR done!

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".


Loading device for application Rf_Device from file '3s250e.nph' in environment
C:\Xilinx92i.
"leeeeeeed" is an NCD, version 3.1, device xc3s250e, package pq208, speed -4

Analysis completed Thu Oct 04 15:33:59 2018


--------------------------------------------------------------------------------
Generating Report ...

Number of warnings: 0
Total time: 3 secs

Process "Generate Post-Place & Route Static Timing" completed successfully

GENERATE PROGRAMMING FILE


Started : "Generate Programming File".

Process "Generate Programming File" completed successfully

23
PIN DESCRIPTION:

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

RESULT:
Thus the FPGA trainer kit was studied and onboard LEDs and switches were tested.

24
Ex no: 5

Date: TESTING THE TRAFFIC CONTROLLER

AIM:
To test the traffic light controller design on the FPGA board.

REQUIREMENTS:

S. NO Item Name Quantity

1. PC 01

2. Xilinx ISE 9.1i Software 01

3 RS232C Interfacing Cable 01

4. JTAG Inteface cable 01

5. Spartan III Trainer Kit 01

6. Power Adapter 01

7. Power Cable 01

THEORY:

Consider a controller for traffic at the intersection of four roads. Consider P1, P2, P3, P4 as four roads
and P5 as pedestrian. The road has following states.

• GREEN-11001
• YELLOW-01000
• RED-00100
the pedestrian
• GREEN-0000
• RED-1111

First the road p1 is green and all other roads p2, p3, p4 and P5 are red. After a some delay p1 is
turn to yellow and then red the traffic signal on p2 is green. After a delay p2 is turn to yellow and
then red the signal on p3 is green. Then p3 is changed to yellow and then red the signal on p4 is
changed to green. After a delay p4 is turn to yellow and then red the pedestrian light P5 is green after
a delay P5 is turn to green then routine will continue.

25
PROCEDURE:

Step 1:Start the Xilinx Project Navigator by using the desktop shortcut or by using the

Start Programs Xilinx ISE (9.1i).

Step 2: Create a new project and Select File menu and then select New project.

Step3: Specify the project name and location in pop up window and click NEXT.

Step4: Select Device. Select the required family, device, package, speed grade, Synthesis tool
Simulator from new project wizard pop up window. Click NEXT. Project summary will
be displayed.

Step 5: Click FINISH to start Project.

Step6: To create new V file Right click on the device name and select NEW SOURCE

Step 7: Select VERILOG MODULE in NEW SOURCE WIZARD and give suitable name for the
Project. Click NEXT for the DEFINE MODULE Window Assign required ports in this Win-
dow.

Step 8: Write the Behavioural VERILOG Code in VERILOG Editor Sample code is given below
for this experiment.

Step 9: Check Syntax

Run the Check syntax  Process windowsynthesize check syntax , and remove errors if pre-
sent

Step 10: Synthesize the design using XST.

Translate the design into gates and optimize it for the target architecture. This is the synthesis
phase. Again for synthesizing your design, from the source window selects synthe-
sis/Implementation from the drop-down menu. Highlight file in the Sources in Project window. To
run synthesis, right-click on Synthesize, and the Run option, or double-click on Synthesize in the Pro-
cesses for Current Source window. Synthesis will run, and

 a green check !will appear next to Synthesize when it is successfully completed.


 a red cross "indicates an error was generated and
 a yellow exclamation mark indicates that a warning was generated. Check the synthesis report.
If there are any errors correct it and rerun the synthesis.
Step 11: Write User Constraint file wherein the FPGA pins are locked as per the Spartan-III hard-

26
ware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and route
your design to fit into a Xilinx device (Spartan3 200k), and you can also get some post place-and-
route timing information about the design. This procedure runs you through the basic flow for imple-
mentation.

Step 12: Right-click on Implement Design, and choose the Run option, or double left-click on Im-
plement Design.Right-click on Generate Programming File, and choose the Run option, or double
left-click on Generate Programming File. This will generate the Bitstream. Double click on Con-
figure Device to download the bitstream.

STEP 12: The output can be observed on the output LEDs.

PROGRAM:
module tlc( clk,reset,p1,p2,p3,p4,p5);
input clk;
input reset;
output[4:0]p1;
output[4:0]p2;
output[4:0]p3;
output[4:0]p4;
output[4:0]p5;
reg [4:0]p1;
reg[4:0]p2;
reg[4:0]p3;
reg[4:0]p4;
reg[3:0]p5;
reg[5:0]Sig;
always@(posedgeclk)
begin
if(reset==1'b0)
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b1111;
Sig<=6'b000000;
end
else begin
Sig <= Sig+1;
case(Sig[5:0])
6'b000000:begin
p1<=5'b10011;//GREEN
p2<=5'b00100;

27
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b1111;
end
6'b000100:begin
p1<=5'b01000;//YELLOW
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b1111;
end
6’b001000:begin
P1<=5’b00100;
P2<=5’b10011;//GREEN
P3<=5’b00100;
P4<=5’b00100;
P5<=4’b1111;
end
6'b001100:begin
p1<=5'b00100;
p2<=5'b01000;//YELLOW
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b1111;
end
6'b01000:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b10011;//GREEN
p4<=5'b00100;
p5<=4'b1111;
end
6'b010100:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b01000;//YELLOW
p4<=5'b00100;
p5<=4'b1111;
end
6'b011000:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b10011;//GREEN
p5<=4'b1111;
end
6’b011100:begin
P1<=5’b00100;
P2<=5’b00100;
P3<=5’b00100;

28
P4<=5’b01000; //YELLOW
P5<=4’b1111;
end
6'b10000:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
p5<=4'b0000;//PEDESTRAIN
end
6'b100100:Sig<=6'b000000;
default:begin
end
endcase
end
end
endmodule

SYNTHESIS REPORT:
Reading design: tlc.prj

========================================================================

* HDL Compilation *

========================================================================

Compiling verilog file "tlc.v" in library work

Module <tlc> compiled

WARNING:HDLCompilers:258 - "tlc.v" line 33 Range on redeclaration of 'p5' overrides range on


output declaration at "tlc.v" line 28

No errors in compilation

Analysis of file <"tlc.prj"> succeeded.

========================================================================

* Design Hierarchy Analysis *

========================================================================

Analyzing hierarchy for module <tlc> in library <work>.

========================================================================

* HDL Analysis *

========================================================================

Analyzing top module <tlc>.

29
WARNING:Xst:883 - "tlc.v" line 77: Ignored duplicate item in case statement.

Module <tlc> is correct for synthesis.

========================================================================

* HDL Synthesis *

========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <tlc>.

Related source file is "tlc.v".

Found 6-bit register for signal <p1>.

Found 6-bit register for signal <p2>.

Found 6-bit register for signal <p3>.

Found 6-bit register for signal <p4>.

Found 4-bit register for signal <p5>.

Found 6-bit up counter for signal <sig>.

Summary:

inferred 1 Counter(s).

inferred 28 D-type flip-flop(s).

Unit <tlc> synthesized.

========================================================================

HDL Synthesis Report

Macro Statistics

# Counters :1

6-bit up counter :1

# Registers :5

4-bit register :1

6-bit register :4

========================================================================

========================================================================

* Advanced HDL Synthesis *

========================================================================

Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx92i.

30
========================================================================

Advanced HDL Synthesis Report

Macro Statistics

# Counters :1

6-bit up counter :1

# Registers : 21

Flip-Flops : 21

========================================================================

========================================================================

* Low Level Synthesis *

========================================================================

Optimizing unit <tlc> ...

Mapping all equations...

Building and optimizing final netlist ...

INFO:Xst:2261 - The FF/Latch <p5_0> in Unit <tlc> is equivalent to the following 3 FFs/Latches,
which will be removed : <p5_1> <p5_2> <p5_3>

Found area constraint ratio of 100 (+ 5) on block tlc, actual ratio is 1.

Final Macro Processing ...

========================================================================

Final Register Report

Macro Statistics

# Registers : 24

Flip-Flops : 24

========================================================================

========================================================================

* Partition Report *

========================================================================

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

31
========================================================================

* Final Report *

========================================================================

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk | BUFGP | 24 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -4

Minimum period: 4.755ns (Maximum Frequency: 210.305MHz)

Minimum input arrival time before clock: 4.762ns

Maximum output required time after clock: 4.450ns

Maximum combinational path delay: No path found

========================================================================

Process "Synthesize" completed successfully


IMPLEMENTATION PROCESS

Command Line: C:\Xilinx92i\bin\nt\ngdbuild.exe -ise

C:/Xilinx92i/traffic/traffic.ise -intstyle ise -dd _ngo -nt timestamp -uc t.ucf

-p xc3s100e-vq100-4 tlc.ngc tlc.ngd

Reading NGO file "C:/Xilinx92i/traffic/tlc.ngc" ...

32
Applying constraints in "t.ucf" to the design...

Checking timing specifications ...

Checking Partitions ...

Checking expanded design ...

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:

Number of errors: 0

Number of warnings: 0

Writing NGD file "tlc.ngd" ...

Writing NGDBUILD log file "tlc.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Using target part "3s100evq100-4".

Mapping design into LUTs...

Running directed packing...

Running delay-based LUT packing...

Running related packing...

Design Summary:

Number of errors: 0

Number of warnings: 1

Logic Utilization:

Number of Slice Flip Flops: 24 out of 1,920 1%

33
Number of 4 input LUTs: 33 out of 1,920 1%

Logic Distribution:

Number of occupied Slices: 18 out of 960 1%

Number of Slices containing only related logic: 18 out of 18 100%

Number of Slices containing unrelated logic: 0 out of 18 0%

*See NOTES below for an explanation of the effects of unrelated logic

Total Number of 4 input LUTs: 33 out of 1,920 1%

Number of bonded IOBs: 30 out of 66 45%

Number of GCLKs: 1 out of 24 4%

Total equivalent gate count for design: 393

Additional JTAG gate count for IOBs: 1,440

Peak Memory Usage: 169 MB

Total REAL time to MAP completion: 11 secs

Total CPU time to MAP completion: 3 secs

NOTES:

Related logic is defined as being logic that shares connectivity - e.g. two

LUTs are "related" if they share common inputs. When assembling slices,

Map gives priority to combine logic that is related. Doing so results in

the best timing performance.

Unrelated logic shares no connectivity. Map will only begin packing

unrelated logic into a slice once 99% of the slices are occupied through

related logic packing.

Note that once logic distribution reaches the 99% level through related

logic packing, this does not mean the device is completely utilized.

Unrelated logic packing will then begin, continuing until all usable LUTs

and FFs are occupied. Depending on your timing budget, increased levels of

unrelated logic packing may adversely affect the overall timing performance of your design.

34
Mapping completed.

See MAP report file "tlc_map.mrp" for details.

Process "Map" completed successfully

Constraints file: tlc.pcf.

Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx92i.

"tlc" is an NCD, version 3.1, device xc3s100e, package vq100, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing
constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically
improve the performance of all internal clocks in this design. The PAR timing summary will list the
performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For
best performance, set the effort level to "high". For a balance between the fastest runtime and best
performance, set the effort level to "med".

Device speed data version: "PRODUCTION 1.26 2007-04-13".

Design Summary Report:

Number of External IOBs 30 out of 66 45%

Number of External Input IOBs 2

Number of External Input IBUFs 2

Number of External Output IOBs 28

Number of External Output IOBs 28

Number of External Bidir IOBs 0

35
Number of BUFGMUXs 1 out of 24 4%

Number of Slices 18 out of 960 1%

Number of SLICEMs 0 out of 480 0%

Overall effort level (-ol): Standard

Placer effort level (-pl): High

Placer cost table entry (-t): 1

Router effort level (-rl): Standard

Starting Placer

Phase 1.1

Phase 1.1 (Checksum:989743) REAL time: 11 secs

Phase 2.7

Phase 2.7 (Checksum:1312cfe) REAL time: 11 secs

Phase 3.31

Phase 3.31 (Checksum:1c9c37d) REAL time: 11 secs

Phase 4.2

......

.Phase 4.2 (Checksum:26259fc) REAL time: 11 secs

Phase 5.30

Phase 5.30 (Checksum:2faf07b) REAL time: 11 secs

Phase 6.3

Phase 6.3 (Checksum:39386fa) REAL time: 11 secs

Phase 7.5

Phase 7.5 (Checksum:42c1d79) REAL time: 11 secs

Phase 8.8

36
.

Phase 8.8 (Checksum:9a7b3f) REAL time: 16 secs

Phase 9.5

Phase 9.5 (Checksum:55d4a77) REAL time: 16 secs

Phase 10.18

Phase 10.18 (Checksum:5f5e0f6) REAL time: 16 secs

Phase 11.5

Phase 11.5 (Checksum:68e7775) REAL time: 16 secs

REAL time consumed by placer: 16 secs

CPU time consumed by placer: 7 secs

Writing design to file tlc.ncd

Total REAL time to Placer completion: 17 secs

Total CPU time to Placer completion: 7 secs

Starting Router

Phase 1: 177 unrouted; REAL time: 19 secs

Phase 2: 159 unrouted; REAL time: 19 secs

Phase 3: 21 unrouted; REAL time: 19 secs

Phase 4: 21 unrouted; (11162) REAL time: 19 secs

Phase 5: 24 unrouted; (0) REAL time: 19 secs

Phase 6: 0 unrouted; (0) REAL time: 19 secs

Phase 7: 0 unrouted; (0) REAL time: 19 secs

Phase 8: 0 unrouted; (0) REAL time: 19 secs

Phase 9: 0 unrouted; (0) REAL time: 19 secs

Total REAL time to Router completion: 19 secs

Total CPU time to Router completion: 9 secs

Partition Implementation Status

-------------------------------

37
No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************

Generating Clock Report

**************************

+---------------------+--------------+------+------+------------+-------------+

| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

| clk_BUFGP | BUFGMUX_X2Y10| No | 17 | 0.010 | 0.065 |

+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------

Constraint | Check | Worst Case | Best Case | Timing | Timing

| | Slack | Achievable | Errors | Score

------------------------------------------------------------------------------------------------------

Autotimespec constraint for clock net clk | SETUP | N/A| 4.441ns| N/A| 0

_BUFGP | HOLD | 1.317ns| | 0| 0

------------------------------------------------------------------------------------------------------

All constraints were met.

38
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the

constraint does not cover any paths or that it has no requested value.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 21 secs

Total CPU time to PAR completion: 10 secs

Peak Memory Usage: 143 MB

Placement: Completed - No errors found.

Routing: Completed - No errors found.

Number of error messages: 0

Number of warning messages: 0

Number of info messages: 1

Writing design to file tlc.ncd

PAR done!

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s100e.nph' in environment

C:\Xilinx92i.

"tlc" is an NCD, version 3.1, device xc3s100e, package vq100, speed -4

Analysis completed Thu Oct 04 15:24:32 2018

--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0

Total time: 6 secs

Process "Generate Post-Place & Route Static Timing" completed successfully

39
GENERATE PROGRAMMING FILE
Started : "Generate Programming File".

Process "Generate Programming File" completed successfully

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

RESULT:
Thus the traffic light controller program was successfully tested on the FPGA kit.

40
Ex no: 6
Date: DESIGN A REAL TIME CLOCK AND DEMONSTRATE

IT’S WORKING ON THE FPGA BOARD

AIM:
To design a real time clock and demonstrate its working on the FPGA Board
REQUIREMENTS:

S. NO Item Name Quantity

1. PC 01

2. Xilinx ISE 9.1i Software 01

3 RS232C Interfacing Cable 01

4. JTAG Interface cable 01

5. Spartan III Trainer Kit 01

6. Power Adapter 01

7. Power Cable 01

THEORY:

Description for Real Clock Timer:

Real Clock timer consists of six character multiplexed display working on system clock of 4 MHz.
Out of six displays first two (DIS -6 and DIS- 5) are used to display hours, next two (DIS-4 and DIS-
3) are used to display minutes and last two (DIS -2 and DIS-1) are used to display seconds status.
Real time status is displayed on these seven segments by writing a HDL functionality of 6 counters
cascaded with each other and decoding its output to seven segment equivalents.
HDL functionality also offers a provision for loading the real clock timer with a new value using load
signal, when high real clock timer is loaded with new value.

41
PROCEDURE:

Step 1:Start the Xilinx Project Navigator by using the desktop shortcut or by using the

Start Programs Xilinx ISE (9.1i).

Step 2: Create a new project and Select File menu and then select New project.

Step3: Specify the project name and location in pop up window and click NEXT.

Step4: Select Device. Select the required family, device, package, speed grade, Synthesis tool Simula-
tor from new project wizard pop up window. Click NEXT. Project summary will be displayed.

Step 5: Click FINISH to start Project.

Step6: To create new V file Right click on the device name and select NEW SOURCE

Step 7: Select VERILOG MODULE in NEW SOURCE WIZARD and give suitable name for thePro-
ject. Click NEXT for the DEFINE MODULE Window Assign required ports in this Window.

Step 8: Write the Behavioural VERILOG Code in VERILOG Editor Sample code is given below for
this experiment.

Step 9: Check Syntax

Run the Check syntax  Process windowsynthesize check syntax , and remove errors if
present

Translate the design into gates and optimize it for the target architecture. This is the

synthesis phase. Again for synthesizing your design, from the source window

selects synthesis/Implementation from the drop-down menu. Highlight file in the Sources in

 Project window. To run synthesis, right-click on Synthesize, and the Run option, or double-
click on Synthesize in the Processes for Current Source window. Synthesis will run, and a
green check !will appear next to Synthesize when it is successfully completed.
 a red cross "indicates an error was generated and
 a yellow exclamation  mark indicates that a warning was generated. Check the synthesis re-
port. If there are any errors correct it and rerun the synthesis.
Step 11: Write User Constraint file wherein the FPGA pins are locked as per the Spartan-II hard-
ware. Running the Xilinx Implementation Tools. Once synthesis is complete, you can place and

42
route your design to fit into a Xilinx device (Spartan3 200k), and you can also get some post place-
and-route timing information about the design. This procedure runs you through the basic flow for
implementation.

Step 12: Right-click on Implement Design, and choose the Run option, or double left-click on
Implement Design.Right-click on Generate Programming File, and choose the Run option, or
double left-click on Generate Programming File. This will generate the Bitstream. Double click
on Configure Device to download the bitstream.

STEP 13: The output can be observed on the output LEDs.

PROGRAM:

module finalclock_verilog (sgout,dis,hr2,hr1,min2,min1,sec1, sec2,load,tc1,tc2,tc3,tc4,tc5,tc6,enable,

reset,clock);

output [3:0]sec1,sec2,min1,min2,hr1,hr2;

output [7:0] sgout;

output [5:0] dis;

output tc1,tc2,tc3,tc4,tc5,tc6,enable;

input reset,clock,load;

reg [3:0]sec1_rg,sec2_rg,min1_rg,min2_rg,hr1_rg,hr2_rg;

reg [21:0] pulsegen ;

reg [2:0]cnk2;

reg [3:0]mout;

reg [7:0]sgout_rg;

reg [5:0]dis_sig;

//reg tc,tc1,tc2,tc3,tc4,tc5,tc6,enable;

//reg sec1_rg(3:0),sec2_rg(3:0),min1_rg(3:0),min2_rg(3:0),hr1_rg(3:0);

//reg hr2_rg(3:0),pulsegen(21:0),sel(2:0);

//regmout(3:0),sgout(7:0),ck1(22:0),cnk2(2:0);

//*************************** Pulse Generator ******************

always@(posedge clock or posedge reset)

begin

if (reset)

43
pulsegen<= 22'b0;

else

begin

if (pulsegen == 22'b1111010000100100000000)

pulsegen<= 22'b0;

else

pulsegen<= pulsegen + 1;

end

end

//Enable signal to generate 1-sec pulse for sec1 counter

else

sec1_rg <= sec1_rg + 1;

end

end

end

assign sec1 = sec1_rg;

//------------------tc1 signal to start sec2 counter---------------------------

assign tc1 = (sec1_rg == 4'b1001) && (enable == 1);

//--************************* Second_cntr2 ***********************

always@(posedge clock or posedge reset)

begin

assign enable = (pulsegen == 22'b1111010000100100000000) ;

//enable signal for sec1 counter

//************************ Second_cntr1 *************************

always@(posedge clock or posedge reset)

begin

if (reset )

sec1_rg <= 4'b0000;

else if (load) begin

sec1_rg <= 4'b0100;

end

44
else

begin

if (enable)

begin

if (sec1_rg == 4'b1001)

sec1_rg <= 4'b0000;

if (reset )

sec2_rg <= 4'b0000;

else if (load) begin

sec2_rg <= 4'b0100;

end

else

begin

if (tc1)

begin

if (sec2_rg == 4'b0101) begin

sec2_rg <= 4'b0000;

end

else begin

sec2_rg <= sec2_rg + 1;

end

end

end

end

assign sec2 = sec2_rg;

//-------------------------tc2 signal to start min1 counter-------------------

assign tc2 = (sec2_rg == 4'b0101) && (tc1 == 1);

//--************************ Minute_cntr1 *************************

always@(posedge clock or posedge reset)

begin

45
if (reset )

min1_rg <= 4'b0000;

else if (load) begin

min1_rg <= 4'b0100;

end

else

begin

if (tc2)

begin

if (min1_rg == 4'b1001) begin

min1_rg <= 4'b0000;

end

else begin

min1_rg <= min1_rg + 1;

end

end

end

end

assign min1 = min1_rg;

//------------------------tc3 signal to start min2 counter--------------------

assign tc3 = (min1_rg == 4'b1001) && (tc2 == 1);

//--************************ Hour_cntr1 *************************

always@(posedge clock or posedge reset)

begin

if (reset)

min2_rg <= 4'b0000;

else if (load) begin

min2_rg <= 4'b0100;

end

46
else

begin

if (tc3)

begin

if (min2_rg == 4'b0101) begin

min2_rg <= 4'b0000;

end

else

begin

min2_rg <= min2_rg + 1;

end

end

end

end

assign min2 = min2_rg;

//---------------------tc4 signal to start hr1 counter--------------------------

assign tc4 = (min2_rg == 4'b0101) && (tc3 == 1);

//--************************ Hour_cntr1 *************************

always@(posedge clock or posedge reset)

begin

if (reset)

hr1_rg <= 4'b0000;

else if (load) begin

hr1_rg <= 4'b0001;

end

else

begin

if (tc6)

begin

hr1_rg <= 4'b0000;

47
end

else

begin

if (tc4)

begin

if (hr1_rg == 4'b1001) begin

hr1_rg <= 4'b0000;

end

else

begin

hr1_rg <= hr1_rg + 1;

end

end

end

end

end

assign hr1 = hr1_rg;

//---------------------tc5 signal to start hr2 counter--------------------------

assign tc5 = (hr1_rg == 4'b1001) && (tc4 == 1);

//------------------------tc6 signal to reset at 23:59:59--------------------------

assign tc6 = (hr2_rg == 4'b0010) && (hr1_rg == 4'b0011) && (tc4 == 1);

//--************************ Hour_cntr2 *************************

always@(posedge clock or posedge reset)

begin

if (reset)

hr2_rg <= 4'b0000;

else if (load) begin

hr2_rg <= 4'b0000;

end

48
else

begin

if (tc6)

begin

hr2_rg <= 4'b0000;

end

else

begin

if (tc5)

begin

if (hr2_rg == 4'b0010) begin

hr2_rg <= 4'b0000;

end

else

begin

hr2_rg <= hr2_rg + 1;

end

end

end

end

end

assign hr2 = hr2_rg;

always@(posedgepulsegen[9] or posedge reset)

begin

if (reset)

cnk2 <= 3'b0;

else

begin

if (cnk2 == 3'b101)

cnk2 <= 3'b0 ;

else

49
cnk2 <= cnk2 + 1;

end

end

always@(cnk2)

case (cnk2)

3'b000 :mout<= sec1;

3'b001 :mout<= sec2;

3'b010 :mout<= min1;

3'b011 :mout<= min2;

3'b100 :mout<= hr1;

3'b101 :mout<= hr2;

endcase

always@(mout)

case (mout)

4'b0000 :sgout_rg<= 8'b11000000;

4'b0001 :sgout_rg<= 8'b11111001;

4'b0010 :sgout_rg<= 8'b10100100;

4'b0011 :sgout_rg<= 8'b10110000;

4'b0100 :sgout_rg<= 8'b10011001;

4'b0101 :sgout_rg<= 8'b10010010;

4'b0110 :sgout_rg<= 8'b10000010;

4'b0111 :sgout_rg<= 8'b11111000;

4'b1000 :sgout_rg<= 8'b10000000;

4'b1001 :sgout_rg<= 8'b10011000;

endcase

always@(cnk2)

case (cnk2)

3'b000 :dis_sig<= 6'b111110;

3'b001 :dis_sig<= 6'b111101;

3'b010 :dis_sig<= 6'b111011;

3'b011 :dis_sig<= 6'b110111;

50
3'b100 :dis_sig<= 6'b101111;

3'b101 :dis_sig<= 6'b011111;

endcase

assignsgout = sgout_rg;

assign dis = dis_sig;

endmodule

PIN DESCRIPTION:

I / O DIRECTION I/O NAME LOCATION

INPUT CLK “P184”

INPUT LOAD “P180”

INPUT RESET “P182”

OUTPUT DIS<0> “P97”

OUTPUT DIS<1> “P100”

OUTPUT DIS<2> “P101”

OUTPUT DIS<3> “P102”

OUTPUT DIS<4> “P132”

OUTPUT DIS<5> “P133”

OUTPUT SEG A “P144”

OUTPUT SEG B “P143”

OUTPUT SEG C “P141”

OUTPUT SEG D “P140”

OUTPUT SEG E “P139”

51
OUTPUT SEG F “P138”

OUTPUT SEG G “P137”

OUTPUT SEGDP “P135”

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

RESULT:

Thus the real time clock was designed and implemented on the FPGA Kit.

52
NETWORKS

LABORATORY

53
LIST OF EXPERIMENTS (NETWORKS)

EXP. PAGE STAFF


DATE EXPERIMENT NAME MARKS
NO. NO. INITIAL

1.(A) Ethernet LAN protocol 55

1.(B) Token Bus protocol 59

1.(C) Token Ring protocol 63

67
2. Wireless LAN protocols

Implementation and study of Stop 71


3.
and Wait protocol

Implementation and study of Go 75


4.(A)
back-N protocols

Implementation and study of Selec- 78


4.(B)
tive repeat protocols

Implementation of distance vector 81


5.
routing algorithm

83

6. Implementation of Link state routing


algorithm

Implementation of Data encryption 85


7.
and decryption

54
Ex.no:1 (A) Ethernet LAN protocol

Date:

Aim: Implement the CSMA protocol for packet communication between a numbers of nodes
connected to a common bus.

Requirements:

a. Computer with Benchmark Lan-T software


b. Hardware emulator kit

Theory:
Each station first listen to the medium (or check the state of the medium) before sending. In
other words, CSMA is based on the principle “Sense before transmit” or “Listen before talk”. CSMA
can reduce the possibility of collision, but it cannot eliminate it.

Procedure:
1. Click on the “MAC Experiment” icon twice from the desktop on both PC’s.

2. Click the Configuration button in the window in both the PC’s.

Setting the configuration menu:

PC 1 PC 2
a. Node Id = ‘0’ on config menu 1 and ‘1’ on a. Node Id = ‘0’ on config menu 1 and ‘1’

config menu 2 on config menu 2

b. Protocol = ALOHA b. Protocol = ALOHA

c. Baud rate = 8 kbps(at both config menu c. Baud rate = 8 kbps(at both config menu

and NEU) and NEU)

d. Duration = 100 s d. Duration = 100 s

e. Packet length = 100 bytes e. Packet length = 100 bytes

f. IPD = 40 ms f. IPD = 40 ms

g. Bit delay = 0(at NEU) g. Bit delay = 0(at NEU)

h. Direction = Sender h. Direction = Sender

Note: All the nodes have to be configured as ‘Senders’

55
3. Select the “OK” button and Download the driver to the NIU using the BOOT button command.
Booting from any one of the applications is enough.

4. Run the experiment by clicking button or RUN – Start from each application.

5. View the statistics window for results. Only Tx packets and collision count are taken into account
for MAC calculation.

6. Save or note down the readings once the experiment is completed.

7. Repeat the above steps from 1 to 6 for a range of ‘G’ values.

8. Plot graph between Offered load and Throughput.

9. Compare graphs of different packet length, node and data rate.

Calculation of Practical Throughput (X) from the obtained readings:

Successfully transmitted packet by a node = Transmitted Packets - Collision Count

(Sum of Successfully Transmitted packets in all 4 nodes*Packet Length*8)

X= -----------------------------------------------------------------------------------------

(Duration of Experiment * data rate)

Calculation of Practical Offered load (G):

(Sum of Transmitted packets in all 4 nodes * Packet Length * 8)

G= ----------------------------------------------------------------------------

(Duration of Experiment * data rate)

56
Tabulation:

IPD Tx1 Tx2 Tx3 Tx4 G – Prac- X – Practical


tical
Throughput
Offered
Load

Graph:

57
CONTENTS MAXIMUM MARKS
MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

Result:
Thus the ALOHA protocol for packet communication in ETHERNET LAN was implemented.

58
Ex.no:1 (B) Token Bus Protocol

Date:

Aim:
To implement the token passing access in BUS-LAN

Requirements:
(i) Computer with Benchmark Lan-T software.
(ii) Hardware emulator kit.

Theory:
Token bus was a 4Mbps local area networking technology created by IBM to connect their terminals
to mainframes. Token bus utilized a copper coaxial cable to connect multiple. The coaxial cable saved
as a common communication bus and a token was created by token bus protocol to manage or arbi-
trate access to the bus.

Any station that has token packet has permission to transmit data. The station releases token when it is
done communication or when a higher priority device needs to transmit. Token bus suffered two ma-
jor limitations-any failure in bus caused all the devices beyond failure to be able to communicate with
rest of the network. Secondly adding more stations to bus was difficult. Token bus was thus seen as
unreliable and difficult to expand and upgrade.

Procedure:
1. Click on the ‘Token Bus icon twice from the desktop.
2. Click the Configuration button in the window in both the PC’s.

Setting the configuration menu:


PC1 PC2

Node ID:0 as config menu’1’,1 as config Node ID:0 as config menu’1’,1 as config
menu’2’ menu’2’

Protocol: ALOHA Protocol: ALOHA

Baud Rate: 8Kbps Baud Rate: 8Kbps

Duration:100 Duration:100

Packet Length:1000 bytes Packet Length:1000 bytes

My Address: 0 as config menu’1’,1 as config My Address: 2 as config menu’1’,3 as config


menu ‘2’ menu ‘2’

Direction: sender Direction: sender

59
Note 1: If you connect two PC’s and configured four nodes then set the “My Address” as 0 to 3 in all
four nodes, if you connect three PCs and configured six nodes then set the My Address’ as 0 to 5 in
all six nodes.
Note 2: Start running the experiment from the lowest priority node (i.e., from ‘My Address’ 3 in case
of four nodes and 5 in the case of six nodes)
Note 3: No. of Nodes has to be set as 4 when two PCs are connected and 6 when three PCs are con-
nected.
3. Download the driver to the NIU using the BOOT button command for both PCs.
4. Run the experiment by clicking the RUN-Start from each application. Run the all the experiments
at the same time.
Note: While you do this THT window pops up, enter the THT time in all nodes and press the OK but-
ton first in the node, which has highest value of ‘My Address’.
5. Set the Token Holding Time (THT) (say1000 ms).
6. View the statistics window for results.
7. Save or note down the reading when the experiment says that it has stopped after the specified du-
ration.
8. Repeat from the above steps from “a” to “h” and take the readings by changing the Inter Packet
Delay (IPD).
9. Plot the Offered Load G Vs Throughput X, Plot Throughput Vs Average Delay.
10. Repeat the Experiment for various THT and plot the graph

Calculation of Practical Throughput (X) from the obtained readings:


(Sum of Successfully Transmitted packet in all the nodes * Packet Length * 8)

X = -----------------------------------------------------------------------------

(Duration of Experiment * Data rate)

Calculation of the Offered load:

N*P

G = ------

C * ta

G – Offered load

N – Number of nodes

P – Packet length in bits

C – Data rate in bits/sec

ta – Inter packet delay in millisecs.

60
Tabulation:

IPD Tx1 Tx2 Tx3 Tx4 G – Practi- X – Practical


cal
Throughput
Offered
Load

Graph:

61
CONTENTS MAXIMUM MARKS
MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

Result:
Thus the Token passing access in TOKEN-BUS LAN was implemented.

62
Ex. no: 1 (C) Token Ring Protocol

Date:

Aim:
To implement the token passing access in RING-LAN

Required:
(i) Computer with Benchmark LanT software
(ii) Hardware emulator kit.
Theory:
Token ring was created by IBM to improve upon the previous bus technology. Token ring
uses a ring-based technology and passes a token around the network to control access to network wir-
ing. The token ring protocol also provides features for allowing delay sensitive traffic to share net-
work with other data that is key to mainframe operations.

Procedure:
1. Click on the ‘Token-Bus icon twice from the desktop.
2. Click the Configuration button in the window in both the PC’s.
Setting the configuration menu:

PC1 PC2

Node ID:0 as config menu’1’,1 as config Node ID:0 as config menu’1’,1 as config
menu’2’ menu’2’

Protocol: Ring Protocol: Ring

Baud Rate: 8Kbps Baud Rate: 8Kbps

Duration:100 Duration:100

Packet Length:1000 bytes Packet Length:1000 bytes

My Address: 0 as config menu’1’,1 as config My Address: 2 as config menu’1’,3 as config


menu ‘2’ menu ‘2’

Direction: sender Direction: sender

Note 1: If you connect two PC’s and configured four nodes then set the “My Address” as 0 to 3 in all
four nodes, if you connect three PCs and configured six nodes then set the My Address’ as 0 to 5 in
all six nodes.

63
Note 2: Start running the experiment from the lowest priority node (i.e., from ‘My Address’ 3 in case
of four nodes and 5 in the case of six nodes)
Note 3: No. of Nodes has to be set as 4 when two PCs are connected and 6 when three PCs are con-
nected.
3. Download the driver to the NIU using the BOOT button command for both PCs.
4. Run the experiment by clicking the RUN-Start from each application. Run the all the experiments
at the same time.
Note: While you do this THT window pops up, enter the THT time in all nodes and press the OK but-
ton first in the node, which has highest value of ‘My Address’.
5. Set the Token Holding Time (THT) (say1000 ms).
6. View the statistics window for results.
7. Save or note down the reading when the experiment says that it has stopped after the specified du-
ration.
8. Repeat from the above steps from “a” to “h” and take the readings by changing the Inter Packet
Delay (IPD).
9. Plot the Offered Load G Vs Throughput X, Plot Throughput Vs Average Delay.
10. Repeat the Experiment for various THT and plot the graph

Calculation of Practical Throughput (X) from the obtained readings:

(Sum of Successfully Transmitted packet in all the nodes * Packet Length * 8)

X = -----------------------------------------------------------------------------

(Duration of Experiment * Data rate)

Calculation of the Offered load:

N*P
G = ------
C * ta

G – Offered load

N – Number of nodes

P – Packet length in bits

C – Data rate in bits/sec

ta – Inter packet delay in millisecs.

64
Tabulation:

IPD Tx1 Tx2 Tx3 Tx4 G – Prac- X – Practical Avg Delay


tical
Throughput
Offered
Load

Graph:

65
CONTENTS MAXIMUM MARKS
MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

Result:
Thus the Token passing acess in RING-LAN was implemented.

66
Ex.no:2 Wireless LAN Protocols

Date:

Aim:
Implement the CSMA/CA protocol for packet communication between a numbers of nodes
connected to a common bus.

Required:
(i) Computer with Benchmark Lan-T software
(ii) Hardware emulator kit.

Theory:
The approach called CSMA/CA is adopted by the IEEE 802.11 wireless LAN standard. In
CSMA/CA, if the station finds the channel busy, it does not restart the timer of the contention win-
dow; it stops the timer and restarts it when the channel becomes idle. When an idle channel is found,
the station does not send immediately. It waits for a period of time the inter frame space or IFS. If af-
ter the IFS time the channel is still idle, the station can send, but it still needs to wait a time equal to
the contention time.

Procedure:

Steps to configure Receiver:


1. Click on the “CSMA CA” icon from the desktop on one PC.
2. Click the Configuration button.
Setting the configuration menu for Access point:
PC 1
a. Node id: “0” on config menu

b. Protocol = set all to “ALOHA”

c. Baud Rate = 8Kbps (At both the config menu )

d. Duration = 100sec

e. Packet Length = 100

f. Bit Delay = 0(at NEU)

g. Direction = Receiver

h. Set the topology to BUS in NEU

i. My address= “1”

j. Number of nodes = “5”

67
Steps to configure Client nodes:
PC 2 PC 2

a. Node id: “0” on config menu a. Node id: “1” on config menu

b. Protocol = set all to “ALOHA” b. Protocol = set all to “ALOHA”

c. Baud Rate = 8Kbps (At both the c. Baud Rate = 8Kbps (At both the

config menu and NEU) config menu and NEU)

d. Duration = 30sec d. Duration = 30sec

e. Packet Length = 100 e. Packet Length = 100

f. Bit Delay = 0(at NEU) f. Bit Delay = 0(at NEU)

g. Direction = sender g. Direction =sender

h. Set the topology to BUS in NEU h. Set the topology to BUS in NEU

3. Click on the “CSMA CA” icon from the desktop on the second PC.

4. Click the Configuration button in the window in the second PC.

5. Select the “OK” button and Download the driver to the NIU using the BOOT button command.
Booting from any one of the applications is enough.

6. Click the RUN button first in access point side.

7. Follow the same procedures in the client side also. Once when you press the run button the follow-
ing window will appear.

8. Set the Back-off time as 40 ms

9. Set the Carrier Back-off time as 40 ms

10. Set the Control Signal Handshake equal to Packet length (for this case it is 100 as the packet
length is 100 bytes).

11. Set the Data Signal Handshake equal to twice the Packet length(for this case it is 200 as the packet
length is 100 bytes).

 After 30 sec both the nodes stops transmitting and the following screen appears:
 After 100 sec both the nodes stops transmitting and the following screen appears:
 Once the Sender stops, press the OK button in the receiver Node and Press the stop button.
12. Repeat the above steps for various values of ta.

68
13. Calculate the Practical offered load from the below given formula and plot the graph between the
practical Offered load and Throughput.

14. Repeat the experiment for various values of Packet length, Node, Data rate

Calculation of Throughput for CSMA/CD:


(Sum of ACK counts in all sender nodes * Packet Length * 8)

X = ---------------------------------------------------------------------------

(Duration of Experiment * 8kbps)

Calculation of Offered Load for CSMA/CD:

(No of G count in all sender nodes * Packet Length * 8)

G= ----------------------------------------------------------------------

(Duration of Experiment * Data rate)

Tabulation:

Receiver Sender G – Practical X – Practical

IPD Offered Load Throughput


RX TX1 TX2

69
GRAPH:

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

Result:
Thus the WIRELESS LAN protocol was implemented by using ALOHA.

70
Ex. no: 3 Implementation and study of Stop and Wait Protocol

Date:

Aim:
Provide reliable data transfer between two nodes over an unreliable network using the stop
and wait protocol.

Required:
(i) Computer with benchmark LanT software
(ii) Hardware emulator kit.

Theory:
In a stop and wait method of flow control, the sender waits for an acknowledgement after every frame
it sends. Only when an acknowledgement has been received, the next frame is sent. This process of
alternately sending and waiting repeats until the sender transmits on end of transmission frame. The
advantage is simplicity and the disadvantage is its inefficiency.

Stop and wait ARQ is a form of stop and wait flow control extended to include retransmission of data
in case of damaged frames. For retransmission to work, four features are added to the basic flow con-
trol mechanism.

The sending device keeps a copy of the last frame transmitted until it receives an acknowledgement
for that frame. Keeping a copy allows the sender to retransmit lost or damaged frames until they are
received correctly.

For identification purposes with data frames and ACK frames are numbered alternately 0 and
1. An ACK 1 frame, indicating that the receiver has gotten data 0 and is now expecting data
1, acknowledges a data 0 frame. This numbering allows for identification allows for identifi-
cation of data frames in case of duplicate transmission.
If an error is discovered in a data frame, indicating that it has been corrupted in transit, a NAK frame
is returned. NAK frames, which are not numbered, tell the sender to retransmit the last frame sent.
Stop and wait ARQ requires that the sender waits till it receives an acknowledgement for the frame,
last sent by it, before it transmits the next one. When the sender receives a NAK, it retransmits the
frame sent after the previous ACK, irrespective of the number. The sending device is equipped with a
timer.

Procedure:
1. Click on the ‘Stop & Wait’ icon from the desktop on both PCs.
2. Click the Configuration button in the window in both the Pc’s.

3.Download the driver to the NIU using the BOOT button command for both PCs.

4. Run the experiment by clicking the RUN-Start from each application. Run the receiver node first
& then the Sender node. While you run the Sender node it will ask for timeout value.

71
5. Set the Timeout Value to 1500

Setting the configuration menu:

PC 1 PC 2
a. Node Id = ‘0’ on config menu 1 and ‘1’ on a. Node Id = ‘0’ on config menu 1 and ‘1’

config menu 2 on config menu 2

b. Protocol = CSMA/CD b. Protocol = CSMA/CD

c. Baud rate = 8 kbps(at both config menu c. Baud rate = 8 kbps(at both config menu

and NEU) and NEU)

d. Duration = 100 s d. Duration = 100 s

e. Packet length = 1000 bytes e. Packet length = 1000bytes

f. IPD = 40 ms f. IPD = 40 ms

g. Bit delay = 0(at NEU) g. Bit delay = 0(at NEU)

h. Direction = Sender h. Direction = Receiver

6. Note down the no of successfully Transmitted Packets & Retransmission Count.

7. Repeat the above steps for various time out values and draw a graph between timeout Value &
throughput.

8. Explain why the throughput is less compared to CSMA/CD protocol.

Calculation of Practical Throughput (X) from the obtained readings:

(Sum of Successfully Transmitted packets in all 4 nodes*Packet Length*8)

X= -----------------------------------------------------------------------------------------

(Duration of Experiment * data rate)

72
Tabulation:
Timeout (T) (ms) Successfully Txd Practical Throughput

Graph:

73
CONTENTS MAXIMUM MARKS
MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

Result:
Thus the STOP and WAIT protocol was successfully implemented.

74
Ex.no:4 (A). Implementation and Study of GOBACK-N Protocol

Date:

Aim:
Provide reliable data transfer between two nodes over an unreliable network using the
Sliding window go back N protocol

Required:
(i) Computer with benchmark Lan-T software
(ii) Hardware emulator kit.

Theory:
In this sliding window Go-Back_N ARQ method, if one frame is lost or damaged, all frames sent
since the last frame acknowledge are retransmitted.
Damaged Frame: When the frames 0, 1, 2 and 3 have been transmitted but the first acknowledge-
ment received is a NAK 3, there are 2 meanings for the NAK. First, a positive acknowledgement of
all frames received prior to the damaged frame and second, a negative acknowledgement of the frame
indicated. If the first acknowledgement of the indicated is a NAK 3, it means that data frames 0, 1 and
2 were all received in good shape. Only frame 3 must be resent. If frames 0 through 4 have been
transmitted before a NAK is received, the receiver discovers and error, it stops accepting subsequent
frames until the damaged frame has been replaces correctly.
Lost data frame: Sliding window protocols require that the data frame be transmitted sequentially. If
one or more frames are noise corrupted that they are lost in transit, the next frame that arrives at the
receiver will be out of sequence. The receiver that one or more have skipped and returns a NAK for
the first missing frames. A NAK frame does not indicate whether the frame has been lost or damaged,
first that it means to be resent. The sending device then retransmits the frame indicated by the NAK,
as well as any frame that it had transmitted after the last one.

Procedure:
1. Click on the ‘Sliding win go back n’ icon from the desktop on both PCs.
2. Click the Configuration button in the window in both the Pc’s.
Setting the configuration
menu:

3. Set the “Inter Packet Delay” to 400msecs


4. Download the driver to the NIU using the BOOT button command for both PCs.
5. Run the experiment by clicking the RUN-Start from each application. Run the receiver node first &
then the sender node. While you run the Sender node it will ask for timeout value.

75
6. Set the Timeout Value to 1500
7. Note down the no of successfully Transmitted Packets & Retransmission Count.
8. Repeat the above steps for various time out values and draw a graph between timeout Value &
Throughput. Find the optimum timeout value from the plot

Calculation of Practical Throughput (X) from the obtained readings:

(Sum of Successfully Transmitted packets in all 4 nodes*Packet Length*8)

X= -----------------------------------------------------------------------------------------

(Duration of Experiment * data rate)

Tabulation:

Timeout (T) (ms) Successfully Transmitted Practical Throughput

76
Graph:

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100
Result:
Thus the GO BACK-N protocol was successfully implemented.

77
Ex. no 4(B). Implementation and Study of Selective Repeat Protocol

Date:

Aim:
Provide reliable data transfer between two nodes over an unreliable network using the sliding
window selective repeat protocol.

Required:
(i) Computer with benchmark Lan-T software
(ii) Hardware emulator kit.
Procedure:
1. Click on the Selective Repeat icon from the desktop on both PCs.

2. Click the Configuration button in the window in both the Pc’s.

Setting the configuration menu:

PC1 PC2

Node id 0 Node id 0

Protocol CSMA/CD Protocol CSMA/CD

Baud Rate 8Kbps (At both Baud Rate 8Kbps (At both
the the

config menu and config menu


and
NEU)
NEU)
Duration 100s
Duration 100s
Packet Length 1000 bytes
Packet Length 1000 bytes
Bit Delay 0(at NEU)
Bit Delay 0(at NEU)
Direction Sender
Direction Receiver
No of packets 4
No of packets 4

78
3. Set the Inter Packet Delay to 400msecs

4. Click OK button and Download the driver to the NIU using the BOOT button command. Booting
from any one of the applications is enough.

5. Run the experiment by clicking button or by choosing RUN _ Start from each application.

6. Set the Timeout Value to 1000 ms

7. Note down the no of successfully Transmitted Packets.

8. Repeat the above steps for various time out values and plot a graph between timeout Value
&Throughput. Find the optimum timeout value from the plot.

Calculation of Practical Throughput:


(Sum of Successfully Tx packets * Packet Length * 8)

X = ----------------------------------------------------------------------

(Duration of Experiment * Data rate)

Tabulation:

Time out Successfully Tx Practical

value in ms Packets Throughput

79
Graph:

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

Result:
Thus the SELECTIVE REPEAT protocol was successfully implemented.

80
Ex .no:5 Implementation of Distance Vector Algorithm

Date:

Aim:
To simulate the distance vector routing protocol to maintain routing tables as the traffic and topology
of the network changes.

Procedure:
1. Double click on Lan-T Routing Simulator icon from the desktop.

2. Click load button and browse open C:\Lantrain\Config\ linear.txt.

3. Click button and configure button and select Distance vector algorithm

4. The icon in the screen represents the nodes and the green color line represents the path. The values
inside the braces represents the ‘Forward and Reverse’ weights.

5. Click on the node icon to obtain the routing table.

6. The above picture shows the nodes and its routing table.

7. Observe the routing table showing No route to some of the destinations even though there is a phys-
ical connection. This is because the routing table of the corresponding nodes is not been updated since
there is no hopping. To update the routing table click button.

8. Hopping happens by clicking button

9. Now after several hopping the routing table gets updated. As the number nodes increases, the num-
ber of hopping increases. This is one of the disadvantages of distance vector algorithm.

Count to Infinity problem


10. Click the green color line lying between N3 and N4.
11. Enter the forward and reverse weight as ‘-1’ in order to disconnect N4 from the other nodes
12. Now observe the routing table.
13. Now you could observe that there are no changes in the routing table, as they are not updated.
Click single step button to update the routing table.
14. Even after several hopping the routing tables of N0, N1, N2, N3 shows the path and weight to N4.
These false updates are another disadvantage in the ‘Distance vector algorithm’.

81
CONTENTS MAXIMUM MARKS
MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

Result:
Thus the DISTANCE VECTOR ALGORITHM was successfully implemented.

82
Ex .no:6 Implementation of Link State Routing Algorithm

Date:

Aim:
To simulate the link state routing protocol to maintain routing tables as the traffic and topology of the
network changes.

Procedure:
1. Double click on Lan-T Routing Simulator icon from the desktop.

2. Click load button and browse open C:\Lantrain\Config\linear.txt.

3. Click configure button and select Link state algorithm.

4. Click on the nodes to obtain the routing table.

5. Click the button to update the routing table. Routing table of entire nodes gets updated after a single
hopping. This is one of the advantages of Link state algorithm over Distance vector algorithm.

Count to Infinity problem:


6. Click on the green color line lying between N3 and N4.

7. Enter forward and reverse weights as -1 to disconnect N4 from the other nodes.

8. Observe the routing table. The values are not changed as it’s not updated.

9. Click the single step button.

10. Now you could see the routing table for each nodes been updated. This is the advantage of ‘Link
state algorithm’ over ‘Distance vector algorithm’.

83
CONTENTS MAXIMUM MARKS
MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

Result:
Thus the LINK STATE ROUTING ALGORITHM was successfully implemented.

84
Ex .no:7 Implementation of Data Encryption and Decryption

Date:

Aim:
To encrypt a file using RC4 encryption algorithm and decrypt the same

Required:
Computer with encryption and decryption software

Initial set-up:
Install jre 1.5(java run time environment) to run this application

Theory:
To carry sensitive information such as military or financial data, a system must be able to assure pri-
vacy. Microwave, satellite and other wireless media, however, cannot be protected from the unauthor-
ized reception (or interception) of transmission. Even cable systems cannot always prevent unauthor-
ized access. Cables pass through out-of-the-way areas (such as basements) that provide opportunities
for malicious access to access to the cable and illegal reception of information.

It is unlikely that any system can completely prevent unauthorized access to transmission
media. A more practical way to protect information is to alter it so that only an authorized
receiver can understand it. Data tampering is not a new issue, nor is it unique to the computer
era.
In fact, there are methods to make information unreadable b unauthorized receivers. The method used
today is called the encryption and decryption of information. Encryption means that the sender trans-
forms the original information to another form and sends the resulting unintelligible message out over
the network. Decryption reverses the encryption process in order to transform the message back to its
original form.

The sender uses an encryption algorithm and a key to transfer the plaintext (the original message) into
a cipher text (the encrypted message). The receiver uses a decryption algorithm and a key to transform
the cipher text back to the original plaintext.

Procedure:
 Double click on RC4 icon.
 Select Step mode and type any text to encrypt. Type any encryption key in either text or bina-
ry mode.
 Click the Next button from the right side panel.
 Now the State table and Key tables are formed.
 The flow of the algorithm in each step is explained in the description panel on the right side.
 In the next step the permutated values are stored in the S Box Permutation.
 Key bit stream is generated from the values obtained from S Box Permutation.
 XOR operation is done between the binary value and key bit stream generated.
 Cipher text is formed corresponding to the XOR value generated.

85
 Copy the cipher text by selecting and pressing ctrl + c.
 Click the clear button and paste the cipher text in the text field.
 Enter the same key that is used for encryption.
 Now you could retrieve back the original message.

CONTENTS MAXIMUM MARKS


MARKS OBTAINED
Preparation 30
Observation 30
Record 40
Total 100

Result: Thus the ENCRYPTION and DECRYPTION of a file using RC4 Encryption and Decryption
Algorithm was successfully implemented.

86
87