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Joules User Guide

Product Version 17.11


September 2017
© 2008-2017 Cadence Design Systems, Inc. All rights reserved.
Portions © IBM Corporation, the Trustees of Indiana University, University of Notre Dame, the Ohio State
University, Larry Wal. Used by permission.
Printed in the United States of America.
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Cadence Joules is based in part on the work of the Qwt project (http://qwt.sf.net).
Product Encounter® Test and Diagnostics contains technology licensed from, and copyrighted by:
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Joules User Guide

Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Additional References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reporting Problems or Errors in Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
What We Changed for this Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
17.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
17.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Cadence Online Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Other Support Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command-Line Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Getting the Syntax for a Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Getting the Syntax for an Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Searching for Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Searching For Commands When You Are Unsure of the Name . . . . . . . . . . . . . . . . 19
Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Three Factors of Chip Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Joules: An Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Flow with Joules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
RTL Power Flow Using Joules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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2
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Installing Joules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Accessing Joules Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Joules Tutorial Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Accessing Joules Command Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3
Power Analysis Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power Tables in Liberty Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4
Library Read and Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Libscore Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Definitions of Commonly Used Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Libscore Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Library Level Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Cell Level Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Plot Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Other Useful Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Current Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Scrubbing Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Sample Library Scrubbing Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5
CPF/1801 – Power Structures in Design . . . . . . . . . . . . . . . . . . . . . . 57
Using MSV in Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Implementing PSO in Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Implementing DVFS Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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6
Design and Power Intent – Read and Elaboration . . . . . . . . . . . 63

7
Simulation, Stimulus Read, and SDB Creation . . . . . . . . . . . . . . . 65
Stimulus Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Generating Stimuli from Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Joules Frame-based Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Reading Stimuli into Joules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Handling Stimulus File Contructs in Joules vs Voltus . . . . . . . . . . . . . . . . . . . . . . . . 71
Reading PHY Database from Palladium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
read_stimulus Use Model for PHY Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Generating PHY Database from Palladium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
read_stimulus Options to Read PHY Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Generating PHY Database for Tutorial Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Reading SHM Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Adding Alias Names to Stims and Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Writing Joules SDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SDB Query Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Using rtlstim2gate with Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
rtlstim2gate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Using Conformal Mapping File with rtlstim2gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Recommended Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Support for VHDL record and System Verilog struct . . . . . . . . . . . . . . . . . . . . . . . . . 88

8
Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Key Clock Gating Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Inserting Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Reviewing Quality of Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Generating Instrumentation for Power Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Stimulus Generation with NCSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Bottom-Up Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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Identifying Clock Gate Low Activity Registers (CGLAR) . . . . . . . . . . . . . . . . . . . . . . . . . 97


Sample Usage of scrub_cglar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Understanding scrub_cglar Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

9
Mapping and DFT Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Reading SDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Synthesis Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Mapping the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DFT Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

10
Clock Tree Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11
Activity Analysis and Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Steps for Activity Analysis and Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
The report_activity Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Other Activity Related Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Vectorless Power Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Priorities w.r.t pin_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Priorities w.r.t stims . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Default Activity Calculation for Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12
Power Analysis and Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Power Analysis Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Propagating Slew in Clock Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Power Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Plotting Power Profile over Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Generating SHM/FSDB to View Power/Activity Profiles . . . . . . . . . . . . . . . . . . . . . . 126
Power Performance Area (PPA) Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Collating Power at SoC Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

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Power Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132


Analyzing Power Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Recommended Power Efficiency Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Power Efficiency Computation Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Power Efficiency Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Sample report_power_ efficiency Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Power Efficiency Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Known Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Rail-based Power Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Rail-based Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

13
Working with GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Invoking and Exiting GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Main Window Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Menu Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Tab List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Joules Flow Tabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Tab List Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Layout Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Setting Color, Visibility, and Selectability for Design Objects . . . . . . . . . . . . . . . . . . 168
Schematic Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
HDL Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Hierarchy Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Object Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Setup Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Run Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Viewing Waveform Signals using SimVision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Running Joules Flow through GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Elaborate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

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Pre Synth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193


Power Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

14
Accessing Reports through Joules Smart Tables . . . . . . . . . . . 199
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Widget Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Plotting Data in GUI Widget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Cross-probing from Widget Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

15
Design Navigation and Power Debug . . . . . . . . . . . . . . . . . . . . . . . . . 211
Getting List of Design Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Getting Instance Pins (or Ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Associated Nets, Net Drivers, and Sink Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

16
Joules Power Bridge - Interface with Other Cadence Tools 213
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Joules Interface for Other Cadence Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

17
RTLScore Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
RTL Shell (RTLSH): An Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
RTLSH Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

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18
Frequently Asked Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

A
Acronyms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

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Preface

■ About This Manual on page 14


■ Additional References on page 14
■ Reporting Problems or Errors in Documentation on page 14
■ What We Changed for this Edition on page 15
■ Customer Support on page 16
■ Command-Line Help on page 17
■ Documentation Conventions on page 19

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About This Manual


This manual describes how to use the Joules platform for power analysis. To use this manual,
you should be familiar with test concepts and with the Genus software.

Additional References
The following sources are helpful references, but are not included with the product
documentation:
■ TclTutor, a computer aided instruction package for learning the Tcl language:
http://www.msen.com/~clif/TclTutor.html.
■ TCL Reference, Tcl and the Tk Toolkit, John K. Ousterhout, Addison-Wesley
Publishing Company
■ IEEE Standard Hardware Description Language Based on the Verilog Hardware
Description Language (IEEE Std.1364-1995)
■ IEEE Standard Hardware Description Language Based on the Verilog Hardware
Description Language (IEEE Std. 1364-2001)
■ IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-1987)
■ IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-1993)
Note: For information on purchasing IEEE specifications go to http://shop.ieee.org/store/ and
click on Standards.

Reporting Problems or Errors in Documentation


The Cadence® Help online documentation lets you view, search, and print Cadence product
documentation. You can access Cadence Help by typing cdnshelp from your Cadence tool
hierarchy.

Contact Cadence Customer Support to file a CCR if you find:


■ An error in the manual
■ An omission of information in a manual
■ A problem using the Cadence Help documentation system

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What We Changed for this Edition

17.11
■ Updated sections:
■ “Identifying Clock Gate Low Activity Registers (CGLAR)” on page 97
■ “Analyzing Power Efficiency” on page 136

17.10
■ Added following sections:
❑ “Adding Alias Names to Stims and Frames” on page 81
❑ “Analyzing Power Efficiency” on page 136
❑ “Identifying Clock Gate Low Activity Registers (CGLAR)” on page 97
❑ “Rail-based Power Analysis” on page 152
❑ “Scrubbing Libraries” on page 51
❑ “Handling Stimulus File Contructs in Joules vs Voltus” on page 71
❑ “Layout Viewer” on page 162
❑ “Schematic Viewer” on page 170
❑ “Viewing Waveform Signals using SimVision” on page 185
■ Enhanced section Frequently Asked Questions.
■ Minor updates to chapter “Working with GUI” on page 157.

16.23
There are no significant updates to the guide for this release.

16.22
Minor updates have been done to chapter Working with GUI.

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16.21
Minor updates have been done to chapter Working with GUI.

16.20
Added the following:
■ Joules Power Bridge - Interface with Other Cadence Tools on page 213
■ Working with GUI on page 157
■ Reading SHM Database on page 80
■ Acronyms and Definitions on page 233

16.10
Added the following sections:
■ Reading PHY Database from Palladium on page 74
■ Using rtlstim2gate with Netlist on page 83
■ Accessing Reports through Joules Smart Tables on page 199

15.23
Added the following sections:
■ Generating Instrumentation for Power Control Signals on page 93
■ Power Sweep on page 132
■ Generating SHM/FSDB to View Power/Activity Profiles on page 126

Customer Support
Cadence offers live and online support, as well as customer education and training programs.

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Preface

Cadence Online Support


The Cadence® Online Support website offers answers to your most common technical
questions. It lets you search more than 40,000 FAQs, notifications, software updates, and
technical solutions documents that give you step-by-step instructions on how to solve known
problems. It also gives you product-specific e-mail notifications, software updates, case
tracking, up-to-date release information, full site search capabilities, software update
ordering, and much more.

For more information on Cadence Online Support go to:

http://support.cadence.com

Other Support Offerings


■ Support centers—Provide live customer support from Cadence experts who can
answer many questions related to products and platforms.
■ Software downloads—Provide you with the latest versions of Cadence products.
■ University software program support—Provides you with the latest information to
answer your technical questions.
■ Video Library - Several videos are available on the support website: Joules Video
Library.
■ Trainings Offerings—Cadence offers the following training courses for Joules:
❑ Joules Power Calculator
❑ Fundamentals of IEEE 1801 Low-Power Specification Format
❑ Low-Power Synthesis Flow with Genus Synthesis Solution

Command-Line Help
Note: The command syntax representation in this document does not necessarily match the
information that you get when you type help command_name. In many cases, the order of
the arguments is different. Furthermore, the syntax in this document includes all of the
dependencies, where the help information does this only to a certain degree.

Getting the Syntax for a Command


Type either of the following to get the syntax and example usage of a command:

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■ help <command name>


■ <command name> -h

For example:
Joules> help read_libs

or
Joules> read_libs -h

Returns the syntax and example usage for the read_libs command.
Note: Examples are shown using Joules tutorial design.

Getting the Syntax for an Attribute


Type the following:
Joules> get_attribute attribute_name * -help

For example:
Joules> get_attribute libs * -help

This returns the syntax for the libs attribute.

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Searching for Attributes


You can get a list of all the available attributes by typing the following command:
Joules> get_attribute * * -h

You can type a sequence of letters after the set_attribute command and press Tab to
get a list of all attributes that contain those letters.
Joules> set_attr li

Returns all the attributes starting with the string li.

Searching For Commands When You Are Unsure of the Name


You can use help to find a command if you only know part of its name, even as little as one
letter.
■ You can type a single letter and press Tab to get a list of all commands that start with
that letter.
For example:
Joules> c <Tab>

Returns all command names starting with c.


■ You can type a sequence of letters and press Tab to get a list of all commands that start
with those letters.
For example:
Joules> read_<Tab>

Returns all command names starting with read_.

Documentation Conventions
The list below describes the syntax conventions used for the Joules commands and
attributes.

literal Non italic words indicate keywords that you must type literally.
These keywords represent command, attribute or option names
arguments and options Words in italics indicate user-defined arguments or options for
which you must substitute a name or a value.

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| Vertical bars (OR-bars) separate possible choices for a single


argument.
[ ] Brackets denote options. When used with OR-bars, they
enclose a list of choices from which you can choose one.
{ } Braces denote arguments and are used to indicate that a
choice is required from the list of arguments separated by OR-
bars. You must choose one from the list
{ argument1 | argument2 | argument3 }
Braces, used in Tcl command examples, indicate that the
braces must be typed in.
... Three dots (...) indicate that you can repeat the previous
argument. If the three dots are used with brackets (that is,
[argument]...), you can specify zero or more arguments.
If the three dots are used without brackets (argument...),
you must specify at least one argument, but can specify more.
# The pound sign precedes comments in command files.

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1
Introduction

This chapter discusses the following:


■ Three Factors of Chip Power
■ Joules: An Overview
■ Power Flow with Joules

In the 90nm and 65nm days, IC designs were smaller, and it was sufficient to measure power
of the design late in the design cycle (typically after P&R), as a sign-off step to validate
packaging and cooling requirements. Shrinking feature sizes has made it possible to pack
manifold more devices in ICs with same size foot-prints, resulting in a significant increase in
their power consumption and dissipation. This has made early power analysis and
management a necessary step in today’s IC design cycle.

Three Factors of Chip Power


Three factors that determine the power of an IC are:
■ Design and Power Structures (RTL, CPF/1801)
■ Implementation (such as library, SDC constraints, clock-tree, physicals)
■ Stimuli through the circuit

Implementation tools (Synthesis, P&R) provide methods to reduce power through


clock-gating, use of low-VT and low drive-strength cells, creation of voltage-domains, use of
power switches, level-shifters for shutoff and power management.

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Figure 1-1 Determining Factors of IC

Leakage power of a design is determined by its implementation. The dynamic power of the
design is determined by the switching activity of the cells due to the applied stimulus.

For an IC design, power, performance, and area are related. The IC designer needs access
to information about design timing, power, physicals, as well as the library cells to be able to
make informed design decisions for an optimal PPA implementation.

Joules: An Overview
Joules is an RTL power analysis product that provides a unified platform to RTL designers
that includes the following:
■ SDC compliant design timing
■ Timing and physical aware, and DFT enabled synthesis engine
■ Integrated CPF/1801 support
■ Clock-tree power estimation

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■ Frame based architecture with multi stimuli support


■ Activity profiling and management
■ Average and time-based power engines
■ Hierarchical and categorical power analysis
■ Tcl shell with word-level data mining and PPA reporting
■ Library and standard-cell analysis
■ Script compatible with Genus

Power Flow with Joules


Although Joules can analyze power of netlist (with and without parasitic), its primary intended
use is for RTL power analysis.

RTL Power Flow Using Joules


The RTL power flow using Joules can be broken into the following steps:

Setup
1. Design Elaboration
In this step, the design (RTL or netlist), library (LIB and optionally LEF), and power intent
(CPF or UPF/1801) are read into Joules and elaborated. The elaborated database
(elab.jdb) is saved for use in the second (process stimuli), and third (mapping) steps.

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Introduction

Figure 1-2 Power Flow with Joules

2. Stimulus Processing and Emulation


Design stimulus for Joules comes from data dumps from simulation. Joules can read
multiple stimuli, in several formats (FSDB, PHY, VCD, SAIF, TCF), and save the stimulus
information as frames in Joules stimulus DB (SDB). The elaborated DB (elab.jdb) is used
to process the stimuli and extract frame-based activity information from them. The
generated SDB is used in the fourth step for PPA (power, performance, area) analysis.
3. Mapping
In this step, the elaborated DB (elab.jdb), the SDC constraint file, and optionally, physical
information (DEF + LEF) are read and synthesized. Joules offers the command
power_map that is much faster than the normal synthesize command (which is also
supported) and creates a fully functional prototype netlist for power analysis and PPA
exploration. The prototype netlist database (proto.jdb) is saved for use in the next step
for PPA analysis.

Run
Annotation, PPA Analysis, and Reporting
In this step, rtlstim2gate is used for annotation of activity from stimulus on registers, I/O
ports, and key RTL control signals such as ICGC enables, and also to set separate
naming rules for simulation/emulation and implementation (synthesis/P&R). Then the

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prototype netlist DB (proto.jdb) and the stimulus DB (SDB) is read into Joules. Joules
allows reading all or some frames from the SDB. After the stimulus has been read in,
power can be computed either in the average or time-based mode. The PPA reporting
follows power computation. Power can be reported by frame, or by stimulus, and by
hierarchy. In addition to power reports, Joules also reports the following:
❑ Activity report by frame, hierarchy, and design element type
❑ Time-based power profile by stimulus, by hierarchy
❑ Clock gating efficiency report by frame, by hierarchy with multiple metrics
❑ Unified PPA (power, performance, area) report of key elements in the design
(memories, registers, ALUs, ICGCs, etc.) by frame, by hierarchy

The Joules commands and the tasks required for all the steps listed above are discussed in
detail in the subsequent chapters.

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2
Getting Started

This chapter discusses the following:


■ Installing Joules
■ Accessing Joules Tutorial
■ Accessing Joules Command Help

Installing Joules
Cadence uses the InstallScape program to download and install software on Linux platform
from the web.

From downloads.cadence.com, select the Joules release you want to install and select
Download by InstallScape.
Note: License information for Joules can be found in the README.txt file at
downloads.cadence.com.

joules -h will show the help for the joules command:


[-work <dir>] : (default: ./joules_work)
All Joules files, unless directed otherwise, go here
[-log <logfile>] : (default: <work>/joules.log)
[-cmd <cmdfile>] : (default: <work>/joules.cmd)
[-overwrite] : overwrite existing cmd/log files (default = false)
[-version] : return program version information
[-batch] : run in batch mode (default: interactive mode)
[-dpa] : run in Palladium/DPA mode (default: false)
[-gui] : invoke GUI (default: interactive mode, gui)
[-display <display>](e.g. -display myvnc:1)
[-common_ui] : run in common_ui mode
[-execute <tcl-command>] : execute command before -files
[-db <db-file>] : load specified DB file (after -execute, before -files)
[-files {<tcl-file>}+] : execute Tcl file(s)
[-E|-abort_on_error] : exit on script error
[-post <tcl-command>] : execute command after -files
[-lsf_cpus <#cpus>] : number of cpus to use in LSF
[-lsf_queue <queue-name>] : name of LSF queue to use
[-accelerate <#count>] : check out 'count -1' copies of startup licenses for
speedup

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[-wait <timeout>] : queue license and wait timeout minutes


[-use_license|-lic_startup <string>] : Joules_RTL_Power
[-add_license <string>+] : additionally checkout any of the following
licenses
Genus_Synthesis
Genus_Physical_Opt
Test_Design_Verification
Modus_DFT_Opt
Modus_LBIST_Opt
Modus_PMBIST_Opt
Modus_Hierarchical_Opt

Note: In DPA mode, Joules supports a select few commands that DPA uses to compute
relative weights for library cells for use in DPA's WTC (Weighted Toggle Count) waveform
from PHY.

Accessing Joules Tutorial


A tutorial is provided with the release to help you get familiarized with the Joules environment
and flow.

By default, the RTLSCORE_ROOT variable is internally set to $INSTALL_DIR/etc/rtls.

The Joules tutorial design, which is a simple 10-bit CPU design, can be found in:
$RTLSCORE_ROOT/tutorial/.

This directory contains the following:


■ cpu_10bit/ RTL Verilog, SDC, and CPF
■ libraries/ LIB, LEF, CAPTABLE, ATPG, and Verilog simulation models
■ stimulus/ 2 x Testbenches, simulation scripts, 1 VCD, and 1 FSDB stimuli
■ dft/ DFT setup and insertion scripts
■ rundir/ Joules run script runMe_joules.tcl

To run Joules tutorial:


$ cp $RTLSCORE_ROOT/tutorial/rundir/runMe_joules.tcl ./runMe_joules.tcl
$ joules –f ./runMe_joules.tcl

To configure the tutorial, modify the following variables in runMe_joules.tcl:


■ demo = 1
Run the tutorial in demo mode (will pause at each step)
■ run_cpf = 1

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Run the tutorial design with CPF


■ run_dft = 1
Enable DFT insertion in the tutorial design
■ pwra_mode = average|time_based
Set the power computation mode to average or time_based (default)

Joules Tutorial Script


When run with CPF and DFT on, the Joules run script is arranged in the following steps:
1. Read library and create library domains
2. Read RTL design and CPF power intent
3. Read stimuli files and create Joules SDB
4. Synthesize the design and insert DFT
5. Generate Clock Tree
6. Perform PPA analysis (compute power)
7. PPA reporting
8. Compare activity propagation and power between Joules and Voltus

Read library and create library domains

The first two lines set the lib_search_path attribute used to look for LIB (and LEF) files.
The CPF-based design requires creation of two library domains, lib_1p08v (1.08v libraries)
and lib_1p20v (1.20v libraries).
Note: In Joules terminology, library set and library domain are used interchangeably when
referring to libraries.

The read_libs command (see “Simulation, Stimulus Read, and SDB Creation” on page 65)
is used to create the two library domains and read the LIB files of these domains. This is
followed by tag_memory command to annotate the address, data out, write enable, and
clock ports of the memory.
set d_lib $d_tutorial/libraries
set_attribute lib_search_path ". $d_lib/LIB $d_lib/LEF"
if { $use_cpf } {
#
# CPF Flow

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# Create library domains used in CPF define_library_set commands


# See tutorial CPF file: $RTLSCORE_ROOT/tutorial/cpu_10bit/cpu.cpf
# define_library_set -name lib_1p08v -libraries $Lib_1p08v_list
# define_library_set -name lib_1p20v -libraries $Lib_1p20v_list
#
set Lib_1p08v_list "slow.lib pwr_mgmt.lib" ;# 1.08v libs
set Lib_1p20v_list "typical.lib CDK_S64x10.lib" ;# 1.20v libs
if { $joules } {
read_libs -domain lib_1p08v -flist $d_lib/LIB/libs_1p08v.txt
read_libs -domain lib_1p20v -libs $Lib_1p20v_list
} else {
set_attribute library $Lib_1p08v_list [create_library_domain lib_1p08v]
set_attribute library $Lib_1p20v_list [create_library_domain lib_1p20v]
}
} else {
#
# Non CPF flow
# No need for library domains
#
if { $joules } {
read_libs typical.lib CDK_S64x10.lib
} else {
set_attribute library typical.lib CDK_S64x10.lib /
}
set_attribute lef_library \
{ gsclib045_tech.lef gsclib045_macro.lef CDK_S64x10.lef }
set_attribute cap_table_file \
$d_lib/CAPTABLE/cln28hpl_1p10m+alrdl_5x2yu2yz_typical.capTbl
}
tag_memory CDK_S64x10 \
-addr ADDR* -din DATA_IN -clock CLOCK \
-dout DATA_OUT \
-wr_enable WR_EN* -mem_enable ENABLE \
-wr_cycles 2 -depth 64 -width 10

Read RTL design and CPF power intent

The first line sets the hdl_search_path attribute used to look for HDL source files. The next
line is the read_hdl command (see “Library Read and Analysis” on page 43) to read the
Verilog design files. That is followed by read_power_intent command (see “Library Read
and Analysis” on page 43) to read the CPF file. This is followed by the elaborate command
(see “Library Read and Analysis” on page 43). After design elaboration, the power intent is
applied and committed using apply_power_intent and commit_power_intent
commands (see “Library Read and Analysis” on page 43). Finally, write_db is use to write
out the elaborated JDB.

Note that the elaborate command must be preceded by read_libs, read_hdl, and
optionally the read_power_intent commands. Also, the apply_power_intent, and
commit_power_intent (optional) commands follow the elaborate command.
set_attribute hdl_search_path $d_rtl /
read_hdl cpu.v fsm.v datapath.v alu.v ram.v

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if { $use_cpf } {
catch { read_power_intent -cpf $CPF -module cpu_10bit }
if { $joules && $demo && ! [cdn_pause "<read_power_intent done> Continue? "]}
{return -1 }
}
elaborate $design
check_design -unresolved
# Read and commit CPF
if { $use_cpf } {
catch { apply_power_intent ; commit_power_intent }
if { $joules && $demo && ! [cdn_pause "<apply/commit_power_intent done>
Continue?"] } { return -1 }
}
# save elab DB
write_db -all -to_file $d_work/${design}_elab.db
if { $joules && $demo && ! [cdn_pause "<elaborate done> Continue? "] } { return -1 }

Read stimuli files and create Joules SDB

In this step, we read two stimuli in time-based mode and create Joules SDB. Frames equal
to 1 cycle of clock /cpu_10bit/clk are extracted from the first stimuli (47 frames), and frames
equal to 5 cycles of clock /cpu_10bit/clk are extracted from the second stimuli (33 frames)
using read_stimulus command (see “Power Analysis Concepts” on page 35). The
write_sdb command (see “Library Read and Analysis” on page 43) saves 47+33 = 80
frames in Joules SDB.
if { $read_stim == "after_elab" } {
if { $joules } {
eval read_stimulus -file $VCD1 -top_instance /${design}_tb/CPU \
$read_stim_timebased_opt ;# -compat voltus
eval read_stimulus -file $VCD2 -top_instance /${design}_tb/CPU \
$read_stim_timebased_opt2 -append ;# -compat voltus
write_sdb -out $SDB
if { $demo && ! [cdn_pause "<read_stimulus done> Continue? "] } { return -1 }
} else {
read_vcd -vcd_scope CPU $VCD1 ;
}
}

Synthesize the design and insert DFT

DFT insertion in Joules (and Genus) happens in the following sequence:


■ After elaboration, set necessary DFT attributes and perform generic synthesis. These
include: scan_chain, test clock, scan mapping and connectivity, segment constraints,
and test mode control.
if { $run_dft } {
source $d_tutorial/dft/dft_setup.tcl ;# setup for DFT
set_attribute ui_respects_preserve false /
}

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synthesize -to_generic -effort medium

Example DFT setup script: $RTLSCORE_ROOT/tutorial/dft/dft_setup.tcl


■ Map the design: power_map | synthesize –to_mapped
■ Insert scan, followed by incremental synthesis and reporting:

source $d_tutorial/dft/dft_scan.tcl
synthesize -to_mapped -effort medium -incr
source $d_tutorial/dft/dft_report.tcl

Example scan insertion script:


$RTLSCORE_ROOT/tutorial/dft/dft_scan.tcl
Example DFT reporting script:
$RTLSCORE_ROOT/tutorial/dft/dft_report.tcl
■ ATPG analysis (optional) – generate Encounter Test (ET) run script for test pattern
generation (write_et_atpg command), invoke ET on the generated script for scan
coverage analysis, and validate the generated scan patterns using ncsim.

write_et_atpg -directory ./et_work -library $d_lib/atpg/stdcell.v \
-ncsim_library "$d_lib/verilog/include_libraries_sim.v"
exec et -e ./et_work/runet.atpg ;# run ATPG and report scan coverage
exec ./et_work/run_fullscan_sim ;# validate patterns in ncverilog (optional)

■ After synthesis and optional DFT insertion, save the proto JDB:
write_db -all -to_file $f_proto_db
puts stdout "Joules DB saved in: $f_proto_db"

Generate Clock Tree

In this step, Joules generates a clock tree (gen_clock_tree command) for power
estimation. The generated clock tree is stored in memory and not saved in the JDB.
set root_fanout 3 ; set branch_fanout 3 ; set leaf_fanout 4
set root_buffers "slow/CLKBUFX2" ; set branch_buffers "slow/CLKBUFX2"
set leaf_buffers "slow/CLKBUFX2 slow/CLKBUFX6"
gen_clock_tree -name CT1 \
-fanout root=$root_fanout branch=$branch_fanout leaf=$leaf_fanout \
-root_buffers $root_buffers -branch_buffers $branch_buffers
-leaf_buffers $leaf_buffers \
-max_tree_depth 5

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Perform PPA analysis (compute power)

In this step, Joules computes the design power (compute_power command) either in
average mode (average activity over all SDB frames) or time-based mode (average power for
each SDB frame).
...
compute_power -mode time_based
...

PPA reporting

After power computation, Joules can generate a variety of reports and plots including activity
report (report_activity command), average power report (report_power command),
time-based power plot (plot_power_profile command), Clock Gating Instances (ICGC)
efficiency report (report_icgc_efficiency command), and PPA (power, performance,
area) report (report_ppa command). All report and plot commands are frame and power-
mode aware.
set f_rpt ${design}.rpt

report_activity -out $f_rpt
report_ppa -out $f_rpt -append ;# requires compute_power
report_power -out $f_rpt -append
plot_power_profile -frame {/stim#1/frame#[1:47]} -category memory register logic
clock
plot_power_profile -frame {/stim#2/frame#[1:33]} -category memory register logic
clock
report_icgc_efficiency -out $f_rpt -append

Compare activity propagation and power between Joules and Voltus

Joules provides an interface to Voltus, the power signoff product from Cadence, through the
voltus_compare command. In this step, this command is used to compare the activity
(duty and toggle) on all leaf cell output pins between Joules and Voltus for each stimulus. The
comparison plots for the first stimulus looks as shown below.
foreach stim_id [get_sdb_stims] {
set f_stim [get_stim_info $stim_id -src_file]
set bname [lindex [split [file tail $f_stim] "."] 0]
voltus_compare -stimulus $stim_id -bname $bname -generate script -pin_dir out
voltus_compare -stimulus $stim_id -bname $bname -generate data
exec voltus -init voltus_work/$bname_run_voltus.tcl
voltus_compare -bname $bname -plot all
}

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Figure 2-1 Comparison Plots between Joules and Voltus

Accessing Joules Command Help


You can get quick syntax help for commands and attributes at the Joules command-line
prompt. Enhanced search capabilities are also available so you can more easily search for
the command or attribute that you need. Refer to “Command-Line Help” on page 17 for more
information.

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3
Power Analysis Concepts

There are three components of power for CMOS devices:


■ Leakage power - Also known as the static power, leakage power dissipation in CMOS
devices is primarily due to leakage current between source and drain of the CMOS
device. This component of leakage power, commonly known as subthreshold leakage,
occurs because the CMOS device does not fully turn off even when the gate voltage falls
below the transistor’s threshold voltage. A second component of leakage power is due to
leakage current between the diffusion layers and the substrate. This is typically much
smaller than the subthreshold leakage, and is mostly ignored.
■ Internal power - As the name implies, internal power is the power consumed by an
instantaneous short circuit between the voltage supply (rail) and ground, when the
transistor gate transitions from off to on state, and the power dissipates when charging
and discharging internal net capacitances of the CMOS device.
■ Switching power - Also known as the net or load power. Switching power is the power
consumed when charging and discharging the capacitive load of a CMOS device. This
load includes the capacitance of the device input pins (also known as internal cell
power), and net capacitance of external downstream devices.

Power Tables in Liberty Libraries


For standard cells and memories, the leakage and internal power is characterized by
technology vendors and provided by them in the LIB files in the following form:
■ Leakage power
Cell leakage power in LIB files, are specified using constructs
cell_leakage_power() and leakage_power().The cell_leakage_power()
denotes the default value for the cell, and leakage_power() denotes the leakage
power under the specified when condition.
cell (AND2FX1) {

cell_leakage_power : 0.089; // default value
leakage_power() { when : "!A & !B"; value : 0.093; }

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leakage_power() { when : "!A & B"; value : 0.072; }


leakage_power() { when : "A & !B"; value : 0.086; }
leakage_power() { when : "A & B"; value : 0.102; }

}

■ Internal power
Cell internal power in LIB files are specified using internal_power() construct,
typically one for each I/O arc. Each internal_power() contains rise_power(), and
fall_power() tables. Presence of when conditions indicate conditional power tables.
Power tables are functions of input slew and output loads, and these form the two indices
of the tables.
cell (AND2X1) {

pin(Y) {
direction : output;

function : "(A B)";

internal_power() {
related_pin : "A";
rise_power(energy_template_7x7) {
index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28");
index_2 ("0.01, 0.016, 0.05, 0.08, 0.12, 0.2, 0.25");
values ( \
"0.001396, 0.001399, 0.001401, 0.001401, 0.001402, 0.001404, 0.001402",\
"0.001367, 0.00137, 0.001374, 0.001375, 0.001375, 0.001376, 0.001376",\
"0.001354, 0.001358, 0.001364, 0.001366, 0.001366, 0.001367, 0.001367",\
"0.001353, 0.001357, 0.001363, 0.001364, 0.001363, 0.001364, 0.001364",\
"0.001348, 0.001355, 0.001362, 0.001364, 0.001365, 0.001365, 0.001365",\
"0.001352, 0.001358, 0.001367, 0.00137, 0.001371, 0.001371, 0.001371",\
"0.001361, 0.001366, 0.001376, 0.001377, 0.001378, 0.001379, 0.00138");
}
fall_power(energy_template_7x7) {
index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28");
index_2 ("0.01, 0.016, 0.05, 0.08, 0.12, 0.2, 0.25");
values ( \
"0.002461, 0.002465, 0.002471, 0.002472, 0.002473, 0.002473, 0.002473",\
"0.002442, 0.002448, 0.002457, 0.002458, 0.002459, 0.00246, 0.00246",\
"0.002435, 0.002443, 0.002456, 0.002458, 0.00246, 0.002461, 0.002461",\
"0.002435, 0.002444, 0.00246, 0.002463, 0.002465, 0.002466, 0.002467",\
"0.002441, 0.002451, 0.002468, 0.002471, 0.002473, 0.002475, 0.002476",\
"0.002447, 0.002458, 0.002476, 0.00248, 0.002483, 0.002485, 0.002486", \
"0.002461, 0.002472, 0.002493, 0.002496, 0.002501, 0.002502, 0.002504");
}
}
internal_power() {
related_pin : "B";

}

}

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■ Switching Activity and Power


Given a design with n instances and m nets, the power of the design is computed as:

Where:
■ Pleakage is the leakage power of a cell instance in the design
■ Pinternal is the internal power of a cell instance in the design
■ Pnet is the switching power of a net in the design

Leakage and internal power of design instances are computed using power tables of the cell
from LIB, slew and activity (toggle and duty) of input pins, and capacitive load of output pin(s).
The switching (or net) power is computed using the net capacitive load and toggle. The
following table shows the relationship among these power types.

Table 3-1 Power Table

Input Output
Slew Duty Toggle Load Duty Toggle
Leakage X √ X X X X
Internal √ √ √ √ X X
Switching X X X √ X √

■ Leakage power calculation


The leakage power of a cell is calculated as follows:

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Where:
■ k is the number of states of the cell
■ Pstate_leakage is the leakage of the cell in that state
■ probabilitystate is the probability that the cell is in this state

Using the cell leakage power table for AND2X2 cell above, and assuming the probability
(duty) of pin A = 0.4, and that of pin B = 0.3, the leakage power for this cell will be computed
as:
0.093 * prob(!A) * prob(!B) +
0.072 * prob(!A) * prob(B) +
0.086 * prob(A) * prob(!B) +
0.102 * prob(A) * prob(B)
= 0.093 * 0.6 * 0.7 + 0.072 * 0.6 * 0.3 + 0.086 * 0.4 * 0.3 + 0.102 * 0.4 * 0.3
= 0.07458

If the leakage power table conditions are incomplete (for example, if the last condition in the
example above did not exist), the cell_leakage_power is used as the filler value for the
missing condition.

As per the Liberty 2013 Standard Guide, the leakage power conditions, if present, are
expected to be mutually exclusive. If they are not, for example, condition 1 is “A & B”, and
condition 2 is “A | B”, the computed leakage power number may vary between Joules and
other tools.
■ Internal power calculation
The internal power of a cell is calculated as follows:

Where:
■ TR is the effective toggle rate of the arc. It depends on the toggle rate of input pin (i) and
probability that the arc gets activated. The probability that the arc gets activated is
determined by the function of output pin (j), and probabilities of the other output pins.
■ Φ is the power obtained from the cell internal power lookup table
■ Si is the slew of input pin (i)
■ Cj is the capacitive load driven by output pin (j)

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The following example illustrates the internal power computation for a library cell:
library(typical) {
delay_model : table_lookup;
in_place_swap_mode : match_footprint;

/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
capacitive_load_unit (1,pf);

cell (SDFFRHQX1) {

pin(CK) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.00062006;
rise_capacitance : 0.000619877;
fall_capacitance : 0.00062006;
clock : true;
internal_power() {
rise_power(passive_energy_template_7x1) {
index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28");
values ("0.003258, 0.003232, 0.003219, 0.00322, 0.003231, 0.003255, 0.003272");
}
fall_power(passive_energy_template_7x1) {
index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28");
values ("0.008198, 0.008172, 0.008165, 0.008184, 0.008197, 0.008238, 0.008275");
}
}

} /* end pin CK */

pin(Q) {
direction : output;

internal_power() {
related_pin : "CK";
rise_power(energy_template_7x7) {
index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28");
index_2 ("0.01, 0.016, 0.05, 0.08, 0.12, 0.2, 0.25");
values ( \
"0.007508, 0.007498, 0.007449, 0.00743, 0.007418, 0.007407, 0.007403", \
"0.007477, 0.007467, 0.007419, 0.0074, 0.007387, 0.007376, 0.007373", \
"0.007462, 0.007453, 0.007406, 0.007386, 0.007374, 0.007363, 0.007358", \
"0.007462, 0.007453, 0.007407, 0.007387, 0.007374, 0.007363, 0.007358", \
"0.007473, 0.007465, 0.007419, 0.0074, 0.007386, 0.007374, 0.00737", \
"0.007489, 0.007482, 0.007439, 0.00742, 0.007406, 0.007393, 0.007388", \
"0.007517, 0.007511, 0.00747, 0.007451, 0.007436, 0.007423, 0.007419");
}
fall_power(energy_template_7x7) {
index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28");
index_2 ("0.01, 0.016, 0.05, 0.08, 0.12, 0.2, 0.25");
values ( \
"0.007758, 0.007768, 0.007781, 0.007784, 0.007786, 0.007787, 0.007788", \
"0.00773, 0.007739, 0.007753, 0.007756, 0.007758, 0.007759, 0.00776", \
"0.007726, 0.007735, 0.007749, 0.007752, 0.007754, 0.007755, 0.007756", \
"0.007742, 0.007752, 0.007765, 0.007768, 0.00777, 0.007772, 0.007772", \
"0.007757, 0.007766, 0.007779, 0.007782, 0.007784, 0.007785, 0.007786", \
"0.00779, 0.007799, 0.007812, 0.007815, 0.007816, 0.007818, 0.007818", \
"0.00785, 0.00786, 0.007873, 0.007875, 0.007877, 0.007878, 0.007879");

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}
}

} /* end pin Q */

}

Let us use the following assumptions:


■ Slew of CLK pin = 8 ps
■ Load on Q pin = 10 ff
■ Toggle rate of CLK pin = 9.89247e+08 per sec
■ Toggle rate of arc CLK->Q = 3.82934e+08 per sec

Internal power = Arc power component (internal_power group with related_pin) + pin power
component(internal_power group without related_pin)

Arc power (CLK -> Q) component of internal power


rise energy (8ps, 10 ff) = .007508 pJ (pico Joules)
fall energy (8ps, 10 ff) = .007758 pJ (pico Joules)

Total_arc_power_dissipated
= Total_arc_energy_dissipated / analysis_duration
= (average_energy_per_arc_event X number_of_arc_event) / analysis_duration
= ( (rise_energy + fall_energy) / 2 ) X toggle_rate_of_arc
= (.007508 + .007758)/2 pJ X 3.82934e+08 sec
= 2.922 uW

Pin power (CLK) component of internal power


rise energy(8ps) = .003258 pJ
fall energy (8ps) = .008198 pJ

Total energy = average energy per transition X number of transition of CLK pin

Total_power_dissipated = Total_energy_dissipated / analysis_duration


= (average_energy_per_transition X # CLK_pin_transitions) / analysis_duration
= ( (rise_energy + fall_energy) / 2 ) X CLK_pin_toggle_rate
= (.003258 + .008198) / 2 X 9.89247e+08
= 5.6 uW
Internal power = 2.922 + 5.6 uW = 8.522 uW

■ Switching power calculation

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The switching (or net) power of a net is calculated as follows:

Where:
■ CL is the capacitive load of the net
■ V is the supply voltage
■ TR is the toggle rate of the net

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4
Library Read and Analysis

This chapter discusses the following:


■ Libscore Functionality
■ Definitions of Commonly Used Terms
■ Libscore Commands
❑ Library Level Utilities
❑ Cell Level Utilities
❑ Plot Commands
❑ Other Useful Utilities
■ Current Limitations
■ Scrubbing Libraries

Libscore Functionality
Standard cell libraries form the basic building blocks of digital designs. It is important to
analyze standard cell libraries to: (i) understand timing, power, area profiles of standard cells,
(ii) drive strength distribution of cells, (iii) identify sub-optimal cells for specific characteristics
(for example, leakage), and more.

Integrated in Joules, is the Libscore functionality that provides a framework of quantifiable


metrics and a set of Tcl utilities for qualification of standard cell libraries and cells. These
include the following capabilities:
■ Auto identification of memories
■ Auto identification of clock buffers
■ Programmatic identification and marking of dont_touch cells
■ Cell grouping by function and drive strength

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Library Read and Analysis

■ Cell property query (function, area, timing, power)


■ Cell pin queries by pin type (data, clock, reset, etc.) and direction (input, output)
■ Cell summary table reporting
■ Display of cell tables (delay, power)
■ Plots showing cell drive profile, slew/load sensitivity, library quality

Libscore functionality is auto enabled in Joules and kicks in once the libraries are read in
using the read_libs command (see subsequent sections).

Definitions of Commonly Used Terms


■ Cell DR – Drive resistance of the cell, computed as the slope of cell transition delay (rise
and fall) with respect to change in load.
■ x1 Cell – User specified, or auto detected reference standard cell with drive strength of
1.0.
■ Cell DS – Drive strength of the cell, computed as the ratio of x1 cell DR and cell DR of
the cell.
■ DS Margin – Cell grouping commands in Libscore allow grouping of cells by drive
strength. As the computed cell drive strengths are real numbers (do not snap to integer
values), the –drive_strength option supports specification of ds_margin as an
optional third argument. By default, a value of 0.1 (10%) is used for ds_margin.
■ Slew Degradation – This is the fraction by which the slew (transition time) of the input
degrades through the cell. For example, if an input slew value of 0.10ns becomes 0.12
at the output, the slew degradation is (0.12 – 0.10)/0.10 = 20%.
■ Load threshold – For a cell, this is the load value at which the cell slew response
degrades. That is, the output transition time becomes worse than the input slew.
■ RF Ratio – Stands for rise/fall ratio and is a computed metric for cell delay (cell_rise/
cell_fall), transition delay (transition_rise/transition_fall), and other
related cell properties.
■ Operating load/slew – Several cell properties such as cell_rise,
transition_fall, and drive_strength are functions of input load and slew
values. The cell property query command(s) allow specification of input load/slew values
using –load and –slew options. However, to avoid repetitive specification of these
options, Libscore allows specification of operating load/slew values for the library. These
values are used as default if –load/-slew options are not specified with a command.

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■ Sense – Typically associated with signal waveform, the sense indicates rise or fall of the
signal.

Libscore Commands
The following categories of commands are supported in Libscore:
■ get commands – these return queried values. Return value of -1 indicates error.
■ report commands – these dump out reports on stdout or file. Returns 0 on success,
1 on error.
■ plot commands – these use gnuplot to display plot. Returns 0 on success, 1 on error.
■ show commands – these are similar to report commands, except that they are typically
used to dump out information about objects such as library and cells.

Library Level Utilities


■ read_libs
Reads a list of libraries into Joules. Refer to read_libs in Joules Command Reference
for information on command syntax and usage.
■ get_lib_domains
Returns a list of library domains read into Joules. Refer to get_lib_domains in Joules
Command Reference for information on command syntax and usage.
■ get_libraries
Returns a list of libraries read into Joules. Refer to get_libraries in Joules Command
Reference for information on command syntax and usage.
■ get_lib_param
Returns queried library parameter. Refer to get_lib_param in Joules Command
Reference for information on command syntax and usage.
■ set_lib_param
Sets a parameter on a library. Refer to set_lib_param in Joules Command Reference
for information on command syntax and usage.
■ show_lib_params

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Shows summary information for specified library. This includes defaults, units, and
operating conditions. Refer to show_lib_params in Joules Command Reference for
information on command syntax and usage.

Cell Level Utilities


■ get_libcells
Returns cells that satisfy a condition. Refer to get_libcells in Joules Command
Reference for information on command syntax and usage.
■ get_cell_param
Returns cell parameter values. Refer to get_cell_param in Joules Command
Reference for information on command syntax and usage.
■ get_cell_pins
Returns a list of cell pins. Refer to get_cell_pins in Joules Command Reference for
information on command syntax and usage.
■ show_cell_info
Shows summary information for specified cell. If an x1_cell is specified, then drive
strength of the cell w.r.t. the specified x1_cell will be shown. Refer to show_cell_info in
Joules Command Reference for information on command syntax and usage.
■ report_libcells
Generates a tabular report for specified cells. Refer to report_libcells in Joules
Command Reference for information on command syntax and usage.
A sample generated report is shown below.
report_libcells -cells $x1_comb_cells -slew_margin 0.2 -lib typical
#--------------------------------------------------------------------------
# cell : area iCnt drive max_cap load_thresh avg_icap rf_fac
#--------------------------------------------------------------------------
XNOR3XL : 7.5200 3 0.8174 0.1431 2.000e-01 0.0013 1.4840
DLY1X1 : 3.0800 1 0.9727 0.2569 2.500e-01 0.0006 1.0120
DLY3X1 : 8.2100 1 0.9727 0.2590 2.500e-01 0.0007 1.0140
NAND4BX1 : 2.3900 4 0.9727 0.0717 2.500e-01 0.0008 0.2990
NAND3BX1 : 2.0500 3 0.9732 0.0959 2.500e-01 0.0008 0.3900
NAND2BX1 : 1.3700 2 0.9735 0.1475 2.500e-01 0.0008 0.5610
DLY2X1 : 5.8100 1 0.9741 0.2671 2.500e-01 0.0006 1.0150
NOR4BX1 : 2.3900 4 0.9774 0.0612 2.500e-01 0.0008 3.6460
NOR4BBX1 : 2.7400 4 0.9775 0.0631 2.500e-01 0.0008 3.6640
NOR2BX1 : 1.3700 2 0.9779 0.1414 2.500e-01 0.0008 1.9000
NOR3BX1 : 2.0500 3 0.9779 0.0963 2.500e-01 0.0008 2.7830
AND2X1 : 1.3700 2 0.9798 0.2631 2.500e-01 0.0006 1.0130
AO21X1 : 2.3900 3 0.9816 0.2586 2.500e-01 0.0007 1.0150
OR2X1 : 1.3700 2 0.9820 0.2600 2.500e-01 0.0006 1.0140

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AOI2BB1X1 : 2.0500 3 0.9823 0.1313 2.500e-01 0.0008 1.8990


MX2X1 : 2.3900 3 0.9825 0.2527 2.500e-01 0.0009 1.0140
MXI4X1 : 7.1800 6 0.9828 0.2585 2.500e-01 0.0010 1.0140
MXI3X1 : 6.5000 5 0.9833 0.2570 2.500e-01 0.0008 1.0140
AO22X1 : 2.7400 4 0.9837 0.2612 2.500e-01 0.0006 1.0150
XNOR2X1 : 2.3900 2 0.9840 0.2593 2.500e-01 0.0009 1.0140
CLKXOR2X1 : 2.7400 2 0.9846 0.2599 2.500e-01 0.0009 1.0130
XOR2X1 : 2.7400 2 0.9846 0.2599 2.500e-01 0.0009 1.0130
DLY4X1 : 9.9200 1 0.9862 0.2626 2.500e-01 0.0007 0.9990
NAND4BBX1 : 3.4200 4 0.9874 0.0692 2.500e-01 0.0008 0.2950
AND3X1 : 2.3900 3 0.9892 0.2603 2.500e-01 0.0006 1.0160
OA22X1 : 2.3900 4 0.9892 0.2550 2.500e-01 0.0006 1.0130
TBUFX1 : 3.4200 2 0.9895 0.2476 2.507e-01 0.0013 1.0030
#--------------------------------------------------------------------------

■ get_cell_pin_type
Returns pin type for specified cell pin. Refer to get_cell_pin_type in Joules Command
Reference for information on command syntax and usage.
■ show_cell_tables
Displays specified cell table. Refer to show_cell_tables in Joules Command
Reference for information on command syntax and usage.

Plot Commands
■ plot_cell_sensitivity
Refer to plot_cell_sensitivity in Joules Command Reference for information on
command syntax and usage.

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Sample plots showing slew sensitivity for a buffer cell BUFX1 from a 180nm library is
shown below.

Figure 4-1 Sample Slew Sensitivity Plots

■ plot_drive_profile
Refer to plot_drive_profile in Joules Command Reference for information on
command syntax and usage.
Sample plot showing the area vs drive_strength for inv, buf, and nand class of cells.

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Figure 4-2 Sample Area vs Drive Strength Plot

■ plot_lib_quality
Refer to plot_lib_quality in Joules Command Reference for information on command
syntax and usage.
Example library quality plot for 180nm library showing distribution of cell drive strengths
per cell class is shown below. Each strand represents cells with different number of
inputs (for example, 2-input AND, 3-input AND).

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Figure 4-3 Sample Library Quality Plot

Other Useful Utilities


■ infer_memory_cells
Memory cells in LIB are expected to be tagged with is_memory() property. Many times,
however, this property is missing from the cell definitions, and tools that rely on this
property, fail to recognize memories. The infer_memory_cells command in Libscore
uses the following heuristics to infer memory cells from the LIB:
❑ Area of memory cells are larger than typical cells
❑ Will have atleast 2 input buses (data-in and addr)
❑ Will have at least 1 set of input and output buses of the same width (data-in and
data-out)
Refer to infer_memory_cells in Joules Command Reference for information on
command syntax and usage.

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■ infer_clock_buffers
Clock buffers typically have rise/fall ratio closer to 1.0 over normal buffers. This property
is used to distinguish clock buffers from normal buffers. The command allows setting of
the rise/fall margin and some other options to infer and return list of desired clock buffers.
Refer to infer_clock_buffers in Joules Command Reference for information on
command syntax and usage.
■ tag_memory
While the infer_memory_cells can be used to automatically infer memory cells, this
command cannot identify several key signals, such as write enable, memory depth, and
read/write address. The tag_memory command allows you to identify these signals for
the memory cells.
Refer to tag_memory in Joules Command Reference for information on command
syntax and usage.

Current Limitations
■ Cell names must be unique across domains and libraries. Consider a cell as the path: /
domain/library/cell. This pathname for each cell must be unique.
■ No support for physical (LEF) and transistor (CDL) view of standard cells.

Scrubbing Libraries
In a typical scenario, a Joules library includes many cells with bad area or power profiles, as
depicted in the following figures.

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Figure 4-4 Library Cells with Bad Power

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Figure 4-5 Library Cells with Bad Area

Presence of such cells in a library either increases synthesis time or compromises on the
QOR (delay, area, power) results.

Joules command, scrub_library, enables you to score cells in a library and select the best
cells, thus removing cells with bad area/power profiles and reducing synthesis runtime
without compromising QOR.

Refer to scrub_library in Joules Command Reference for information on command syntax


and usage

The scrubbing process is as follows:


1. Bucketize cells by function (and ipin cnt), for example, AND2, OR3. By default, cells are
bucketized by cell type and input pin count. Use -buckets option to change this.
2. Set the following scoring weights for the cells:
cell area, delay, transition, leakage_power, internal_power
These parameters are set using the -weights option, as shown below:
-weights delay=2 transition=1 area=1 leakage=1 internal=1

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3. Cluster cells in each bucket by drive strength. By default, cell with highest score is kept.
Use -cells_per_ds_cluster or -pct_keep option to change this. If -buckets
option is used, you can use -per_bucket_cells_per_ds_cluster or -
per_bucket_pct_keep option to specify cells_per_ds_cluster and pct_keep values
for each specified bucket.
4. Generate an avoid script file with cell dont_use commands joules_work/
dont_use_<lib_name>.tcl, where <lib_name> is the logical name of the library.
Use -f_script option to change this.
5. Generate either a plot (-plot option) or a table (-report option) for the library scrub
results.

The following figure shows a sample flow for executing the scrub_library command with
examples.

Figure 4-6 Recommended Scrub Library Flow

Sample Library Scrubbing Output


Some examples of scrub_library command and the respective plot output are depicted
in the following figures.

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Figure 4-7 Scrub Library Example 1

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Figure 4-8 Scrub Library Example 2

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5
CPF/1801 – Power Structures in Design

This chapter discusses the following:


■ Using MSV in Design
■ Implementing PSO in Design
■ Implementing DVFS Design

You can use CPF or UPF (IEEE 1801) to bring in power structures in your design that includes
the following:
■ Multiple Supply Voltages (MSV) in your design
■ Implement Power Shutoff (PSO) capability
■ Implement Dynamic Voltage/Frequency (DVFS) scaling

Using MSV in Design


An MSV design uses multiple supply voltages for the core logic. In Figure 5-1, the top design
and instance inst_A operate on voltage VDD1, inst_B operates on voltage VDD2, and
instance inst_C operates on voltage VDD3. Design portions that operate at the same voltage
are referred to as power domain that corresponds to that operating voltage.

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Figure 5-1 MSV Design

Instances Libraries Power


Operating
Operating on Characterize Library Set Domains for
Voltage (OV)
OV for OV OV
VDD1:0.8 top, inst_A lib1 lib2 set1 PD1
VDD2:1.0 inst_B lib3 set2 PD2
VDD3:1.2 inst_C lib4 set3 PD3

As libraries are characterized for a specific set of operating conditions, power domains must
use libraries characterized for their operating voltage. This requires grouping of libraries
characterized for the same nominal conditions in a library domain. In the example above, a
library domain was created corresponding to each power domain. LIB1 and LIB2 were
associated with library domain set1, and so on. See read_libs on page 45 to see how to
group libraries in a library domain.

To pass signals between power domains, level shifters are required. As the name indicates,
level shifter cells change the operating voltage of a signal from the source power domain to
the destination power domain (these cells are characterized for multiple to/from voltages).

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Implementing PSO in Design


A PSO implementation provides the ability to shut off portions of the design, saving both
leakage and dynamic power. Design elements in a power domain can be shut off by switching
off the domain’s power supply. The example below shows a design with three power domains:
PD1, PD2, and PD3.

Figure 5-2 Sample Design with 3 Power Domains

The table below shows three power modes of the design. A power mode is steady state of
the design in which some power domains are switched on, while others are switched off. Also,
in a power mode, each power domain operates in a specific voltage. Voltage of 0 volts
indicates the power domain is shut off.

Power Power Domain


Mode
PD1 PD2 PD3
PM1 1.1V 1.1V 1.1V

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PM2 1.1V 0.0V 1.1V


PM3 1.1V 0.0V 0.0V

To prevent propagation of unknown states into a power domain that is powering up, isolation
cells are used at the domain boundaries. To facilitate domain power-up, state retention cells
are used for some sequential cells that preserve their state during the power-down period.
Voltage supplies for power domains are controlled through power switches. Special control
signals are used to shut down a power domain, enable state retention, and enable isolation
cells. The table below shows control signals used in this example.

Power Control Signals


Domain
Power Switch Isolation Cell State Retention
Cell
PD1 no control signal no control signal no control signal
PD2 ps_enable[0] ice_enable[0] pge_enable[0]
PD3 ps_enable[1] ice_enable[1] pge_enable[1]

Implementing DVFS Design


DVFS reduces power in a chip by scaling down the voltage and frequency when peak
performance is not required. A design using DVFS is a special case of an MSV design
operating in multiple design modes, where the operating voltages can be changed
dynamically.

DVFS designs require variable power supplies that can generate the required voltage levels
with fast voltage transition and minimal transition energy loss. When scaling the voltage, the
frequency must be scaled accordingly to meet the required signal propagation delay. A power
scheduler block can intelligently compute the appropriate frequency and voltage levels
needed to execute various applications.

The example below shows a DVFS design with three power domains: (i) PLL power domain,
containing block PLLCLK_INST, is an always-on block that operates at 0.99v, (ii) TDSPCORE
power domain operating at 0.792v, containing TDSP_CORE_INST block, and (iii) AO power
domain containing pm_inst, and other blocks that are always on, but with dynamically scaled
voltage and frequency.

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Figure 5-3 Sample DVFS Design

The table below shows the three power modes of the design with the worst case voltages
ranging from 0.792 volts to 0.99 volts. The typical voltages for the design range from 0.88 volts
to 1.1 volts.

Power Corresponding Power Domain


Mode
AO PLL TDSPCore
Full 0.99 0.99 0.792
Slow 0.99 0.99 0.0

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Sleep 0.792 0.99 0.0

The table below shows the power control signals for this DVFS design.

Power Control Signals


Domain
Power Switch Isolation Cell State Retention
Cell
AO no control signal no control signal no control signal
PLL no control signal no control signal no control signal
TDSPCore ps_enable iso_enable pg_enable and
pg_restore

CPF codes for all of these examples above can be found in Chapters 10, 11, and 12
respectively in the Guide Low Power in Genus UPF examples can be found in Chapter 13
in the guide Low Power in Genus.

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6
Design and Power Intent – Read and
Elaboration

Joules is command compatible with Genus and supports all Genus commands to read
Verilog, VHDL, System Verilog, or mixed language designs (RTL or netlist) and CPF or 1801
power intent files. The primary commands for design and power intent read are:
■ read_hdl
Refer to the Command Reference for Genus for command syntax and usage.
The read_hdl command is cumulative. Multiple files can be read using a sequence of
read_hdl commands. This enables read of mixed language designs. For more
information on the read_hdl command, refer to Chapter 4 in Genus User Guide.
Refer to read_hdl in Joules Command Reference for information on command syntax
and usage in Joules.
Related Attributes
hdl_search_path - Search directories for HDL files.
■ read_power_intent
Refer to the Command Reference for Genus for command syntax and usage.
Joules (and Genus) supports a single read_power_intent command in the flow.
Mixed CPF and 1801 power intent files are not supported. For more information on the
read_power_intent command, refer to Chapter 10 in Genus User Guide.
Refer to read_power_intent in Joules Command Reference for information on
command syntax and usage in Joules.
■ elaborate
Refer to the Command Reference for Genus for command syntax and usage.
The elaborate command creates the design hierarchy, identifies unresolved
references, infers registers, and performs HDL optimizations such as constant

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propagation and dead code removal. Before calling the elaborate command, you
must:
❑ Read the library and create necessary library domains (see read_libs on
page 45)
❑ Read the HDL design (see read_hdl on page 63)
❑ Read the power intent (see read_power_intent on page 63)
The elaborate command in Joules is an instrumented version of the elaborate
command in Genus. As Joules is an RTL analysis tool, it needs to preserve the RTL
hierarchy, macro and register boundaries necessary for word-level reporting. To achieve
that, the following attributes are pre-set in Joules’ elaborate command:
❑ Flop naming and preserve RTL register names
set_attribute hdl_array_naming_style %s\[%d\] /

❑ Preserve RTL hierarchy


foreach subd [find /designs -subd *] { set_attribute ungroup_ok false $subd
}

■ write_db
Refer to the Command Reference for Genus for command syntax and usage.
In Joules, it is recommended to write out the Joules database (JDB) after elaboration.
The elaborated JDB is used to process the stimulus (see Power Analysis Concepts on
page 35).

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7
Simulation, Stimulus Read, and SDB
Creation

This chapter discusses the following:


■ Stimulus Formats
■ Generating Stimuli from Simulation
■ Joules Frame-based Architecture
■ Reading Stimuli into Joules
■ Reading PHY Database from Palladium
■ Reading SHM Database
■ Writing Joules SDB
■ Using rtlstim2gate with Netlist

Stimulus, a key ingredient of power analysis, is the dump of signal activity data from
simulation of the design. All simulators (and emulators) offer utilities that dump signal activity
data into files for use by tools such as waveform viewers, debugging tools, and power analysis
tools.

Stimulus Formats
The stimulus comes in various formats. The commonly used ones are:
■ VCD (Value Change Dump)
VCD is a text format and one of the oldest formats around. As the name suggests, VCD
files capture the change of signal values over time.
See example here: $RTLSCORE_ROOT/tutorial/stimulus/cpu_10bit_pgm_hash.vcd
■ FSDB (Fast Signal DataBase)

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FSDB is a binary format and like VCD, stores change of signal values over time. It was
introduced initially to work with SpringSoft’s Debussy debugger, and has been widely
adopted by other tools since it is much more compact than VCD.
■ TCF (Toggle Count Format)
This is a text format that records average activity data (toggle count) over certain
simulation duration. As it saves average toggle data, TCF is very compact, and is used
by several Cadence tools such as Voltus (VOLTUS) and Genus for power analysis.
See example here: $RTLSCORE_ROOT/tutorial/stimulus/cpu_10bit_pgm_hash.tcf
■ SAIF (Switching Activity Interchange Format)
Like TCF, SAIF is another text format that records average activity data. It was introduced
by Synopsys for use in Primetime-PX for power analysis and has now been handed over
to IEEE to be converted into a standard.
See example here: $RTLSCORE_ROOT/tutorial/stimulus/cpu_10bit_pgm_hash.saif
■ SHM (Simulation History Manager)
This is a database format generated from NCSim.
■ PHY (PHYsical probe)
This is a database format from Palladium.

Joules supports all of the above stimulus formats, including both flat and hierarchical flavors
of TCF and SAIF.

Generating Stimuli from Simulation


Each HDL simulator has its own utilities to dump data dumps. Here we provide examples
using Joules tutorial files in $RTLSCORE_ROOT/tutorial directory. Examples use Cadence
IES and Verilog-XL simulators.
■ VCD Generation
A simple way to dump VCD is using calls to $dumpfile() and $dumpvars() as
shown in $RTLSCORE_ROOT/tutorial/stimulus/cpu_10bit_tb.v.
initial begin

$dumpfile(“cpu_10bit_pgm_hash.vcd”);
$dumpvars();

end

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■ FSDB Generation
Generation of FSDB requires installation of Springsoft package that contains APIs called
by simulators. These include $fsdbDumpfile() and $fsdbDumpvars(). One way to
generate FSDB is shown in $RTLSCORE_ROOT/tutorial/stimulus/cpu_10bit_tb.v.
initial begin

$fsdbDumpfile(“cpu_10bit_pgm_gcf.fsdb”);
$fsdbDumpvars(0, "cpu_10bit_tb");

end

■ TCF Generation
IES provides Tcl command called dumptcf to dump flat as well as hierarchical TCF.
echo “dumptcf –scope -internal -inctoggle -output $out_file" > ncsim.stdin
# to dump flat TCF, use option – flatformat in the line above
irun -access +rwc -coverage a -covoverwrite -input ncsim.stdin $design_files

■ SAIF Generation
IES provides Tcl command called dumpsaif to dump flat as well as hierarchical SAIF.
echo “dumpsaif –scope -internal -output $out_file" > ncsim.stdin
# to dump hierarchical SAIF, use option –hier in the line above
irun -access +rwc -coverage a -covoverwrite -input ncsim.stdin $design_files

■ SHM Generation
Refer to Reading SHM Database on page 80 for information on how to dump SHM
database.
■ PHY Generation
Refer to Reading PHY Database from Palladium on page 74 for information on how to
dump PHY database.

Assuming your environment is set to run IES’ irun simulator, a simple invocation looks like this
(see file $RTLSCORE_ROOT/tutorial/stimulus/runMe_ies.sh):
cd $RTLSCORE_ROOT/tutorial/stimulus
irun -access +rwc -coverage a -covoverwrite \
cpu_10bit_tb.v \
../cpu_10bit/cpu.v \
../cpu_10bit/fsm.v \
../cpu_10bit/datapath.v \
../cpu_10bit/alu.v \
../cpu_10bit/ram.v

For more information on using simulator and/or Springsoft FSDB package, refer to the
respective User Guides.

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Joules Frame-based Architecture


With increasing functionality on a single ASIC, it has become common to have multiple
operational modes for a design. Each mode requires specific stimuli to verify functionality, and
perform mode-specific power analysis. It is important to analyze peak and time -based power
to understand power variation across time and operational modes, and use this information
to optimize the design for power. Time intervals (or cycles) where power consumption is high,
may cause significant voltage drop and require special attention from implementation and
signoff tools.

Also, with increasing use of 3rd party IPs in today’s SOCs, it is not always possible to simulate
the system for all possible modes. While good block-level vectors may be available, it is hard
to build good system level-vectors. And, of course, runtimes for system level simulation
explode. It is important to be able to use existing block-level stimuli, apply mode-based activity
scaling, and collate them for analysis at the SOC level.

Joules’ frame-based architecture caters to the above requirements and offers the following
key capabilities:
■ Supports multiple stimuli for analysis
■ Allows definition and extraction of frames from each stimuli
■ Allows average activity and power analysis over frames of choice
■ Allows time-based activity and power profile analysis
■ Allows creation of custom frames by merging of frames and applying scaling (weights)

Stimulus in Joules is saved in a compact binary database called Stimulus DataBase (SDB).
The SDB structure looks as shown in Figure 7-1. The SDB header stores information about
the containing stimuli. Each stimulus can have multiple frames of varying sizes (by simulation
duration). The frame headers store information about the frames, such as frame start-time
and finish-time.

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Figure 7-1 SDB Header

Each stimulus and frame has an associated ID, which is used to extract information about
them. The stimulus and frame IDs follow the Unix directory naming convention: /stim#1, /
stim#2 for stimulus, and /stim#1/frame#1, /stim#2/frame#3 for frames. Each
stimulus has a hidden frame#0 that saves the average activity over all the frames in the
stimulus.

Reading Stimuli into Joules


The command to read stimulus into Joules and create SDB is read_stimulus. This
command reads the following types to stimulus files:
■ TCF
■ VCD
■ SAIF
■ FSDB
■ SDB
■ PHY
■ SHM

Refer to read_stimulus in Joules Command Reference for information on command syntax


and usage.

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Here, we discuss the command options related to extraction of frames from the stimulus, and
stuffing them into Joules SDB:
■ Extraction of fixed-sized frames
Option:interval_size <time_val>
With this option, the stimulus will be divided into frames of the specified interval size,
average activity of signals over each interval will be computed and saved in SDB. This
option, in conjunction with –start and -finish options, would determine the number
of frames extracted from the stimulus.
For example, for a stimulus of 100ns duration (start=0ns, finish=100ns),
read_stimulus –interval_size 20ns

This will extract 5 frames of 20ns each


read_stimulus –interval_size 15e-9 –start 25ns

This will extract 5 frames of 15ns each, starting at 25ns


■ Extraction of variable-sized frames
Option:-interval_list {<time_val>[:<time_val>}+
This option can be used in two ways: (i) specify a list of time markers (list of single time
values), and (ii) specify list of time pairs, one for each frame. In the first method, you can
extract variable-sized frames from a contiguous simulation time range. The second form
allows specification of time pairs for each frame. Mixing of these two forms is not allowed.
For example,
read_stimulus –interval_list 10ns 25ns 35ns 60ns

This will extract 3 frames: 10ns:25ns, 25ns:35ns, and 35ns:60ns


read_stimulus –interval_list 10ns:20ns 40ns:65ns 85ns:100e-9

This will extract 3 frames of 10ns, 25ns, and 15ns


■ Extraction of frames based on clock cycles
Option:–cycles <number_of_cycles> <signal_name>
Using this option, you can extract frames based on number of cycles of a specified signal.
A cycle is a pair of rise and fall (or fall and rise) transitions of the signal. This is intended
to be used in conjunction with repetitive signals such as a clock. If the specified signal is
a clock, the extracted frames will be of the same size. If the signal is not a clock (for
example, memory write_enable), the frame sizes will likely be different.
For example,
read_stimulus –start 20ns –cycles 10 /cpu_10bit/clock

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This will extract 20 cycle frames of /cpu_10bit/clock starting 20ns


read_stimulus –cycles 5 /cpu_10bit/ RAM_64x10/RAM_64x10/WR_ENABLE

This will extract frames containing 5 cycles of memory WR_ENABLE.


Note:
■ Options -interval_size, -interval_list, and –cycles are mutually exclusive.
If specified together, Joules will issue a warning and ignore frame-based extraction.
■ The number of frames will depend on –start and -finish options (if specified) and
interval size (fixed/variable or signal based). Last frame may not be of same size as
previous ones. Joules will issue warning in such a case.

Handling Stimulus File Contructs in Joules vs Voltus


The default mode of Joules and Voltus differs in handling some of the stimulus file constructs.
Following are two areas where Voltus differs with default mode of Joules.
■ Implicit start time in VCD
The actual simulation start time is when simulator starts dumping the value changes
including initial values. Initial values are called dumpvar section and according to VCD
LRM, if the dumpvar time is '0' then dumping time value in VCD is optional. Few
simulators dumps it while others do not. This is called implicit dumpvar time. Voltus does
not consider implicit start time but Joules does.

Case 1 Case 2
Voltus_duration = 100, Voltus_duration = 90 (it
Joules_duration = 100 starts with #10),
#0 Joules_duration = 100
$dumpvar $dumpvar
... ...
$end $end
#10 #10
... ...
#100 #100

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■ X/Z handling

Voltus has completely different algorithm for toggle count and duty cycle calculation for X
values than Joules :

Toggle count : anything to X or X to anything is considered as .5 toggle


0|1 -> X = .5 toggle
X -> 1 | 0 = .5 toggle

Duty cycle : For duty cycle calculation, X value is always considered as 0 ( which is not
consistent with toggle count algorithm )

Here are results from three scenarios and different permutation of X, 1, 0 value changes.

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Case 1 Case 2 Case 3


X as initial value X value in between the X as a last value change
(X is always value changes:
ex1 : DC = .049 (again all x
considered 0) ex1 : DC = .025 (X is is considered as 0)
ex1 : DC = .95 considered 0) #0
#0 #0 x5
x5 x5 #1033
#1033 #1033 15 T1 = 11
15 T1 = 11 15 T1 = 11 #1044
#20500 #1044 x5
ex2 : DC = 0 x5 #2000
#0 #2000 05
x5 15 T1 = 500 #2500
#1033 #2500 15 T1 = 1000
05 x5 #3500
#20500 #3500 x5
05 #20500
#20500 ex2 : DC = .025 (All X as 0)
ex2 : DC = .00536==.001 (X #0
is considered as 0)
x5
#0
#1033
x5
15 T1 = 11
#1033
#1044
15 T1 = 11
x5
#1044
#2000
x5
15 T1 = 500
#2000
#2500
05
05
#2500
#3500
x5
x5
#3500
#20500
05
#20500

To facilitate correlation studies between Joules and Voltus, Joules supports an option -
compat voltus for read_stimulus, which, when specified, enables Joules to calculate
the stimulus the way Voltus does.

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Simulation, Stimulus Read, and SDB Creation

Reading PHY Database from Palladium


The read_stimulus command is used to read a PHY database from Palladium and extract
activity for power calculation.

Following are requirements for reading PHY database in Joules:


■ UXE15.1 (Palladium XP-I and XP-II)
❑ UXE15.1.0.p48
■ UXE14.1 (Palladium XP-I and XP-II)
❑ UXE14.1.1.p99
■ VXE15.1 (Palladium Z1)
❑ VXE15.1.0.p18
■ xeDebug binary executable should be present in the path. Use the following command
to add xeDebug in the path:
set path = (/lan/cva_rel/uxe151/15.1.0.177/bin $path)

■ You must be able to do a password-less rsh on localhost. If this limitation exists in your
LSF environment, check with your local IT administrator.

If Joules is unable to invoke xeDebug, it will issue the STIM-0054 error message.

There can be several reasons for the error:


■ The PHY database has been generated from xeDebug version earlier than 15.1.0.125.
■ The PHY database is dumped using IXCOM and read back in xeDebug version prior to
15.1.0.124.

Joules issues the following error message if xe.lck file is present in the design directory.
Error : STIM-0054 [StimError] Cannot establish connection for design path
: "PHY_DB_PATH". Connection
: with XeDebug failed. Design directory is locked. Remove xe.lck and
: xeDebug.log files and restart the run.

This typically happens due to following reasons:


■ When the previous state of the design is not completed fully due to issues such as disk
space problem
■ If you ctrl C the Joules run in between a process

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In the above cases, xeDebug creates a file named xe.lck that locks the directory. Further
invocation of commands results in connection error.

To overcome this, hard kill the xeDebug session, that is,


Kill the xeDebug process and remove xe.lck xeDebug.key xeDebug.log

You can find the process ID in the xe.lck file (<user name> running on hsv-sc25
(PID=97754))

If none of the conditions is true and you are still getting the above error, contact
rtls@cadence.com.

read_stimulus Use Model for PHY Read


The following figure represents the flow for reading PHY database.

Figure 7-2 PHY Read Use Model

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Generating PHY Database from Palladium


Add the following environment variables in the PATH before dumping out the PHY database:
QTHOME=/lan/cva_rel/uxe151/15.1.0.177
IUS=/grid/avs/install/incisiv/14.2/latest/tools.lnx86
LD_LIBRARY_PATH=/lan/cva_rel/uxe151/15.1.0.177/tools.lnx86/lib/64bit
PATH=${QTHOME}/bin:${IUS}/bin:$PATH
export QTHOME IUS LD_LIBRARY_PATH PATH

There are two ways to dump PHY database from Palladium.


Note: PHY database can only be generated from a machine connected to the Palladium box.

Using ICE (In Circuit Emulation) Mode

In this mode, the design is completely synthesizable and runs entirely on the Palladium XP
emulator. For ICE mode compilation, xeCompile is used, and the runtime and debug
functionality on the emulator is handled by xeDebug. Following are the steps to generate PHY
database using ICE mode:
1. Read the input RTL and synthesizable testbench using xeDebug vavlog command.
2. Elaborate the design using vaelab command and generate a netlist.
3. Compile the design using xeCompile. The following figure highlights the steps required
for compiling the design. After the design is successfully compiled, a design database
directory is created.
4. Use the following commands (in the given sequence) to dump the PHY database:

a. debug .

b. host .

c. download

d. run (number of simulation cycles)

e. database -prepareoffline

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Figure 7-3 Dumping PHY DB using ICE Mode

Using IXCOM(Incisive Xaccelerator COMpiler) SA(Simulation Acceleration) Method

In this mode, only the synthesizable part of the design runs on the Palladium XP emulator.
Rest of the design, that is, the non-synthesizable or behavioral part of the design, runs on the
software simulator. For SA mode compilation, the SA compiler is primarily IXCOM. IXCOM
compiles RTL, gate-level netlists, and some behavioral HDL constructs into the hardware
emulator by internally invoking xeCompile, and identifies other behavioral elements and
testbenches to run with the IES software simulator, irun. Following are the steps required for
compiling the design using SA mode:
1. Compile the design using IXCOM command and generate the design database directory.
2. Use the following commands (in the given sequence) to dump the PHY database:

a. debug .

b. host .

c. xc xt0 zt0 run

d. database -open PHY_DB_NAME

e. run (Number of simulation cycles)

f. database -prepareoffline

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Figure 7-4 Dumping PHY DB using IXCOM SA Mode

read_stimulus Options to Read PHY Database


The read_stimulus command can be run in average or time-based mode while reading
out the PHY database. The existing options of read_stimulus, except -cycles, can be
used to read PHY database.

Some example are given below:


read_stimulus -file trace.phy -start 5ns -end 35ns -out 5_35_phy.sdb
read_stimulus -file trace.phy -dut_instance /dut -start 100ps -end 5000ps -out
phy_ps.sdb
read_stimulus -file trace.phy -dut_instance /dut -frame_count 10 -out phy.sdb
read_stimulus -file trace.phy -dut_instance /dut -interval_size 99ns -out phy.sdb

While reading PHY database, you can specify either the full path where PHY database exists
or the standalone PHY_DB name. If a standalone file name is passed with -file option,
then read_stimulus considers the present working directory as design directory. The
design directory where PHY_DB is present must contain all the other database-related files
that are dumped while generating the PHY database. The design directories must contain the
following directories/files:
■ PDB
■ QTDB
■ dbFiles
■ cellList
■ .design (file)

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If the design directory does not contain any of the database files/directories then Joules is not
able to connect with xeDebug and errors out.

Parallel Computing for DPA using Multiple CPUs

To improve performance of DPA, UXE uses multithreading in its DPA computation engine to
make use of multiple CPUs on a host. The core engine can detect the number of CPUs
installed on a host and decide how many CPU to use. The maximum number of CPUs to use
can be specified through the following variable:
setenv CDN_FV_MAX_THREAD <number>

For example, if you specify 8, then if a host has 8 or fewer CPUs, the core engine uses all of
them; otherwise, it uses only 8.

Generating PHY Database for Tutorial Design


setenv INSTALL_DIR /home/rtlsbld/install/trunk/2015_09_22/RTLScore
set path = ($INSTALL_DIR/bin $path)

You can use the following script for generating PHY database for tutorial design.
$INSTALL_DIR/tutorial/stimulus/runMe_palladium.sh

The script takes three arguments.


■ Design name, that is, cpu_10bit or cpu_12bit . Default is cpu_10bit.
■ Mode, that is, normal or escaped _name. Default is normal.
■ PHY compile_mode, that is, ice or ixcom. Default is ixcom.

The use model is:


1. copy $INSTALL_DIR/tutorial in your local area
2. cd to tutorial/stimulus and run the following command
./runMe_palladium.sh cpu_10bit normal ixcom

The above script generates two directories under stimulus/palladium, pgm_gcf_ixcom and
pgm_hash_ixcom, which contain PHY database directories and the corresponding PHY file.
These directories also contain the respective VCD/FSDB/TCF files dumped from Palladium.
You can cd to a specified directory and load the PHY file in Joules using read_stimulus
command.

For generating PHY database for ICE mode, use the following command:

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./runMe_palladium.sh cpu_10bit normal ice

The above script generates two directories under stimulus/palladium, pgm_gcf_ice and
pgm_hash_ice, which contain PHY database directories and the corresponding PHY file.
These directories also contain the respective VCD/FSDB/TCF files dumped from Palladium.
You can cd to a specified directory and load the PHY file in Joules using read_stimulus
command.

Limitations
■ Only the PHY database generated from xeDebug version 15.1.0.125 or later can be read
by Joules.
■ The PHY database dumped with xeDebug version 14.x will not be read in Joules. Joules
will give a connection error at startup for such PHY's.

Reading SHM Database


Joules allows reading of SHM database generated from NCSim and extract activity of power
calculation using the read_stimulus command.

Joules supports SHM version 13.20 and later but it is recommended to use the latest version,
which is 16.20.
Note: The NCSim binary executable must be present in the path. You can do so by
specifying:
set path = (/grid/avs/install/incisive/15.2/latest/tools/bin $path)

To dump SHM database, use the following dump command in NCSim stdin file.
database -open shmdb -shm -default -into <shm_output_dir>
probe -all -ports -shm -memories -depth all
irun -64 -sv -access +rwc -input shm.stdin -top <top_name> <design_files>

irun will dump a directory <shm_output_dir> with the following two files:
■ *.trn: transaction file - captures all the value changes
■ *.dsn: design hierarchy file - captures design hierarchy

For monitoring large MDAs (>4096 bits), use the option -packed <some_high_number>
with the probe command, as shown below:
probe -all -ports -shm -memories -depth all -packed <high_number>

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Specify the -file option of the read_stimulus command to read the SHM database, as
shown below:
read_stimulus -file <shm_output_dir>

If <shm_output_dir> does not have the extension of.shm, specify -format shm with
read_stimulus.
Note: You can run the read_stimulus command in average or time-based mode while
reading the SHM database.

Adding Alias Names to Stims and Frames


By default, while reading the stimuli using read_stimulus in SDB, Joules names the SDB
stims and frames as /stim#1, /stim#1/frame#1, and so on.

You can use the -alias option of read_stimulus to assign an alias name to the stimulus
that is being read.

The sample usage given below reads the activity.vcd file and assigns an alias name (/
mystim1) to the stim.

read_stimulus -file activity.vcd -alias /mystim1;

In addition, you can use the following commands to assign and retrieve alias names to stims
and frames, respectively.
■ set_sdb_alias: Can be used to assign alias names for stims and frames. After
assigning alias names to stims or frames, you can use the alias names as arguments to
all commands that accept stim ID or frame ID as argument.
Refer to set_sdb_alias in Joules Command Reference for information on command
options.
Sample usage is given below:
set_sdb_alias –stim /stim#1 –alias /mystim –frame_bname /myframe –
frame_seperator $ -frame_idx_start 10 –frame_idx_incr 5

The above command will set the following alias names for /stim#1 and its frames.
/stim#1/frame#1 /mystim/myframe$10,
/stim#1/frame#2 /mystim/myframe$15,
/stim#1/frame#3 /mystim/myframe$20 and so on...

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■ get_sdb_alias: Can be used to retrieve the alias name associated with the given stim
ID or frame ID. You can also use the command to get the stim ID (or frame ID) associated
with a given alias name.
Refer to get_sdb_alias in Joules Command Reference for information on command
options.
Sample usage is given below:
get_sdb_alias –stim /stim#1 ; returns /mystim
get_sdb_alias –frame /stim#1/frame#1; returns /mystim/mystim$10

Writing Joules SDB


The write_sdb command writes out all in-memory frames onto the disk. Refer to write_sdb
in Joules Command Reference for information on command syntax and usage.

SDB Query Utilities


Joules offers the following SDB query utilities:
■ get_sdb_stims command returns information about stimuli read into Joules SDB.
Refer to get_sdb_stims in Joules Command Reference for information on command
syntax and usage.
■ get_sdb_frames command returns information about frames present in Joules SDB.
Refer to get_sdb_frames in Joules Command Reference for information on command
syntax and usage.
■ get_stim_info command returns requested information about the stimuli present in
Joules SDB. Refer to get_stim_info in Joules Command Reference for information on
command syntax and usage.
■ get_frame_info command returns requested information about a specific frame in the
SDB. Refer to get_frame_info in Joules Command Reference for information on
command syntax and usage.
■ get_frame_duration [-frames] <frame_id> returns duration of the specified
frame. Refer to get_frame_duration in Joules Command Reference for information on
command syntax and usage.

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Using rtlstim2gate with Netlist


RTL designers and implementation engineers often see low annotation when trying to apply
RTL stimulus (simulation activity dump) on post synthesis netlist. The problem is that
simulator and synthesis tools apply different rules for RTL constructs such as: (i) generate
statements, (ii) VHDL records, SV structs, (iii) multi-dimensional arrays (MDAs), and (iv)
escaped names. Additionally, for design optimization, implementation tools may perform
design transformations such as flattening of hierarchy, design retiming (original RTL flip-flops
are renamed). These result in differences in hierarchical object names between the
simulation and synthesis databases.

Figure 7-5 RTLStim2gate Flow

For a given a stimulus, accurate power analysis requires high annotation of activity from
stimulus on registers, I/O ports, and key RTL control signals such as ICGC enables. Also,
naming changes between simulation and synthesis databases result in low annotation. To
address the name change issue, Joules offers the name mapping feature through the
rtlstim2gate command. This command, as explained below, allows you to set separate
naming rules for simulation/emulation and implementation (synthesis/P&R). The naming
rules mimic the common RTL name transformations. In addition, the command supports
name mapping file generated from Conformal equivalence checking product from Cadence.

Refer to man rtlstim2gate for information on the command options.

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rtlstim2gate Command
The rtlstim2gate command uses Joules elaborate DB as the base RTL representation,
and must be initialized (-init option) using the elaborated DB. Following initialization, you
can specify multiple rules using the -rule option. Target for the application of each rule
(simulation or synthesis) can be specified using the -target option. Following rules are
supported:
■ ungroup - Specify pattern used for ungrouping (hierarchy flattening) in synthesis.
■ reg_ext - Specify pattern used by synthesis to name registers inferred from RTL.
■ bit_slice - Specify pattern to slice the packed dimension of multi dimensional array
(MDA) nets. See example below.
■ array_slice - Specify pattern to slice unpacked dimensions of MDA nets and all
dimensions of flops. See example below.
■ hier_slice - Specify pattern for each slice of generate statement hierarchy.
■ generate - Specify pattern used to refer contents of generate statements. This applies
to both simulation and synthesis.
■ record - Specify the record/struct names.
■ flop_slice - Specify MDA expansion for flops, msb->lsb, overrides array_slice.

In Verilog and System Verilog, MDAs are declared as follows:

<type> <packed_dimension> <name> <unpacked_dimension>+ ;

For example, consider the following 3-dimensional register X_reg:

reg [0:1] X_reg [0:3] [0:2] ;

Here, dimension 1 is [0:1], dimension 2 is [0:2], dimension 3 is [0:3].

The bit_slice rule applies to dimension 1 (packed dimension), and array_slice rule,
applies to dimension 2, and dimension 3 (unpacked dimensions). An example is shown
below:

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Figure 7-6 Examples of rtlstim2gate Rules

Let us demonstrate the use of rtlstim2gate rules using the RTL snippet below. Let us assume
that the reg_ext rule used by synthesis is {%s__REGISTER%s}. Name of qout signal of
reg_w_enable module for generate bit_dx = 0 :

In Incisive it will be: cpu_10bit.DP.PC[0].flop.qout[0]

In Palladium, it will be: cpu_10bit.DP.PC_0_.flop.qout[0]

Genus will infer flop named: /cpu_10bit/DP/PC[0]/flop/qout__REGISTER [0]

To apply IES generated stimulus on Genus netlist, use the following commands:
rtlstim2gate -rule reg_ext {%s__REGISTER%s}
rtlstim2gate -rule bit_slice {[%s]}

//Hierarchy till this module: /cpu_10bit/DP


module cpu_10bit__dp(clk,rst,done, ...
<snip>
gevar bit_idx;
generate for (bit_idx = 0; bit_idx < ‘addr_width; bit_idx=bit_idx + 1)
begin : PC
reg_w_enable #(1) flop(clk,rst_reg,pc_load_en, pc_din[bit_idx],
pc[bit_idx]);
end
endgenerate
<snip>
endmodule

module reg_w_enable(clk,rst,en,din,quot);
paramter WIDTH = 8;
input clk, rst,en;
input [WIDTH-1:0] din;
output [WIDTH-1:0] quot;
reg [WIDTH-1:0] quot;
always @ (posedge clk or posedge rst)
begin
if (rst)
quot = 0;
else if (en) quot = din;
end
endmodule

To apply Palladium generated stimulus on Genus netlist, use the following commands:

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rtlstim2gate -rule reg_ext {%s__REGISTER%s}


rtlstim2gate -rule bit_slice {[%s]}
rtlstim2gate -rule bit_slice {_%d_} -target sim

Using Conformal Mapping File with rtlstim2gate


The rtlstim2gate command also accepts a Conformal mapping file as input that specifies
instance name mapping between RTL and GATE level netlist. The –golden sub-option
specifies marking of the instance names in the map file. In Conformal map file, (G) stands for
Golden, and (R) stands for Revised. If RTL is golden, the (G) entries in the map file denote
RTL names and (R) entries denote Gate netlist names. If Gate is golden, (G) entries denote
Gate netlist names and (R) entries denote RTL names.

A sample Conformal mapping file is given below:


tclmode
read_library -liberty -state -both library.lib
vpxmode
set naming style rc
set naming rule "[" "]" -array_delimiter -golden
set naming rule "%s[%d]" -instance_array
set naming rule "%s_reg" -register -golden
set naming rule "%L_%s" "%L_%d_%s" "%s" -instance
set naming rule "%L_%s" "%L_%d_%s" "%s" -variable
tclmode
read_design -golden -sv design.v -lastmod -root top -rootonly
read_design -revi -root top -rootonly mapped.gv
vpxmode
set sys m lec
set gate report -use_library_pinname
rep map po -long > mapped.rpt

Sample usage of rtlstim2gate using Conformal mapping file as input is shown below:
read_libs -lib <library list>
read_netlist <gate level netlist>
rtlstim2gate -map_file <conformal map file>
read_stimulus -file <stimulus file>

An example of the mapping file output from Conformal is shown below.


1-th mapped points:
(G) + 1 PI /clk1
(R) + 1 PI /clk1
2-th mapped points:
(G) + 3 PI /data1[0]
(R) + 3 PI /data2[0]
3-th mapped points:
(G) + 3 PI /data1[1]
(R) + 3 PI /data2[1]
4-th mapped points:
(G) + 4 PI /data1[2]
(R) + 4 PI /data2[2]
5-th mapped points:

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(G) + 5 PI /data1[3]
(R) + 5 PI /data2[3]
6-th mapped points:
(G) + 6 PI /data1[4]
(R) + 6 PI /data2[4]
7-th mapped points:
(G) + 10 PO /out1[4]
(R) + 11 PO /out2[4]
10-th mapped points:
(G) + 10 DFF /inst/out1_reg[3]
(R) + 11 DFF /foo/my_mbci/Q3N
10-th mapped points:
(G) + 10 DFF /inst/out1_reg[2]
(R) + 11 DFF /foo/my_mbci/Q2N
10-th mapped points:
(G) + 10 DFF /inst/out1_reg[1]
(R) + 11 DFF /foo/my_mbci/Q1N
10-th mapped points:
(G) + 10 DFF /inst/out1_reg[0]
(R) + 11 DFF /foo/my_mbci/Q0N

Recommended Flow
The rtlstim2gate command is intended to be used for power analysis of a synthesis (or
proto synthesis) DB or enlist and Joules’ SDB (Stimulus DB). The command must be invoked
before loading a synthesized (or proto synthesis) netlist or DB and loading the SDB.
1. Generate SDB. Following is a template script to generate SDB:
set d_lib $env(RTLSCORE_ROOT)/tutorial/libraries
set d_rtl $env(RTLSCORE_ROOT)/tutorial/cpu_10bit
set d_stim $env(RTLSCORE_ROOT)/tutorial/stimulus

set_attribute lib_search_path “.$d_lib/LIB $d_lib/LEF”


read_libs typical.lib CDK_S64x10.lib

set_attribute hdl_search_path $env(RTLSCORE_ROOT)/tutoriald_rtl /


read_hdl cpu.v fsm.v datapath.v alu.v ram.v
elaborate
write_db -all -to_file $joulesWorkDir/cpu_10bit.elab.db

read_stimulus -file $d_stim/cpu_10bit_pgm_hash.escaped_name.vcd


write_sdb -out $joulesWorkDir/cpu_10bit.rtl.sdb

2. Use rtlstim2gate on a Genus/Joules mapped DB:


rtlstim2gate -init $joulesWorkDir/cpu_10bit.elab.db
read_sdb $joulesWorkDir/cpu_10bit.mapped.db
read_stimulus -file $joulesWorkDir/cpu_10bit.rtl.sdb
Note: When a Genus/Joules mapped DB is read, rtlstim2gate automatically infers
the naming rules used for synthesis and applies them. You’ll see the following
messages:
Info: rtlstim2gate initialized ...
Info: Auto Infer: rtlstim2gate -rule ungroup {%s__SLASH__%s}

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Info: Auto Infer: rtlstim2gate -rule reg_ext {%s__REGISTER%s}


Info: Auto Infer: rtlstim2gate -rule bit_slice {[%s]}
Info: Auto Infer: rtlstim2gate -rule array_slice {_%s}
Info: Auto Infer: rtlstim2gate -rule hier_slice {[%s]}
Info: Auto Infer: rtlstim2gate -rule generate {%s__GEN__%s}
3. Use rtlstim2gate on a post-synthesis netlist:
rtlstim2gate -init $joulesWorkDir/cpu_10bit.elab.db
rtlstim2gate -rule ungroup “%s__SLASH__%s”
rtlstim2gate -rule reg_ext “%s_REGISTER%s”
rtlstim2gate -rule generate “%s_GEN_%s”

read_netlist $joulesWorkDir/cpu_10bit.netlist.v
read_stimulus -file $joulesWorkDir/cpu_10bit.rtl.sdb

For a netlist, you have to code up the appropriate rtlstim2gate rules as shown above.

Support for VHDL record and System Verilog struct


In VHDL, there are records, and in System Verilog, there are structs.

In simulation, records and structs are expanded as: <record_name>[index], while


synthesis typically names them as <record_name>_<index>. For example:
type cplx6_s_t is record
re : signed(5 downto 0);
im : signed(5 downto 0);
end record cplx6_s_t;
type cplx6_s_v is array(integer range <>) of cplx6_s_t;
signal out1 : cplx6_s_v(1 downto 0);

The stimulus will have:


out1[0].re[0],…out1[0].re[0], out1[1].re[0],…out1[1].re[5]
out1[0].im[0],…out1[0].im[0], out1[1].im[0],…out1[1].im[5]

The synthesized netlist will have:


out1_0_RE_0,… out1_0_RE_5, out1_1_RE_0,…out1_1_RE_5
out1_0_IM_0,… out1_0_IM_5, out1_1_IM_0,…out1_1_IM_5

rtlstim2gate enables identifying records/structs and applying the name conversion. For
the above example, use the following rtlstim2gate option:
rtlstim2gate -rule record "%s_%s"

VHDL objects require case-insensitive lookup. This is triggered on modules which are of type
VHDL. In the previous example, RE and re are matched if they are in VHDL.

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8
Clock Gating

This chapter discusses the following:


■ Key Clock Gating Attributes
■ Inserting Clock Gating
■ Reviewing Quality of Clock Gating
■ Generating Instrumentation for Power Control Signals
■ Identifying Clock Gate Low Activity Registers (CGLAR)

Although clock network is a small portion of the design, it contributes significantly to the
overall power dissipation of the design. Even though data in registers change infrequently,
clock signals, toggling at very high frequency and driving large capacitive loads, is a major
source of dynamic power dissipation. Effective clock-gating can result in significant power
savings.

This chapter describes the Joules commands and attributes related to clock gating and
reporting. For more information, refer to Chapter 6 in the Guide Low Power in Genus.

Key Clock Gating Attributes


■ set_attribute lp_insert_clock_gating [true|false] /

Set this attribute to true before design elaboration to achieve maximum percentage of
gated flip flops.
■ set_attribute lp_clock_gating_infer_enable [true|false] /

Set this attribute to true before design elaboration to identify additional clock gating
opportunities, even in the absence of mux feedback into the register.
■ set_attribute lp_clock_gating_min_flops <min> /

Use this attribute to specify the minimum number of flops necessary for ICGC insertion
(default = 3)

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■ set_attribute lp_clock_gating_max_flops <max> /

Use this attribute to specify the maximum number of flops that can be driven by an ICGC
(default = 32). If the number of flops exceeds <max>, additional ICGCs will be used to
satisfy the constraint.
■ set_attribute lp_clock_gating_extract_common_enable [true|false] /

Set this attribute to true to enable enhanced clock gating (ECG), where common
enables are shared across multiple registers to satisfy <min> flop constraint and
increase flip-flop clock gating percentage.
■ set_attribute lp_clock_gating_exclude [true|false] <design-hierarchy>

Set this attribute to true to disable clock gating on specified design hierarchy or a leaf
instance.
■ set_attribute lp_clock_gating_cell <cell-vdir-path> <design-hierarchy>

Use this attribute to select set of ICGC cells from the library to be used for clock gating
in the specified <design-hierarchy>. You can create a separate module to define
your own custom clock gating logic. Refer to Subsection Defining a Clock-Gating
Module in Section Controlling Selection of Clock-Gating Logic in Chapter 6 in the
Guide Low Power in Genus.
■ set_attribute lp_clock_gating_prefix <prefix>

Set this attribute to add <prefix> to all inserted ICGCs and clock nets. By default, no
prefix is added.

Inserting Clock Gating


Clock gating can be inserted either after synthesis to generic (preferred), or during global
mapping. To insert clock gating after generic synthesis, run:
synthesize –to_clock_gated

To insert clock gating during mapping, run:


synthesize –to_mapped –no_incremental

Reviewing Quality of Clock Gating


The purpose of clock gating is to save power. To check quality of clock gating in your design,
use the following commands. Both of these commands require that you have read in the input
stimuli (see Power Analysis Concepts on page 35) and run compute_power (see Clock Tree
Power Estimation on page 109). These commands are SDB frame (see Power Analysis

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Concepts on page 35) and power_mode (see Clock Tree Power Estimation on page 109)
aware.
■ get_icgc_info
This command returns information about the specified ICGC. Refer to get_icgc_info in
Joules Command Reference for information on command syntax and usage.
■ report_icgc_efficiency
This command, built on top of get_icgc_info command (above), reports the clock
gating efficiency report in a tabular form, with a line for each ICGC. Refer to
report_icgc_efficiency in Joules Command Reference for information on command
syntax and usage.
Note: The command errors out if no ICGCs are present or if no activity propagation is
done on any stimuli.
If you specify power columns, then the command reports efficiency for PDB frames, and
if PDB frames are not available, then it reports efficiency for SDB frames for non power
columns. If no power columns are specified, then the report_icgc_efficiency uses SDB
frames to calculate and report the efficiency.
A typical report looks like this:
SDB Frame: /stim#1/frame#0
En/Duty Clk/InFreq Clk/CGFreq En/Eff DwnPower Clk/Power ICGC-Instance
--------------------------------------------------------------------------------------
0.30110 4.946e+08 3.602e+08 0.27174 5.721e-05 2.931e-05 /cpu_10bit/DP/MAR_reg/...
0.25810 4.946e+08 3.441e+08 0.30435 3.947e-05 2.510e-05 /cpu_10bit/DP/MDR_reg/...
0.25810 4.946e+08 3.441e+08 0.30435 4.799e-05 2.462e-05 /cpu_10bit/DP/MDR_reg/...
0.15050 4.946e+08 3.065e+08 0.38043 2.733e-05 2.438e-05 /cpu_10bit/DP/PC_reg/...
0.15050 4.946e+08 3.065e+08 0.38043 2.760e-05 2.187e-05 /cpu_10bit/DP/IR_reg/...
0.15050 4.946e+08 3.065e+08 0.38043 2.576e-05 2.136e-05 /cpu_10bit/DP/IR_reg/...
0.10750 4.946e+08 2.903e+08 0.41304 2.400e-05 2.115e-05 /cpu_10bit/DP/ACC_reg/...
0.10750 4.946e+08 2.903e+08 0.41304 2.635e-05 2.102e-05 /cpu_10bit/DP/ACC_reg/...
--------------------------------------------------------------------------------------
SDB Frame: /stim#2/frame#0
En/Duty Clk/InFreq Clk/CGFreq En/Eff DwnPower Clk/Power ICGC-Instance
--------------------------------------------------------------------------------------
0.36140 4.984e+08 3.801e+08 0.23750 5.653e-05 3.080e-05 /cpu_10bit/DP/MAR_reg/...
0.21180 4.984e+08 3.271e+08 0.34375 2.996e-05 2.598e-05 /cpu_10bit/DP/PC_reg/...
0.25550 4.984e+08 3.474e+08 0.30312 3.796e-05 2.522e-05 /cpu_10bit/DP/MDR_reg/...
0.25550 4.984e+08 3.474e+08 0.30312 4.051e-05 2.473e-05 /cpu_10bit/DP/MDR_reg/...
0.18070 4.984e+08 3.193e+08 0.35938 2.974e-05 2.282e-05 /cpu_10bit/DP/IR_reg/...
0.18070 4.984e+08 3.193e+08 0.35938 2.696e-05 2.229e-05 /cpu_10bit/DP/IR_reg/...
0.07480 4.984e+08 2.788e+08 0.44063 2.395e-05 2.045e-05 /cpu_10bit/DP/ACC_reg/...
0.07480 4.984e+08 2.788e+08 0.44063 2.493e-05 2.032e-05 /cpu_10bit/DP/ACC_reg/...

In the report:
■ En/Duty - Probability of the enable signal.
■ Clk/InFreq - For an ICGC, Clk/InFreq is the frequency of the CK port.

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■ Clk/CGFreq - Frequency of the ECK port.


■ En/Eff - (GCK_toggles/CK_toggles). For a single stage ICGC, this is equal to enable
duty, but not so for multi-stage ICGCs. Cumulative enable efficiency of an ICGC is
computed as: 1 - (ratio of total clock toggles that ACTUALLY reach all downstream flops,
vs the total clock toggles that would have reached in absence of ICGCs).
■ DwnPower - Power dissipated by ALL downstream elements, including: self, flop, and
other downstream icgc, logic gates.
■ Clk/Power - Power dissipated by the clock network. This is the same as DwnPower,
except for endpoints (flip-flops), this includes ONLY the clock pin power (instead of power
of the entire flop).
■ report_icgc_scrub

This command tries to find the lint errors. In this case, if there are two ICGCs in sequence it
will be reported.

For example, in the following figure, G is clock gating instance. The report_icgc_scrub
command reports all ICGCs of second type (which is x) only if first ICGC is driving only ICGC
and no other instances.

Refer to report_icgc_scrub in Joules Command Reference for information on command


syntax and usage.

Figure 8-1 Reporting Sequential ICGCs

A sample report_icgc_scrub report is shown below:


------------------------------------------------------------------------------------------
|scrubber delta_gate delta_area delta_power(W) leaf_inst
------------------------------------------------------------------------------------------
1|CGDUP 1 6.50000e+00 1.31076e-07 /cpu_10bit/DP/ACC_reg/RC_CG_HIER_INST1/RC_CGIC_INST
2|CGDUP 1 6.50000e+00 1.31076e-07 /cpu_10bit/DP/ACC_reg/RC_CG_HIER_INST0/RC_CGIC_INST
------------------------------------------------------------------------------------------

The column headers are explained below:

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■ scrubber - For reporting double ICGC lint, the tool uses CGDUP as the scrubber.
■ delta_gate - In case of CGDUP, the extra ICGC/gate added is always 1.
■ delta_area - Area of the extra ICGC which can be removed.
■ delta_power - Power of the extra ICGC which can be removed.
■ leaf_inst - Leaf ICGC which can be removed.

Generating Instrumentation for Power Control Signals


As discussed earlier in the chapter, during synthesis, Joules (or Genus) inserts Clock Gating
Instances (ICGC) in the design. Statistical error due to activity propagation on these synthesis
inserted ICGC's can cause significant clock power differences for gated registers and
memories. To improve clock power accuracy for gated registers and memories it is best to
simulate activity on the enable pins of these synthesis inserted ICGCs. Joules enables this
by generating RTL expressions for ICGC enables in a side instrumentation System Verilog
(SV) file that can be added in the simulation deck. The resulting activity file (VCD, FSDB, PHY,
TCF, or SAIF) contains simulated (or emulated) activity of the enable pins of synthesis
inserted ICGCs that Joules can use for more accurate power computation.

The following figure represents the process flow.

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Figure 8-2 Instrumentation Flow

Read and Elaborate Design

synthesize -to_generic

set attribute
lp_insert_clock_gating true

synthesize -to_clock_gated

generate_joules_monitor

The generate_joules_monitor command creates a system verilog module file for the
ICGC enable signals. You need to include this file in the test_bench and simulate to create an
instrumented VCD file. For this:
1. Change the test_bench to instantiate the ICGC enable system verilog module
2. Simulate the test_bench and dump out the instrumented stimulus (VCD, FSDB, PHY,
TCF, or SAIF) file.

After dumping out the instrumented file, you can read it back in the Joules flow, as shown
below:
1. read_design and elaborate
2. synthesize -to_generic
3. set_attribute lp_insert_clock_gating true /
4. synthesize -to_clock_gated
5. read_stimulus <Instrumented_file>
6. power_map

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7. compute_power
Note: The database, if used, should be created using Joules 15.20 or higher.

Figure 8-3 Normal Flow

Stimulus Generation with NCSim


If you are using Cadence simulator NCSim for simulation, consider the following points:
■ Add the -genhier flag to your irun command. The generated verilog file made out of
module references to "generated" hierarchy. This is technically illegal in verilog and will,
by default, result in an error message, but IES has a flag to enable this behavior.
■ There are two methods to instantiate the ICGC module into the simulation environment:
❑ Include the ICGC module file in the simulation files and instantiate the module in the
testbench.
❑ Without changing existing testbench or design code, create a binding file which will
allow to instantiate the ICGC module.

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❍ Create a binding file : example bind.txt - bind <Path to DUT>


joules_monitor_signals u_joules_monitor_signals()
bind testbench.u_wrapper.u_dut joules_monitor_signals
u_joules_monitor_signals();

❍ In you irun script add "-extbind bind.txt


"irun -extbind bind.txt ..."

■ On the generate_joules_monitor command, use the -sim_top option. This will


change the path in the ICGC module file, so you do not have to modify the file.
generate_joules_mointor -sim_top testbench.u_wrapper.u_dut -out filename

Bottom-Up Flow
If you are using the Joules bottom-up flow, the ICGC monitor file should be generated on the
block that is synthesized once and instantiated multiple times.

The ICGC module could be then instantiated using the bind method given above as many
times as the module is instantiated.

For example: if u_dut is the block that has been synthesized, we generate the ICGC module
on this design using the command generate_joules_monitor -sim_top u_dut

Now, if in the top_design, u_dut module is instantiated 3 times as u_dut_1, u_dut_2 and
u_dut_3, the bind.txt file will have the following entries:
bind.txt
bind testbench.u_wrapper.u_dut_1 joules_monitor_signals
u_joules_monitor_signals();
bind testbench.u_wrapper.u_dut_2 joules_monitor_signals
u_joules_monitor_signals();
bind testbench.u_wrapper.u_dut_3 joules_monitor_signals
u_joules_monitor_signals();

The same name of the monitor module will work as the scope of each of them is different.
(testbench.u_wrapper.u_dut_1.u_joules_monitor_signals,
testbench.u_wrapper.u_dut_2.u_joules_monitor_signals, .. respectively).

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Figure 8-4 Bottom-up Flow

Identifying Clock Gate Low Activity Registers (CGLAR)


CGLAR identifies non-enabled registers in the design that have low activity. For such
registers, most of the power is consumed by the clock pin of individual flops.

Such registers can be clock gated using enables generated by XOR-ing D, and Q pins of
individual register bits. The following figure illustrates the CGLAR process on a 4-bit low
activity and non-enabled register called pst_reg.

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Figure 8-5 CGLAR Process

Figure 8-6 Clock-gating CGLAR

The scrub_cglar command in Joules identifies CGLAR opportunities in a design. It


evaluates each non-enabled, low activity register, and generates a tabular report, with a line
for each evaluated register, and a summary table with a line for each frame or stimuli used for

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CGLAR analysis. This command must be run on a post-mapped design after power has been
computed (compute_power has been run).

Refer to scrub_cglar in Joules Command Reference for information on command syntax


and usage.

Sample Usage of scrub_cglar


This section includes sample usage of the scrub_cglar command with corresponding
output.
scrub_cglar -da_threshold 0.05

Figure 8-7 Clock-gating CGLAR

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scrub_cglar -da_threshold 0.05 -summary

Figure 8-8 Clock-gating CGLAR

The options -ps_absolute and -ps_threshold are used for reporting power savings
columns.

If -bit_blast option is used, then the -ps_absolute and -ps_threshold options apply
to individual flops instead of the register bank and also the reporting now will show the flops
involved along with the bank.

A sample usage is shown below.


scrub_cglar -frame /stim#2/frame#0 -process_gated_flops -da_threshold 0.5 -
reg_list {/cpu_10bit/DP/MDR_reg/qout_reg[0:9]} -ps_absolute 5.22e-8 -bit_blast

Figure 8-9 Clock-gating CGLAR

Understanding scrub_cglar Output


The standard CGLAR output contains the following columns:
■ flops: Number of candidate low activity flops of the register
■ avg_data_freq: Average data frequency of selected low activity flops
■ +icgcs: Number of added ICGCs for CGLAR. This is dependent on these attributes:

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lp_clock_gating_min_flops and lp_clock_gating_max_flops


■ +gates: Number of added gates for CGLAR (XOR + OR gates)
■ orig_power: Total clock pin power of selected low activity flops before CGLAR gating
■ saved_power: Power savings due to CGLAR gating
■ pct_redn: (saved_power/orig_power) * 100
■ enable_freq: Frequency of ICGC enable
■ min_data_freq: Min data frequency of selected low activity flops
■ max_data_freq: Max data frequency of selected low activity flops
■ cglar_power: Total power after CGLAR gating, including XOR, OR, and ICGCs
■ saved_power: Power savings due to CGLAR gating

The CGLAR Summary output includes following columns:


■ registers: Number of candidate CGLAR registers
■ threshold: Threshold value used for CGLAR analysis
■ flops: Number of candidate CGLAR flops
■ +icgcs: Number of added ICGCs for CGLAR
■ +gates: Number of added gates for CGLAR (XOR + OR gates)
■ orig_power: Total clock pin power of selected low activity flops before CGLAR gating
■ cglar_power: Total power after CGLAR gating
■ saved_power: Total power savings
■ design_power: Total design power
■ pct_redn: (saved_power/design_power) * 100

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9
Mapping and DFT Insertion

This chapter discusses the following:


■ Reading SDC Constraints
■ Synthesis Settings
■ DFT Insertion

Joules supports all commands, options, and attributes of Genus for synthesis. This includes:
■ Reading SDC (see Chapter 6 in Genus User Guide)
■ Optimization Settings (see Chapter 7 in the Genus User Guide)
■ Synthesizing the Design (see Chapters 9 and 10 in Genus User Guide)

In addition to synthesis options of Genus, Joules supports the command power_map for fast
and accurate synthesis suitable for power analysis. Target runtime for Joules’ prototype
synthesis is 500K instances per hour, a 5x speedup over Genus medium effort synthesis. The
quality of the design (power_map vs –to_mapped) is measured using: (i) cell count, (ii) cell
drive strength profile, (iii) cell area profile, and (iv) slack (TNS and WNS) profiles. The runtime
speedup is achieved by:
■ Partitioning the design
■ Synthesizing the partitions over multiple CPUs (upto 8 CPUs)
■ Relaxing timing constraints in timing dense areas

Reading SDC Constraints


Key commands are:
■ read_sdc - Reads one or more SDC files.
Usage:
read_sdc [-stop_on_errors] [-no_compress] [-mode <mode>] <string>+
[-stop_on_errors]:stops the script when errors encountered

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[-no_compress]:turns off advanced compression


[-mode <mode>]:the timing mode
<string>+:the sdc file names to be read

■ report timing –lint - Reports useful information about the library and constraints:
❑ Technology libraries by library domain, wire-load/area modes
❑ Timing exceptions that have no effect on the design
❑ Inputs without clocked external delays, and outputs without external loads
Module :cpu_10bit
Library domain :lib_1p08v
Domain index :0
Technology libraries :slow pwr_mgmt
Operating conditions :_nominal_ (balanced_tree)
Library domain :lib_1p20v
Domain index :1
Technology libraries :typical CDK_S64x10 0.0
Operating conditions :_nominal_ (balanced_tree)
Wireload mode :enclosed
Area mode :timing library

Lint summary
Unconnected/logic driven clocks 0
Sequential data pins driven by a clock signal 0
Sequential clock pins without clock waveform 0
Sequential clock pins with multiple clock waveforms 0
Generated clocks without clock waveform 0
Generated clocks with incompatible options 0
Generated clocks with multi-master clock 0
Paths constrained with different clocks 0
Loop-breaking cells for combinational feedback 0
Nets with multiple drivers 0
Timing exceptions with no effect 1
Suspicious multi_cycle exceptions 0
Pins/ports with conflicting case constants 0
Inputs without clocked external delays 3
Outputs without clocked external delays 0
Inputs without external driver/transition 5
Outputs without external load 12
Exceptions with invalid timing start-/endpoints 0

Total: 21

Synthesis Settings
Attribute settings for clock gating are listed in CPF/1801 – Power Structures in Design on
page 57. Other synthesis settings include:
■ set_attribute optimize_merge_flops true|false /

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Set this attribute to turn on/off merging of flops during optimization.


■ set_attribute optimize_merge_latches true|false /

Set this attribute to turn on/off merging of latches during optimization.


■ set_attribute tns_opto true|false /

Set this attribute to enable/disable TNS (Total Negative Slack) optimization.


■ set_attribute power_optimization_effort low|medium|high /

Set this attribute to control the power optimization effort. Currently, power optimization
(Vt swaps, etc.) operates on leakage power reduction.

Mapping the Design


■ power_map

The power_map command performs synthesis and creates a fully functional prototype netlist
for power analysis and PPA exploration. Refer to power_map in Joules Command
Reference for information on command syntax and usage.
■ synthesize

Although synthesize –to_mapped is supported in Joules, using power_map command


along with set_attribute auto_super_thread 1 / is recommended. With this option,
Joules uses super-threading to parallelize synthesis (upto 8 CPUs), achieving significant
runtime reduction. For synthesize command, the –to_generic and –incremental
options are supported to enable DFT insertion. This release of Joules does not support the
–spatial and -to_placed options.

Refer to synthesize in Joules Command Reference for information on command syntax


and usage.

Examples showing how to configure super-threading in Joules are given above. Three
attributes are used for this purpose:
■ set_attribute super_thread_servers { {localhost | lsf | <server-name>}+ }

❑ The localhost keyword refers to the host machine. If the host machine has
multiple CPUs, use multiple localhost keywords to specify the number of CPUs
to use.
❑ The lsf keyword is used to farm jobs to a LSF queue. Use of LSF machine requires
specification of the LSF job submission command using the
super_thread_batch_command attribute (see below).

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❑ If <server-name> is specified, by default, Joules will use the Unix rsh command
to submit jobs to the specified server(s). The remote job submission command, if
different from rsh, can be specified using the attribute
super_thread_rsh_command (see below).
■ set_attribute super_thread_batch_command { bsub <option>+ }

Use of LSF machine requires specification of the LSF job submission command using
this attribute. Refer to the Unix bsub command (typically used for LSF batch job
submission) or consult your system administrator. Some key options of the bsub
command are:
❑ -n <min>[,<max>] - Min/max number of CPUs to use.
Please do not use this option.
❑ -q “<queue_name>+” - List of LSF queues to use.
❑ -R “<resource_req>” - Resource requirement for the job.
Multiple –R options can be specified.
Example:
set_attribute super_thread_batch_command \
{ bsub "type==X86_64 && mem >=40000" -q "queue1" }

■ set_attribute super_thread_rsh_command { <remote_shell_command> }

If <server-name> is specified in super_thread_servers attribute above, Joules


will, by default, use the Unix rsh command to submit jobs to the specified server(s). If
some other command is to be used, use the above-mentioned attribute to specify it.
Make sure the remote shell command does not require any interactive password.

DFT Insertion
Joules supports all commands, options, and attributes of Genus Design for Test (DFT). This
includes:
■ Setting up for DFT Rule Checking (see Chapter 4 in Genus User Guide)
■ Running and Fixing DFT Rule Checker Violations (see Chapters 5 and 6 in Genus User
Guide)
■ Controlling Mapping to Scan (see Chapters 8 and 9 in Genus User Guide)
■ Connecting the Scan Chains (see Chapter 10 in Genus User Guide)
■ Exporting the Design for Encounter Test ATPG (see Chapter 11 in Genus User Guide)

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Note: For insertion of more advanced DFT structures such as Boundary Scan, Core
wrapping, and Test Compression, additional Encounter DFT Architect license options are
required.

To generate a baseline DFT template from Joules or Genus, run the command:
■ write_template -outfile <string> -dft –split

This generates a DFT setup file and a synthesis run script. The DFT setup file includes
the basic attributes and commands to get you started.

For your reference, here are some key DFT attributes and commands that you will be using
in the flow:
■ set_attribute dft_scan_style {muxed_scan | clocked_lssd_scan} /

Defines scan style muxed scan or clocked LSSD.


■ set_attribute dft_mix_clock_edges_in_scan_chains <true|false> /

Defines whether mixing edges of Scan Flip-Flops in same scan chain is allowed.
■ set_attribute dft_dont_scan true <instance or subdesign>

Defines any Flip Flops that are excluded from scan chains

Key DFT commands for defining test control signals and scan chains are:
■ define_dft shift_enable …
■ define_dft
■ test_mode …
■ define_dft
■ test_clock …
■ define_dft scan_chain …

Key Design Rule Checking and DFT Reporting commands are:


■ check_dft_rules [-advanced]
Note: The –advanced option requires Encounter DFT Architect License.
■ check_design -multidriven
■ report dft_registers
■ report dft_setup

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Key DFT commands to map to scan Flip Flops and create the scan chains are:
■ replace_scan
■ connect_scan_chains –auto_create_chains

To write out the DFT netlist and run scripts for Encounter Test ATPG, use the command:
write_et_atpg
[-ncsim_library string [-library string]]
[-directory string]
[design]

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10
Clock Tree Power Estimation

Clock power constitutes a significant portion of the overall design power. Clock is a high
activity signal. The objective of a good clock-tree implementation is to reduce its dynamic
power. This is achieved by (i) minimizing the number of clock buffers, and (ii) reducing the total
drive strength of all clock-buffers in the clock tree. In addition, clock-tree generation needs to
satisfy the following constraints:
■ Clock skew – difference between minimum and maximum clock arrival times at any end
point fed by the clock
■ Slew degradation – maximum allowable slew degradation on the clock signal at any end
point
■ Insertion delay - maximum allowable delay from the clock root to the clock end point

To estimate the clock-tree power, Joules creates an in-memory clock tree structure. The clock
skew constraint is addressed by creating a balanced clock-tree, using similar drive-strength
clock buffers at each level. Clock insertion delay is be to determine the depth of the clock tree
(number of clock buffers from clock root to clock sink). Alternately, you can specify the clock-
tree depth. Allowable slew degradation is used to select appropriate drive-strength of leaf and
branch level clock buffers.

This chapter describes the Joules commands and options related to generating clock-tree
structure and reporting its structure and estimated power dissipation.
■ gen_clock_tree
This command generates the clock tree structure for the ideal or partially specified RTL
clock, including presence of ICGCs (post clock gating) and generated clocks.
Refer to gen_clock_tree in Joules Command Reference for information on command
syntax and usage.
■ report_clock_tree
This command reports information about the structure of the generated clock tree. Refer
to report_clock_tree in Joules Command Reference for information on command
syntax and usage

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The clock-tree summary report looks like this.


----------------------------------------------------------------------------
Total levels in the tree 6
Level Buffers/Elements(cnt)
-----------------------------------------------------------------------------
1 CLKBUFX2( 1)
2 CLKBUFX2( 3)
3 TLATNTSCAX2( 8) CLKBUFX2( 1)
4 SDFFRHQX4(22) SDFFRHQX1(12) SDFFRHQX2(3) SDFFRHQX8(5) CLKBUFX2(2)
5 CLKBUFX6( 6)
6 CDK_S64x10( 1) SDFFQX1(10) SDFFRHQX1(2) SDFFRHQX2(4)
-----------------------------------------------------------------------------
Root Branch Leaf
-----------------------------------------------------------------------------
Maximum Fanout 3 3 4
Average Fanout 3 2 2
-----------------------------------------------------------------------------
Buffers Inserted 1 6 6
Root : CLKBUFX2
Branch : CLKBUFX2
Leaf : CLKBUFX6
-----------------------------------------------------------------------------

The detailed clock-tree report looks like this.


Clock Tree Root : /CT1/clk
--------------------------------------------------------------------------
Level Libcell/Ipin Instance
--------------------------------------------------------------------------
1 CLKBUFX2/A r_1
2 CLKBUFX2/A b_2_1
3 TLATNTSCAX2/CK DP/ACC_reg/RC_CG_HIER_INST1/RC_CGIC_INST
4 SDFFRHQX4/CK DP/ACC_reg/qout_reg[9]
4 SDFFRHQX4/CK DP/ACC_reg/qout_reg[8]
4 SDFFRHQX4/CK DP/ACC_reg/qout_reg[7]
4 SDFFRHQX4/CK DP/ACC_reg/qout_reg[5]
4 SDFFRHQX4/CK DP/ACC_reg/qout_reg[6]
3 TLATNTSCAX2/CK DP/IR_reg/RC_CG_HIER_INST2/RC_CGIC_INST
4 SDFFRHQX1/CK DP/IR_reg/qout_reg[3]
4 SDFFRHQX1/CK DP/IR_reg/qout_reg[2]
4 SDFFRHQX1/CK DP/IR_reg/qout_reg[1]
4 SDFFRHQX1/CK DP/IR_reg/qout_reg[0]
4 SDFFRHQX1/CK DP/IR_reg/qout_reg[4]

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11
Activity Analysis and Reporting

This chapter discusses the following:


■ Steps for Activity Analysis and Reporting
■ Vectorless Power Analysis

Activity dumps from simulation are limited to RTL signals visible to the simulator. For example,
the RTL statement: c[3:0] = a[3:0] + b[3:0] results in a 4-bit adder in the design.
Simulation has visibility of signals a, b, and c, and can dump their activities. Activities on nets/
pins of gates implementing the 4-bit adder, required for power computation, are not available
from the simulation dumps (stimuli). They need to be derived by propagating known activities
from the inputs of the adder (signals a, and b). The process of propagating known activities
from the stimuli (also known as asserted activities), through the design is known as activity
propagation.

Two commonly-used methods for activity propagation are: (i) pseudo-random simulation
method, and (ii) statistical method. The pseudo-random method uses fixed width bit patterns
on each input pin. Random patterns that reflect the toggle frequency and duty cycle of the pin
are generated for each pin. The function of the gate is used to propagate the input bit patterns
to the output pin(s) of the gate. The statistical method uses static formulas to compute duty
and toggle of the output pins based on the duty/toggles of the input pins and the function of
the gate.

In the Cadence suite of tools, Genus uses the pseudo-random method, Voltus (and EPS)
uses the statistical method. Joules supports both methods, with the default being the
statistical method.

Steps for Activity Analysis and Reporting


After you have created Joules’ proto JDB (see Clock Gating on page 89) and SDB (see
“Simulation, Stimulus Read, and SDB Creation” on page 65), use the following sequence of
commands to do activity analysis and reporting:
■ read_db proto.jdb - Load the mapped prototype design

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■ read_stimulus –format sdb joules.sdb - Load activities from SDB. See


“Simulation, Stimulus Read, and SDB Creation” on page 65 for read_stimulus
command details.
■ propagate_activity - Propagate activity through the design
■ report_activity - Report activity. Command details are given below.
■ plot_activity_profile - Plot time-based profile of activities.
■ voltus_compare - Compare activities between Joules/Voltus. Command details are
given below.

The report_activity Command


Refer to report_activity in Joules Command Reference for information on command syntax
and usage.

This command can be used in three primary modes:


■ Hierarchy mode: This mode uses the –inst option with one or more hierarchical
instances specified. The sub-options –rtl_type and –rtl_group can be used to
select leaf level instances of the specified hierarchies. Using this, for example, you can
see the activities of all flops, or adders under a specific hierarchy. In this mode, activity
of data input pins, clock pins (if applicable), and enable pins (if applicable) are shown in
the report.
In the tutorial design, the following command will show activities of all flops under:
/cpu_10bit/FSM: report_activity –inst /cpu_10bit/FSM –rtl_type flop
# Info: Processing activity: 1/1
#----------------------+----------------------+----------------------+---------------
#Data (input pins)|Clock | Enable |
#Pins Duty Toggle |Pins Duty Toggle |Pins Duty Toggle |Inst|Instance
Type Path
#----------------------+----------------------+----------------------+---------------
1 0.427 1.430e+02 |1 0.498 4.120e+02|1 0.500 4.000e+00|flop|/cpu_10bit/FSM
pst_reg[0]
1 0.156 1.210e+02 |1 0.498 4.120e+02|1 0.500 4.000e+00|flop|/cpu_10bit/FSM
pst_reg[3]
1 0.306 1.980e+02 |1 0.498 4.120e+02|1 0.500 4.000e+00|flop|/cpu_10bit/FSM
pst_reg[1]
1 0.355 1.620e+02 |1 0.498 4.120e+02|1 0.500 4.000e+00|flop|/cpu_10bit/FSM
pst_reg[2]

Similarly, report_activity –inst /cpu_10bit/DP –rtl_group alu will show this:


# Info: Processing activity: 1/1
#----------------------+----------------------+----------------------+---------------
#Data (input pins)| Clock | Enable |
#Pins Duty Toggle |Pins Duty Toggle |Pins Duty Toggle |Inst |Instance
Type Path
#----------------------+----------------------+----------------------+---------------

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7 0.423 1.171e+01|0 0.000 0.000e+00|0 0.000 0.000e+00|add |/cpu_10bit/DP/


inc_add_41_60_1
20 0.359 1.890e+01|0 0.000 0.000e+00|0 0.000 0.000e+00|sub |/cpu_10bit/DP/
ALU/sub_61_37
20 0.359 1.890e+01|0 0.000 0.000e+00|0 0.000 0.000e+00|mult|/cpu_10bit/DP/
ALU/mul_80_37
20 0.359 1.890e+01|0 0.000 0.000e+00|0 0.000 0.000e+00|div |/cpu_10bit/DP/
ALU/div_87_37

■ Single leaf inst mode: This mode is invoked using –inst option on leaf instances. The
leaf instances can be a logic gate or an RTL macro (for example, adder, multiplier). The
report will show the activities of all input and output pins of the specified instance(s). For
example, report_activity -inst /cpu_10bit/DP/ALU/sub_61_37 will show
the following:
-----------------------------------------------------------------------------
Level Cell Pin Prob Toggle Instance Path | Driver Pin | Pin Function
-----------------------------------------------------------------------------
0 sub_unsigned /cpu_10bit/DP/ALU/sub_61_37
A[9] 0.053 2.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[9]/Q}
A[8] 0.053 2.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[8]/Q}
A[7] 0.101 4.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[7]/Q}
A[6] 0.053 2.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[6]/Q}
A[5] 0.155 4.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[5]/Q}
A[4] 0.135 4.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[4]/Q}
A[3] 0.420 8.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[3]/Q}
A[2] 0.473 8.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[2]/Q}
A[1] 0.271 6.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[1]/Q}
A[0] 0.560 8.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[0]/Q}
B[9] 0.551 2.800e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[9]/Q}
B[8] 0.377 3.600e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[8]/Q}
B[7] 0.401 3.400e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[7]/Q}
B[6] 0.372 2.800e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[6]/Q}
B[5] 0.541 4.000e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[5]/Q}
B[4] 0.459 4.200e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[4]/Q}
B[3] 0.725 2.600e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[3]/Q}
B[2] 0.565 3.200e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[2]/Q}
B[1] 0.531 3.400e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[1]/Q}
B[0] 0.391 3.000e+01 {/cpu_10bit/DP/MDR_reg/qout_reg[0]/Q}
Z[10] 0.927 1.700e+01
Z[9] 0.475 3.700e+01
Z[8] 0.582 4.500e+01
Z[7] 0.555 4.200e+01
Z[6] 0.580 3.800e+01
Z[5] 0.496 5.000e+01
Z[4] 0.512 5.200e+01
Z[3] 0.503 4.700e+01
Z[2] 0.501 4.100e+01
Z[1] 0.509 4.200e+01
Z[0] 0.519 3.700e+01

■ Path mode: View activities of instances in a path using the –by_path option. This
mode, similar to the report timing command, traces pins in specified paths, and lists the
activities on the pins. In this mode, the –from option is required. The –num_paths
option can be used to limit the number of paths shown in the report. In the Joules tutorial
design, the following command will show this:

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report_activity –by_path –from /cpu_10bit/FSM/pst_reg[3]/Q


CK 0.498 4.120e+02 /cpu_10bit/clk
D 0.156 1.210e+02 /cpu_10bit/FSM/g1177/Y
SI 0.314 7.200e+01 {/cpu_10bit/FSM/pst_reg[2]/Q}
SE 0.500 4.000e+00 /cpu_10bit/scan_en
Q 0.155 5.400e+01
1 INVX1 /cpu_10bit/FSM/g920
A 0.155 5.400e+01 {/cpu_10bit/FSM/pst_reg[3]/Q}
Y 0.845 5.400e+01 !(A)
2 NOR2X1 /cpu_10bit/FSM/g916
A 0.845 5.400e+01 /cpu_10bit/FSM/g920/Y
B 0.314 7.200e+01 {/cpu_10bit/FSM/pst_reg[2]/Q}
Y 0.106 4.800e+01 (!((A) | (B)))
3 NOR2BX1 /cpu_10bit/FSM/g909
AN 0.106 4.800e+01 /cpu_10bit/FSM/g916/Y
B 0.799 1.130e+02 /cpu_10bit/FSM/g915/Y
Y 0.024 1.000e+01 (!((!(AN)) | (B)))
4 CDK_S64x10 /cpu_10bit/RAM_64x10/RAM_64x10
ADDRESS[5] 0.430 5.200e+01 {/cpu_10bit/DP/MAR_reg/qout_reg[5]/Q}
ADDRESS[4] 0.353 4.400e+01 {/cpu_10bit/DP/MAR_reg/qout_reg[4]/Q}
ADDRESS[3] 0.565 4.800e+01 {/cpu_10bit/DP/MAR_reg/qout_reg[3]/Q}
ADDRESS[2] 0.623 4.000e+01 {/cpu_10bit/DP/MAR_reg/qout_reg[2]/Q}
ADDRESS[1] 0.527 3.800e+01 {/cpu_10bit/DP/MAR_reg/qout_reg[1]/Q}
ADDRESS[0] 0.440 3.400e+01 {/cpu_10bit/DP/MAR_reg/qout_reg[0]/Q}
DATA_IN[9] 0.053 2.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[9]/Q}
DATA_IN[8] 0.053 2.000e+00 /cpu_10bit/DP/g20/Y
DATA_IN[7] 0.101 4.000e+00 /cpu_10bit/DP/g21/Y
DATA_IN[6] 0.053 2.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[6]/Q}
DATA_IN[5] 0.155 4.000e+00 /cpu_10bit/DP/g22/Y
DATA_IN[4] 0.135 4.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[4]/Q}
DATA_IN[3] 0.420 8.000e+00 /cpu_10bit/DP/g23/Y
DATA_IN[2] 0.473 8.000e+00 /cpu_10bit/DP/g24/Y
DATA_IN[1] 0.271 6.000e+00 {/cpu_10bit/DP/ACC_reg/qout_reg[1]/Q}
DATA_IN[0] 0.560 8.000e+00 /cpu_10bit/DP/g19/Y
ENABLE 1.000 0.000e+00 /cpu_10bit/RAM_64x10/constants/1
WR_ENABLE 0.024 1.000e+01 /cpu_10bit/FSM/g909/Y
CLOCK 0.498 4.120e+02 /cpu_10bit/clk
DATA_OUT[9] 0.525 3.600e+01
DATA_OUT[8] 0.311 4.400e+01
DATA_OUT[7] 0.443 4.200e+01
DATA_OUT[6] 0.291 4.000e+01
DATA_OUT[5] 0.564 4.200e+01
DATA_OUT[4] 0.515 4.400e+01
DATA_OUT[3] 0.752 3.200e+01
DATA_OUT[2] 0.631 4.000e+01
DATA_OUT[1] 0.583 3.600e+01
DATA_OUT[0] 0.477 4.400e+01

Other Activity Related Commands


■ get_pin_activity
Refer to get_pin_activity in Joules Command Reference for information on command
syntax and usage.
■ get_inst_activity
Refer to get_inst_activity in Joules Command Reference for information on command
syntax and usage.

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Some examples of the command usage are given below:

get_inst_activity /cpu_10bit/FSM

get_inst_activity /cpu_10bit/DP/ALU/add_55_37

get_inst_activity /cpu_10bit/FSM/pst_reg[3]

The return value for the last flop example looks like this:
1:0.153:1.210e+02 1:0.498:4.120e+02 1:0.500:5.000e+00
The 1st triple: 1:0.153:1.210e+2 is for the flop data input pins. It indicates it has 1
input pin, with average duty of 0.153, and average toggle count of 121.
The 2nd triple: 1:0.498:4.120e+02 is for the flop clock pin. It indicates it has 1 clock
pin, with average duty of 0.498, and average toggle count of 412.
The 3rd triple: 1:0.500:5.000e+00 is for the flop scan enable pins. It indicates it has
1 enable pin, with average duty of 0.500, and average toggle count of 5.
■ voltus_compare
This command generates scripts and data necessary to run Voltus, extract pin activity
information, compare it with Joules’ pin activity and generate comparison plots. The list
of design pins for comparison can be selected using design hierarchy, instance types,
and pin direction and pin data types. Data generated for Voltus includes the design netlist
(Verilog), constraints (SDC), and net parasitic (SPEF). LIB and stimulus files read by
Joules for power analysis are included in the run script for Voltus to read. The Voltus run
generates data file with activity values computed by Voltus. The Voltus activity data file
is read by Joules and used to compute stats and generate comparison plots. This is a
four step process:
❑ Generate Voltus script and pin list file for comparison
❑ Generate Joules activity data
❑ Run Voltus using generated script
❑ Read Voltus data, perform comparison, and generate plots
Refer to voltus_compare in Joules Command Reference for information on command
syntax and usage

A convenient handle for all four steps is the –bname option. The generated scripts and data
files are named using the –bname handle. All scripts and data files are saved in the Voltus
work directory (./voltus_work by default). For the tutorial design, the activity comparison
plots (duty and toggle) look like this:

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Figure 11-1 Activity Comparison Plots

Vectorless Power Analysis


Often, in early stages of RTL development, designers do not have access to stimulus. In
absence of stimuli, designers can estimate block or chip power using Joules' Vectorless
power analysis method.

In Vectorless power analysis mode, Joules derives clock activity (frequency and duty cycle)
from SDC. For other pins, Joules offers commands set_default_activity, and
set_pin_activity to set pin activity. These commands provide options to set activity on
the following types of pins:
■ Primary inputs (non-clock)
■ ICGC enable pins
■ Sequential output pins
■ Black box output pins

For Vectorless mode, Joules uses special frame, /stim#0/frame#1. System default activities
are pre-populated in this frame, which can be changed using the set_default_activity
and set_pin_activity commands. Use set_default_activity command to set
default values, and the set_pin_activity command to selectively set activity on key data
and control pins.

Refer to set_default_activity and set_pin_activity in Joules Command Reference for


information on the command syntax and examples.

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The following table shows the default frequency values for various pins.

Table 11-1 Pin Types with Default Frequency Values

Pin is NOT
Pin Type No Clocks in Pin is Associated
Associated with
Design with Clock
any Clock
Primary Input 10MHz 10 % of the 1 % of the frequency
frequency of the of the fastest clock
associated clock
Flop Output 10MHz 6 % of the frequency 1 % of the frequency
of the associated of the fastest clock
clock
Latch Output 10MHz 6 % of the frequency 1 % of the frequency
of the associated of the fastest clock
clock
ICGC Output 10MHz 6 % of the frequency 1 % of the frequency
of the associated of the fastest clock
clock
ICGC Enable Driver of ICGC Driver of ICGC Driver of ICGC
enable will be enable will be used enable will be used
used to get the to get the default to get the default
default activity* activity* activity*
Black Box Output 10MHz 6 % of the frequency 6 % of the frequency
of the associated of the fastest clock
clock

* - If the driver of ICGC enable is primary input/flop output/latch output, it will get the default
values from those pin types.

The following table shows the implicit values calculated for various pins.

Table 11-2 Implicit Values for Pins

Pin Type No Clocks in Design


set/reset pins of Toggle is set to 0 and duty is set to 0/1 depending on
async/sync flops if the pin is active high/low

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Pin Type No Clocks in Design


Scan enable of Toggle is set to 0 and duty is set to 0/1 depending on
flops, clock gate if the pin is active high/low
test pin
Q complement Setting the activity of Q comp using the activity of Q
pinSetting the activity of inout mate using the activity
of inout pin
Inout mate Setting the activity of inout mate using the activity of
inout pin
Buf/inv output Setting activity of buf/inv output by propagating
annotated activity backwards through bufs/invs
Hanging pins Activity is set to (0, 0). In voltus mode activity is set as
(0.5, 0.1 * freq of fastest clock)

Priorities w.r.t pin_types


The priorities of setting the activities of pins are as follows:
1. Drivers of ICGC enables
2. All the remaining pins (flop_out, latch_out .... primary_input)

That is, if the ICGC enable is driven by primary_input or flop_out or latch_out or


memory_output then ICGC enable will get the default activity from icgc_enable.

For example:

There is an ICGC whose enable(EN) is driven by primary_input(enable). And the default


activity is set both on icgc_enable and primary_inputs as follows.
Joules> set_default_activity -pin_type icgc_enable -duty 0.4 -freq 4444
Joules> set_default_activity -pin_type primary_input -duty 0.3 -freq 3333

Then primary_input 'enable' will get the default activity 0.4 and 4444 rather than activity (0.3,
3333) as ICGC enable will get higher priority.

Priorities w.r.t stims


You can set default activity on all stims(global stim). If the default activity is set without -stim
it will be applicable to all stims. Internally the default activity is stored on /stim#0. In case if a

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specific stim does not have default activity for a pin type, it checks if it is set on global stim
and if set, it will be used.

The priority to get the activity of a pin is done as follows


1. Get the duty, abs/perc toggle from (pin type, given stim).
2. Get the duty, abs/perc toggle from (pin type, global stim).
3. Get the duty, abs/perc toggle from (global type, given stim).
4. Get the duty, abs/perc toggle from (global type, global stim).

For example if the default activities are set as follows:


Joules> set_default_activity -pin_type primary_input -duty 0.1 -freq 1111

Joules> set_default_activity -pin_type primary_input -duty 0.3 -freq 3333 -stim /


stim#1
Joules> set_default_activity -global -duty 0.4 -freq 4444

Joules> set_default_activity -global -duty 0.2 -freq 2222 -stim /stim#2

■ In stim#1, all the primary inputs get activity (0.3, 333).


■ In stim#2, all the primary inputs get activity (0.1, 1111) as it was set on global stim
■ In stim#1, all the flop outputs get activity (0.4, 4444) as it was set on global stim global
type.
■ In stim#2, all the flop outputs get activity (0.2, 2222) as it was set on stim#2, global type

In set_default_activity, always the last command wins. That is, if


set_default_activity is set for primary_inputs in /stim#1(first command) and global
stimulus(second command), than the second command activity will be used for all stims.

A sample usage scenario for vectorless power flow is given below:


1. Read library
2. Read RTL and elaborate design
3. Run power_map command
4. Vectorless setup:
Joules> set_default_activity -pin_type primary_input -duty 0.2 -freq 0.2 -clock
related
Joules> set_default_activity -pin_type icgc_enables -duty 0.1 -freq 0.1 -clock
related
Joules> set icgc [get_icgcs -root /cpu_10bit/DP/MAR_reg]

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Joules> set en_port [lindex [get_inst_pins $icgc -pin_type enable] 0]


Joules> set en_pin $icgc/$en_port
Joules> set_pin_activity -pin $en_pin -duty 0.15 -freq 50MHz -frame /stim#0/
frame#1
Joules> set_pin_activity -pin /cpu_10bit/start -duty 0.05 -freq 5.0e+6

5. Vectorless power analysis and reporting


Joules> compute_power -mode vectorless
Joules> report_power

Default Activity Calculation for Clocks


For example, there are three clocks in the design clk1, clk2, clk3.
■ If the stimulus is not read, then the sdc frequencies of clock are used to find the activity
of the clock pins.
■ If the stimulus is present, but annotated only clk1, the sdc and stim frequencies of clocks
are as follows:

Clock SDC Freq Stim Freq


clk1 1GHz 800MHz
clk2 650MHz
clk3 270MHz

Then, for clk2, stim frequency is calculated as 650 * (800/1000) = 520MHz

For clk3, stim frequency is calculated as 270 * (800/1000) = 216MHz

If the stimulus is present, but annotated only clk1, clk2. The sdc and stim frequencies of
clocks are as follows:

Clock SDC Freq Stim Freq


clk1 1GHz 800MHz
clk2 650MHz 300MHz
clk3 270MHz

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Factor for clk1 is 800/1000 = 0.8. Factor for clk2 is 300/650 = 0.46

clk3 stim frequency is calculated as 270 * (800/1000) = 216MHZ. As clk1 is the fastest clock.
However if clk1 is not annotated then we should take from the next fastest clock which is clk2.

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12
Power Analysis and Reporting

This chapter discusses the following:


■ Power Analysis Modes
■ Power Reporting
■ Power Performance Area (PPA) Reporting
■ Collating Power at SoC Level
■ Power Sweep
■ Analyzing Power Efficiency
■ Rail-based Power Analysis

Three factors that determine power of an IC design are:


■ Design and Power Structures (RTL, CPF/1801)
■ Implementation (library, SDC constraints, clock-tree DFT, physicals, etc.)
■ Stimuli through the circuit

For accurate power analysis, all of the above are equally important. The tool must take timing
into account, do proper implementation of power structures, and understand insertion of DFT
structures. And above all, the tool must be able to process multiple stimuli from simulation of
various modes, and report mode aware power analysis.

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Figure 12-1 Factors Determining IC Power

Early RTL power estimation is key to making several design and business decisions. This
includes: packaging, IP selection, technology node and foundry selection, among others. This
requires that the power estimation takes into account design components such as clock-tree,
power structures, as well as technology libraries.

Joules provides an RTL power estimation unified platform that addresses all of these
requirements.

Power Analysis Modes


Joules power analysis is CPF/1801 power mode aware (see CPF/1801 – Power Structures in
Design on page 57) and supports the following modes of power analysis:
■ Average mode - In this mode, activities of all SDB frames for each stimulus are averaged
and used to compute average power for the design for each stimulus. Average power
computation is power mode aware and is quite fast. Typical runtime, per stimulus, for a 1
million instance design per stimulus is in minutes.
■ Time-based mode - In this mode, Joules computes power for each SDB frame and keeps
the power information in memory. Time-based power computation takes more memory
and runtime. For each leaf element, Joules uses 16 bytes of memory to store activity
information (duty and toggle), and 32 bytes to store power information (leakage, internal,
and switching). So, for example, for a 1 million instance design, and 100 frames, Joules

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will require an additional (16 + 32) x 1 million x 100 bytes = 4.8 GB. Power analysis
runtime for multiple frames is sub-linear. Runtime for 100 frames is about 8-10x of the
runtime for a single frame.

The Joules command to perform power analysis is compute_power. Refer to


compute_power in Joules Command Reference for information on command syntax and
usage.

The following table shows the default toggle rates and signal probability in case of computing
power in vectorless mode:

Pin is not
Pin is associated associated with
Pin Type No clock in design
with clock any clock

Primary input / Freq = 10MHz Freq = 10 % of Freq = 1 % of


the frequency the frequency
Bbox output Duty = .5 of the of the fastest
associated clock
clock
Duty = .5
Duty = .5

Propagating Slew in Clock Tree


Joules can compute power for both RTL and netlist. For synthesis of RTL designs, the clock
and reset networks are treated as ideal. After synthesis, you can use the gen_clock_tree
command to create a model of the clock tree for power analysis. When the design is a post
CTS netlist, with clock tree present in the netlist, then instead of using the gen_clock_tree
command, use the post_cts_clock option with the compute_power command to direct
Joules to treat the clock network as non-ideal, and propagate slew before computing power.
Note:
■ If a design has Joules clock tree, then compute_power automatically applies the -
post_cts_clock option and creates CT#0 as the default clock tree, present in the
design, to calculate the clock category power.
■ The slew propagation does not happen on actual DB (present in /designs), so there is no
timing impact on DB/design loaded. The changes are applied on pseudo clock tree
created by Joules under /ctgs.

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Power Reporting
The primary command for power reporting in Joules is report_power. Refer to
report_power in Joules Command Reference for information on command syntax and
usage.

Plotting Power Profile over Time


If you have extracted multiple frames from a stimulus and run the compute_power command
in time-based mode, you can view the power profile over time using the
plot_power_profile command. The power profile plot assumes that the specified SDB
frames are contiguous in time. Refer to plot_power_profile in Joules Command Reference
for information on command syntax and usage.

Generating SHM/FSDB to View Power/Activity Profiles


The plot_power_profile command plots different power types (leakage, internal, switching
and total) over a period of time. This command can plot for various categories such as
memory, registers, and logic for different instances. The command can generate output in
gnuplot, png, fsdb and shm formats.

The following figure shows power profile for different hierarchies using the following
command:
plot_power_profile -inst /cpu_10bit/DP /cpu_10bit/FSM -format shm

Figure 12-2 Displaying Power Profile in SHM Format

The following figure shows power profile for specific categories and power types using the
following command:

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plot_power_profile -category memory register logic -types total -format shm

Figure 12-3 Displaying Power Profile for specific categories

The following figure shows both power and activity profile in a single plot.

Figure 12-4 Displaying Power Profile and activity is single plot

Use the dump_power_profile command to profile all power types on all categories for all
the sub-hierarchies for a given design instance.

The command dumps only fsdb and shm db formats. You can filter instances based on macro
types such as registers, adders, and multipliers.

The following figure shows power profile for the following command:
Dump_power_profile -format shm -inst /cpu_10bit

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Figure 12-5 Power Profile through dump_power_profile

Power Performance Area (PPA) Reporting


In Joules, you can report the power, performance, and area characteristics of key design
elements using the report_ppa command. The element include: memories, registers,
macros (such as adder, multipliers), registers, and a bucket of all other combinational logic.
Refer to report_ppa in Joules Command Reference for information on command syntax
and usage.
Note: This command is currently not SDB frame and power mode aware.

The PPA report looks like this:


----------------------------------------------------------------------------------------
Cat bits %cg Power Timing Area Instance Path
egory static dynamic delay slack cell routing
----------------------------------------------------------------------------------------
memory 1 0 1.69e-07 7.80e-04 -1 1e10 1.64e+03 0.00e+00 /cpu_10bit/RAM_64x10/
RAM_64x10
add 6 n/a 9.34e-10 1.27e-06 602.4 784.0 1.74e+01 0.00e+00 /cpu_10bit/DP/
inc_add_41_60_1
sub 10 n/a 2.59e-09 6.41e-06 2327.7 425.3 6.32e+01 0.00e+00 /cpu_10bit/DP/ALU/
sub_61_37
mult 10 n/a 1.57e-08 7.56e-05 2621.1 75.3 3.53e+02 0.00e+00 /cpu_10bit/DP/ALU/
mul_80_37
div 10 n/a 3.91e-08 1.18e-04 4959.4 6.8 7.57e+02 0.00e+00 /cpu_10bit/DP/ALU/
div_87_37
shift 10 n/a 3.40e-09 7.33e-06 709.1 98.4 7.01e+01 0.00e+00 /cpu_10bit/DP/ALU/
sll_67_28
shift 10 n/a 3.37e-09 5.83e-06 629.1 84.4 6.87e+01 0.00e+00 /cpu_10bit/DP/ALU/
srl_73_28
register 1 0 2.45e-10 4.65e-06 215.0 1317.1 7.52e+00 0.00e+00 /cpu_10bit/DFT_tpi_flop
register 1 0 2.45e-10 4.54e-06 215.0 1317.1 7.52e+00 0.00e+00 /cpu_10bit/
DFT_tpi_flop5
register 1 0 2.45e-10 4.37e-06 215.0 1317.1 7.52e+00 0.00e+00 /cpu_10bit/
DFT_tpi_flop11
register 1 0 2.45e-10 4.20e-06 215.0 1317.1 7.52e+00 0.00e+00 /cpu_10bit/

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DFT_tpi_flop17
register 1 0 2.45e-10 3.91e-06 215.0 317.1 7.52e+00 0.00e+00
/cpu_10bit/
DFT_tpi_flop23
register 1 0 2.45e-10 3.77e-06 215.0 1317.1 7.52e+00 0.00e+00 /cpu_10bit/
DFT_tpi_flop29
register 1 0 2.45e-10 3.75e-06 215.0 1316.8 7.52e+00 0.00e+00 /cpu_10bit/
DFT_tpi_flop35
register 1 0 2.45e-10 3.77e-06 215.0 1316.9 7.52e+00 0.00e+00 /cpu_10bit/
DFT_tpi_flop38
register 1 0 2.45e-10 3.75e-06 215.0 1316.6 7.52e+00 0.00e+00 /cpu_10bit/
DFT_tpi_flop41
register 1 0 2.45e-10 3.77e-06 214.2 1335.5 7.52e+00 0.00e+00 /cpu_10bit/
DFT_tpi_flop44
register 10 100 5.52e-09 3.56e-05 485.5 74.5 1.24e+02 0.00e+00 /cpu_10bit/DP/ACC_reg/
qout_reg[0:9]
register 10 100 4.23e-09 4.08e-05 284.2 1389.3 9.61e+01 0.00e+00 /cpu_10bit/DP/IR_reg/
qout_reg[0:9]
register 6 100 3.16e-09 4.76e-05 409.1 116.2 7.01e+01 0.00e+00 /cpu_10bit/DP/MAR_reg/
qout_reg[0:5]
register 10 100 5.98e-09 6.40e-05 341.4 31.3 1.26e+02 0.00e+00 /cpu_10bit/DP/MDR_reg/
qout_reg[0:9]
register 1 0 3.72e-10 4.99e-06 268.4 1348.5 8.21e+00 0.00e+00 /cpu_10bit/DP/
OVERFL_reg/qout_reg[0]
register 6 100 2.23e-09 2.15e-05 277.8 784.0 4.92e+01 0.00e+00 /cpu_10bit/DP/PC_reg/
qout_reg[0:5]
register 1 0 3.72e-10 4.87e-06 263.0 1346.1 8.21e+00 0.00e+00 /cpu_10bit/DP/ZERO_reg/
qout_reg[0]
register 4 0 2.09e-09 4.83e-05 140.0 732.4 3.97e+01 0.00e+00 /cpu_10bit/FSM/
pst_reg[0:3]
logic n/a n/a 6.30e-08 2.30e-04 n/a n/a 6.80e+02 0.00e+00 other logic
------------------------------------------------------------------------------------------

Collating Power at SoC Level


System-level simulations are expensive. Furthermore, block-level relationships result in many
scenarios and simulating all scenarios exhaustively is often infeasible. Consider, for example,
a chip with four blocks, as shown in Figure 12-6 below. When the Video block is on, the Audio
block can be off, or partially on.

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Figure 12-6 System-level Simulations in Sample Chip

System-level power verification teams often need to work with block-level stimulus. These
may come from block-level designers or IP providers. The block-level stimulus is used to
compute power for blocks, and the block power is collated to estimate power at the chip level
for different use scenarios. This is often a manual process, done using spreadsheets.

The other challenge in power verification is how to capture SoC-level activity of scenarios that
lead to peak power for grid stress testing, peak current, voltage drop, and other power signoff
analysis.

Joules provides this capability, using which you can:


■ Emulate various chip-level scenarios using block-level stimuli
■ Collate chip-level power using computed block-level power
■ Capture chip-level activity for scenarios of interest for signoff analysis

Using the collate_power command, you can:


■ Assign specific stimuli (or frames), and power_mode for each block
■ Assign stimuli (or frames), and power_mode for the root (SoC top level)
■ Compute power of the blocks with block settings and collate power at SoC level

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Refer to collate_power in Joules Command Reference for information on command syntax


and usage.

Consider the following table of stimuli available:

Audio Video Security IP


Stim #1 √
Stim #2 √
Stim #3 √ √
Stim #4 √ √
Stim #5 √ √
Stim #6 √ √ √
Stim #7 √ √ √
Stim #8 √ √ √ √

Stimulus #1 is stimulus for the Audio block, Stimulus #2 for Video, Stimulus #3 covers both
Security and IP blocks, and so on. Using Joules, you can do the following:
■ Scenario 1 - Use stim#1 for Audio, stim#2 for Video, stim#8 for the top-level and
everything other than Audio and Video blocks (include Security and IP blocks).
Joules> collate_power -reset
Joules> collate_power -set -stim /stim#1 -inst /cpu/Audio
Joules> collate_power -set -stim /stim#2 -inst /cpu/Video
Joules> collate_power -set -stim /stim#8 -inst /cpu
Joules> collate_power -report

■ Scenario 2 - Use stim#4 for Audio and Security blocks, stim#5 for Video and IP blocks.
Use stim#7 for the top-level and glue logic.
Joules> collate_power -reset
Joules> collate_power -set -stim /stim#4 -inst /cpu/Audio /cpu/Security
Joules> collate_power -set -stim /stim#5 -inst /cpu/Video /cpu/IP
Joules> collate_power -set -stim /stim#7 -inst /cpu
Joules> collate_power -report

For the tutorial design, the collate_power output looks like this:

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Power Sweep
Power dissipation of a digital IC depends heavily on operating clock frequency, rail voltage,
and to a lesser extent on the operating temperature. In the current scenario, SoCs typically
consist of several cores, each of which can run at different frequencies and voltages, and are
controlled by power structures in the design. Often, system architects want to understand the
tradeoff between frequency, voltage, and power. The following figure illustrates this.

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Figure 12-7 Sample Power Sweep Chart

The upper right (green) line shows the power vs voltage profile of the design running at
200MHz, and the lower right (blue) line shows the power vs voltage profile of the design
running at 100MHz. At VDD of 1.2v VDD, reducing the clock frequency from 200MHz to
100MHz reduces the power by 2x (from 2.0mW to ~1.0mW). Lowering the VDD to 0.9v,
reduces the power to 0.5mW, for a total of 4X power reduction. Such analysis is invaluable
early in the design stage for making key design decisions.

Such power sweep charts can be generated brute force by synthesizing the design multiple
times, once for each clock frequency, using library characterized for each rail voltage. This is
very expensive in runtime and compute resources. Joules offers an elegant solution to
explore frequency, voltage, corner vs power tradeoff that is fast and efficient, and caters to
various stages of the design - from early RTL, through synthesis, and detailed P&R. The key
tenets that enable such exploration are:
■ A design synthesized for frequency F, can run at slower frequencies without timing
violations
■ Increasing the rail voltage(s) in a design synthesized using standard cell library
characterized for rail voltage V, decreases the cell delay, and does not violate timing
(except for hold constraints)

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■ Decreasing the operating temperature in a design synthesized using standard cell library
characterized for operating temperature T, decreases the cell delay, and does not violate
timing (except for hold constraints and temperature inversion scenario)

Joules sweep_power command explores power vs clock frequency, voltage, corner tradeoff,
and works as follows -
1. Synthesize the design for fastest clock frequencies, and slowest corner (high
temperature, and lowest rail voltage).
2. Set sweep axis parameters:
❑ Frequency axis - Range of frequencies (max, min, and decrements) for each clock
of interest.
❑ Voltage axis - Range of rail voltages (min, max, and increments) for each power
domain of interest. Voltage sweep requires CPF/1801 and at least two libraries
characterized using same temperature but two rail voltages (preferably the min/max
sweep rail voltages).
❑ Temperature axis - Range of operating temperatures (max, min, and decrements)
for each library set of interest. Temperature sweep requires CPF/1801 and atleast
two libraries characterized using the same rail voltage but different temperatures
(preferably the min/max sweep temperatures).
3. Execute power sweep for the specified axis in one of two effort levels:
❑ Fast
With fast effort level, Joules uses scaling factors for each sweep axis. For the
frequency axis, the scale factor of (clock_freq/max_clock_freq) is applied to internal
and switching power on all elements of clock domain. For voltage and temperature
axis, scale factors are computed for each element category (such as memory,
register, latch, logic, clock, pm) by interpolating average power of cells used for each
of categories between two libraries characterized for different axis (voltage or
temperature) values.
❑ Accurate
With accurate effort level, for the frequency axis, Joules scales the toggle
frequencies of asserted nodes and uses activity propagation for unasserted nodes.
For the voltage and temperature axis, individual scale factors for each leaf element
are computed and used to compute power.

For syntax, supported options, and sample usage of sweep_power command refer to
sweep_power in Joules Command Reference

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sweep_power is a multi-stage command. The most commonly used options are:

The -reset option resets the sweep settings.

Use the -set option to set sweep parameters. This includes the sweep axis (-axis freq),
min/max values (-max_val, -min_val options), sweep increments (-incr option), or
number of sweep points (-points option).

Use the -handle option to specify list of sweep axis handles. For the frequency axis, handle
is clock (pin or SDC name), for the voltage and temperature axis, handle is power domain
(requires CPF/1801).

Once the sweep parameters are set, use the -plot option to plot the power profile by clock
domains (-by_clock_domain option), by design hierarchy (-by_hierarchy and -root
options), or by power domain (-by_hierarchy and -power_domain options). If multiple
stimuli have been read in, use -stims option to select the stimuli for power sweep (by default
all power sweep is performed for all stimuli).

The following figure shows the power sweep for Joules tutorial design for clock frequencies
of 500MHz to 250MHz in increments of 50MHz. The power sweep is shown for both stimuli (/
stim#1 and /stim#2), and for hierarchies /cpu_10bit/DP/ALU and /cpu_10bit/FSM. Each of the
sweep points (S6, thru S1) is a set of specific design clock frequency. The tutorial design has
a single clock, and S6 corresponds to frequency of clk = 500MHz, S5 corresponds to
frequency of clk = 450MHz, and S1 corresponds to frequency of clk = 250MHz.

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Figure 12-8 Power Sweep Graph

Analyzing Power Efficiency


This section describes a flow and a methodology to enable you explore different regions of
the design for a power efficient implementation and also identify, debug and fix wasted power.

Overview
The power efficiency methodology is based on identifying non-propagating (redundant)
switching activity flowing through the design. The non-propagating switching activity consists
of 1) clock toggles that do not change the state of a flop and 2) data and related clock toggles
that change the state of a flop but are not propagated to the output of the design. The
redundant switching activity, if removed, preserves the functionality but reduces power
consumption. It is not feasible to identify, triage and predict wasted power due to the
redundant activity manually, as a typical circuit design these days have millions of elements.
Real world applications and length of tests further makes it hard to perform the cycle accurate
analysis manually.

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Joules power efficiency solution enables you to locate instances and regions having
redundant clocking. Removing such toggles saves clock switching power in flip-flops and
clock tree elements without changing the design functionality.

The solution provides an estimate of the Ideal clock cycles in the form of a new clock
efficiency metric that analyzes data-traffic patterns in the design in a cycle-accurate manner.
In other words, it is a metric that quantifies wasted power due to the clock cycles with stable
data. It is the power that is left on the table in the current implementation. Using the metric, it
is easier to understand power inefficiency with or without the knowledge of implementation.
Joules power efficiency analysis:
■ Quantifies wasted power and reports power distribution along with the clock toggles and
efficiency.
■ Provides an estimate of the clock toggles that are redundant in the implementation
(directly correlates to the wasted clock pin switching and power).
■ Considers leaf-level clock gating and works for both gated and ungated flops.
■ Can be done both on a clock enable and individual register bank basis (explained using
the following figure).
■ Identifies and triages power inefficient instances hierarchically as well as on a leaf
instance basis. It ranks low efficiency blocks before the high efficiency blocks.
■ Can be done in a frame-based manner and also over multiple tests at the same time.

Joules’s predictability and accuracy ensures that the efficiency numbers are preserved at
RTL and gate-level stages of design.

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Figure 12-9 Ideal Clock Cycles and Efficiency Calculations

Figure 12-9 shows a design with three flop banks - QA, QB, and QC - all clocked by the same
clock signal, CK. Flop QA and QB are gated by the enable signal EN. EN stops 4 out of 10
clock cycles of CK to QA and QB. There is no enable signal for QC, hence it receives all the
10 clock cycles. A total of 22 clock cycles reach the clock pins of the flops. Only 8 out of 22
clock cycles have data changes and 14 clock cycles are wasted in the implementation. The
efficiency values are computed as a percentage of data active toggles out of total clock
toggles at the flop pins. Therefore, for QA and QB, the clocking efficiency is 50% whereas for
QC, it is only 20%. For the entire design, the clock efficiency is 36%, which means 64% (14)
of total clock cycles (22) are wasted.

The efficiency calculations can be done on per clock enable basis. An enabled clock cycle
having any data toggle in the entire sequential fanout of the clock enable is considered
efficient. In the current example, sequential fanout of the clock enable (EN) consists of flops
QA and QB. Data active clock cycles for QA and QB (4 cycles out of 6, Efficiency 66.67%)
are computed by adding the data active clock cycles of QA (3 cycles out of 6) and QB (3
cycles out of 6) and then subtracting the overlapping data active cycles (2 cycles out of 6).

Recommended Power Efficiency Flow


The power efficiency flow works by triaging the children blocks that are responsible for
causing low efficiency at the parent block. The children blocks are hierarchically sorted in the
descending order of power inefficiency so you see the most inefficient block first. The high
efficiency or high switching blocks can be seen towards the end. Using the interactive debug

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capability, the you can dive into the hierarchies to see the leaf-level instances having
inefficient clocking. In addition to efficiency numbers, the you also get an idea about which
blocks or instances are switching and how much is their contribution to the total power.

Low Clock Efficiency


■ This means the clock is not aligned well with the data toggles and is toggling without
making any change in the state of flops.
❑ It is possible in the absence as well as in the presence of combinational clock gating.
■ You should focus on finding out the reason that is causing stable data to the flops. That
reason in the form of a logical condition can be used to shut off the clock during the data
stable cycles.
❑ The reason could be simply some control signal in the data path, available in the
current cycle, but missing in the clock path; or
❑ That the upstream data flops are gated but the current flop is not.

High Clock Efficiency


■ This means that clock toggles are well aligned with data toggles.
■ You should focus on finding out if all the data toggles are observed downstream. All the
non-observed writes are redundant.
❑ You should atleast check the activity of one stage forward driven flops to see if there
is less switching there.

Zero Clock toggles (But non-zero Sequential Power)


■ This means that the data line is toggling when the clock is shut-off (in the non-reset mode
of operation).
■ It is possible both at block and instance level. At a block level, it is an opportunity for a
block-level data gating.
■ This kind of scenario can be easily identified from the power efficiency reports as they
shows the power contribution alongside the efficiency and total clock toggle numbers.
■ You should focus on finding out the reason that is causing the data to change.
❑ The reason could be that the upstream producer blocks or instances are not gated
correctly.

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High Clock Efficiency (Buses with only few bits toggling)


■ Clock efficiency could be high or even 100 percent with just one bit toggling in every clock
cycle. In such a case, clock is required in every clock cycle, so no clock cycle can be
gated.
❑ These cases can happen with large busses or where the design has some control
bits also as part of the data in a bus.
❑ Apart from efficiency, clock toggles and power contribution, the power efficiency
report also provides activity distribution of all the bits of a bus that are controlled by
the same clock and enable condition.
❑ Knowledge of few toggling bits can be beneficial for you to make alternate design
decision, such as splitting the bus.

The following figure represents the recommended power efficiency flow. As shown in the
figure, power efficiency calculations can be done on a power mapped as well as on a generic
database. It can be done with or without power calculation step, that it, compute_power.

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Figure 12-10 Power Efficiency Calculation Flow

Power Efficiency Computation Use Model


The power efficiency computation flow does not require significant changes in design setup.
The basic power computation setup (average or time-based) can be used as it is. Accuracy
requires monitoring clock waveforms along with their related data waveforms. This is
implemented on a per cycle basis for the entire design with no impact on runtime.
1. The command read_stimulus has an option, -scrub_prep, to perform cycle-based
data collection for efficiency computation. The read stimulus needs to be done on a
generic or clock-gated database. This is the only change that is needed in the setup.
Refer to read_stimulus in Joules Command Reference for information on command
syntax and usage.
2. The efficiency computation as shown in the above figure can be run on a generic as well
as on a mapped database.

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3. The compute_efficiency command needs to be run once activities have been


propagated or power has been computed. It performs the efficiency computation and has
the following options:
❑ mode: average | time_based (default is average)
❑ stims: list of stimulus ids (default is all SDB stimulus)
❑ frames: list of frame ids (default is all SDB frames)
Refer to compute_efficiency in Joules Command Reference for information on
command syntax and usage.
4. The command report_power_efficiency is the high level command to report
power efficiencies for blocks, instances, clocks, interfaces etc. Refer to
report_power_efficiency in Joules Command Reference for information on command
syntax and usage.

Some sample scripts for power efficiency calculation are given below:

Figure 12-11 Sample Script - Using Generic DB

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Figure 12-12 Sample Script - Using Power-mapped DB

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Figure 12-13 Sample Script - Using Multiple Stimulus

Power Efficiency Report


A typical power efficiency report contains the following components:

Header

The header section in the report has details of the release, date, design, command info, and
the terminology used. A sample report header is shown in the following figure.

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Figure 12-14 Sample Report Header

Hierarchical Report

Hierarchical instance report is the default mode for report_power_efficiency


command. It reports efficiency at a hierarchy level by accumulating efficiency values from all
the flops that are part of the hierarchy and its children hierarchies. It reports the following for
a hierarchy:
■ Total flop bits
■ Leaf Clock Gating %
❑ Percentage of bits gated using Synthesis
❑ Percentage of bits gated using RTL ICGCs
❑ Percentage of ungated bits
■ Total clock toggles reaching the clock pins of flops
■ Clock gating efficiency

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■ Data Aware Gating Efficiency


■ Clock efficiency
■ Hierarchy level with respect to the root instance used in report_power_efficiency
command.

A sample hierarchical report is shown in the following figure.

Figure 12-15 Sample Hierarchical Report

If power data is available (that is, compute_power has been run) and –show_power_data has
been used, then it will also report the power contribution, as shown below.

Figure 12-16 Sample Hierarchical Report

You can override the default columns by using -cols option. For example, the following report
shows only the wasted and sequential power columns out of all the power columns shown
above.

Figure 12-17 Sample Hierarchical Report

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Leaf Report

Leaf instance report is generated by using option -by_leaf at any hierarchical instance
level. It reports the following for a register bank:
■ Total flop bits
■ Clock gating % by flavor (Synth, Arch, Ungated)
■ Total clock toggles reaching the clock pins of bits
■ Clock Gating Efficiency
■ Data Aware Gating Efficiency
■ Clock Efficiency
■ Activity distribution of the bits with respect to the clock
■ Power contribution (if power data is available and asked for)

In the sample report shown below, the least efficient registers are in the beginning and most
efficient ones are towards the end.

The activity distribution for /top/blk1/q4_reg[2:0] shows the reason why its efficiency is 100%
(because 1 bit is toggling in every clock cycle).

Figure 12-18 Sample Leaf Report

Also, wasted power reported for /top/blk1/q4_reg [2:0] is 0 (because clock is needed in every
clock cycle).

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Figure 12-19 Sample Leaf Report

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Sample report_power_ efficiency Commands

Figure 12-20 Sample Leaf Report

Power Efficiency Use Cases

Same Cycle Data Stability Condition

In the following figure, register Q[5:0] has a synthesis-based clock enable ‘ready’ but is 0%
efficient (clock toggles at clock pin of Q > 0 but all the bits of Q are static). The input signal
‘cntrl’ shuts off the incoming data to the flop and is missing in the clock path.

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Figure 12-21 Use Case 1

Missing Clock Gating

In the following figure, register wdata[7:0] does not have a synthesis-based clock enable and
is reported with 0% clock efficiency (clock toggles at clock pin of wdata > 0 but all the bits of
wdata are static).

Figure 12-22 Use Case 2

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The input data ‘D’ to the flop is stable because l1, l2, and S are stable.

The register wdata[7:0] can be gated by using an enable signal derived from the stability
condition of I1, I2 and S inputs.

Figure 12-23 Sample Use Case

Unused Writes

In the following figure, the upstream register p_reg is toggling and, hence, has high clock
efficiency. None of the data toggles reaches the q_reg flop as it is completely static and has
0 clock efficiency. All of the writes to p_reg are wasted.

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Figure 12-24 Use Case 3

Known Limitations
■ Flop bits are merged together to form a register bank only if all of the following hold true:
❑ They are part of the same register variable
❑ Their parent instance is same
❑ Their clock and enable conditions are same or equivalent
This merging currently does not happen in following cases:
❑ Multi-dimensional flops (such as FIFOs) are merged using only the first dimension
❑ A flop bank that is mapped to several multi-bit flops.
■ Unlike compute_power, the compute_efficiency command does not automatically
trigger activity propagation.

Rail-based Power Analysis


A power supply network can feed the following elements in a design:
■ Power domains (using -supply {primary} option in UPF)
■ Hard macros (using connect_supply_net in UPF)
■ Primary ports (set_port_attributes in UPF)

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■ Low power cells (using -supply {default_isolation/default_retention}


option of create_power_domain)

The Joules command get_power_rails enables you to list all the supply nets
(create_supply_nets) which are being used in UPF; it does not report any unused rails.

Refer to get_power_rails in Joules Command Reference for information on command


syntax and usage.
Note: A used supply net is the one that is:
■ Part of a supply set which is referenced as primary/default_isolation/default_retention
supply handle in create_power_domain (called implicit connection).
■ Explicitly connected to pg_pin of macro (macro cells have multiple rail, only
primary_power rail cannot cater them so explicit supply connection is required to connect
all pg_pin of macro)
■ Explicitly connected to a port (primary input and output) using set_port_attributes.
You can define primary input and output to be connected to different rails; if not specified
then they are connected to primary supply of their power domain.

For example, for below UPF, only supply set SS1 will be used for domain supply, extra_supply
will not be used:
create_supply_net net1
create_supply_net net2
create_supply_set SS1 -function {power net1} -function {ground net2}
create_supply_net net3
create_supply_net net4
create_supply_set extra_supply -function {power net3 } -function {ground net4}
create_power_domain PD -supply {primary SS1} -supply {extra_supply SS2}

Therefore, get_power_rails should list net1 and net2.

If the following statement is added:


create_power_domain PD -supply {primary SS1} -supply {default_isolation SS2} -
supply {default_retention SS2}

Then get_power_rails should list supply nets from supply set SS1 as well as SS2 (net1,
net2, net3, net4)

Rail-based Reporting
When you specify report_power -power_rail <rail_name>, Joules calculates the
power (leakage, internal, switching) of <rail_name> as follows:

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■ For each power_domain where <rail_name> is part of


primary|default_isolation|default_retention supply set:
❑ If <rail_name> is part of primary supply net, it traces all the domain elements
(including low power cells as well) and computes power of pg_pin_type=rail_name
function type (mentioned in supply_set definition)
❑ If rail_name is part of default isolation supply set, it traces all the domain isolation
cells and computes power of pg_pin_type=backup_power
❑ If rail_name is part of default retention supply set, it traces all the domain retention
cell and computes power of pg_pin_type==backup_power
■ It traces all the connect_supply_net where this <rail_name> has explicit rail connection
for hard macros or IO peripherals, identifies instance and pg_pin_name from the
port_name (-ports option value), and computes pg_pin_name power of these
instances.
■ Traces all the set_port_attributes where this <rail_name> is in receiver_supply and
report their switching power under this supply.

Example:

UPF
create_supply_net ss1_power
create_supply_net ss1_ground
create_supply_net ss2_power
create_supply_net ss2_ground
create_supply_net port_net
create_supply_net port_gnd
create_suuply_set SS1 -function {power ss1_power} -function {ground ss1_ground}
create_suuply_set SS2 -function {power ss2_power} -function {ground ss2_ground}
create_power_domain PD -supply {primary SS1} -supply {isolation SS2} -supply
{retention SS2} -elements {inst1 inst2} ' There are three primary inputs and 2
primary outputs all belong to this domain
connect_supply_net ss1_power -ports {mem1/vdd1 mem2/vdd2}
create_supply_set PS -function {power port_net} -function {ground port_gnd}
set_port_attributes -receiver_supply_set PS -driver_supply_set SS2 {PI1 PI2 PO1}

get_power_rails will return:


ss1_power ss1_ground ss2_power ss2_ground port_net port_gnd

report_power -power_rail ss1_power will return:


■ power (leakage, internal, switching) of - implicit (say X)
❑ inst1 pg_type primary_power
❑ inst1 pg_type primary_power

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❑ Any low power cell in this domain (isolation retention, level shifter, switch cell)
pg_type primary_power
■ power(leakage, internal, switching) of - explicit (say Y)
❑ pg_pin vdd1 of inst mem1
❑ pg_pin vdd2 of inst mem2
■ Switching power of PI3 (note that PI1, PI2 are connected to supply net 'port_net') (say Z)
■ Switching power of PO1 (it belongs to different supply so needs to be deducted ) (say L)

Power of ss1_power rail = X+Y+Z-L

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13
Working with GUI

This chapter discusses the following:


■ Overview
■ Invoking and Exiting GUI
■ Main Window Components
■ Tab List Windows
■ Viewing Waveform Signals using SimVision
■ Running Joules Flow through GUI

Overview
Joules GUI provides the following features:
■ Interactive mode to execute Joules flow
■ Setup Wizard to implement Joules recommended flow in a step-by-step manner
■ Run Wizard to read Joules database, apply RTL stim-to-gate rules, read mapped
database and sdb files, define clock trees, and compute power for design elements
■ GUI widget to view design hierarchy as tree and to search for instances, nets and
modules
■ Interface to access HDL files
■ Interface to view and edit all attributes of design object(s)
■ Access Joules reports, plots, and debugging features through GUI menu bar

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Invoking and Exiting GUI


To start the GUI mode by default while launching Joules, type the following:
joules -gui

To start GUI while working on the Joules command prompt, type:

gui_show

To exit or hide the GUI:


■ On Joules command prompt, type quit or exit.
■ From the menu bar, select File - Exit and click:
❑ Ok in the Confirm window to close the GUI
❑ Hide GUI to hide the GUI (type the gui_show command to re-display the GUI)
■ Use the Close button at the top-right corner of the main window to close the GUI.
The difference between exit GUI command and the gui_hide command is that the
former kills the GUI application whereas the latter hides the GUI from view but does not
close the GUI process.

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Main Window Components


The following figure displays the main GUI window:

Figure 13-1 Main GUI Window

Tab List Menu Bar

Joules Flow Tabs

Menu Bar
The menu bar in the main GUI window has the following options:

File

Has the following options (in order of appearance):


■ Run Script - Use this to source and execute a Tcl script.
■ DB - Use this option and the associated sub-options to read and/or write Joules
database.
■ Preferences - Power Format - Use this option to specify the format and unit for power
reporting in Hierarchy Browser, power density treemap, and Report Power dialog.

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Changing the power format through this window also changes any power attribute values
set for a design.
■ Hide GUI - Use this option to hide the GUI; it is equivalent to specifying gui_hide
command at the Joules command prompt.
Note: To show the GUI again, type gui_show at the Joules command prompt.
■ Exit - Use this option to exit the GUI and the tool. It is equivalent to specifying Exit at
the Joules command prompt.

Stimulus

Has the following options (in order of appearance):


■ SDB - Use this option and associated sub-options to read and/or write SDB files.
■ Vectorless - Use this option and the associated sub-options, Set Default Activity and
Set Pin Activity, to apply default activity and power information for design objects in
vectorless mode. Refer to set_pin_activity and set_default_activity in Joules Command
Reference for more information.
■ Compute Power - Use this option to perform power analysis for design objects. Refer
to compute_power in Joules Command Reference for more information.

Reports

Has the following reporting options (in order of appearance):


■ Power - Use this option and associated sub-options to view reports for power, ICGC
Efficiency, PPA and low power design cells. Refer to report_power,
report_icgc_efficiency, and report_ppa in Joules Command Reference for more
information.
■ Activity - Use this option and the associated sub-options, Report Activity and SDB
Annotation, to report activity post SDB creation and the annotations on a design,
respectively. Refer to report_activity and report_sdb_annotation in Joules Command
Reference for more information.
■ Libscore - Use this option and the associated sub-options, Libs and Lib Cells, to report
information about design libraries and specified design cells, respectively. Refer to
report_libs and report_libcells in Joules Command Reference for more information.
■ Clock Tree - Use this option and the associated sub-options, Clocks and Clocktree, to
report clocks based on specified criteria and clock tree information, respectively. Refer
to report_clocks in Joules Command Reference for more information.

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Plots

Has the following report plotting options:


■ Power Profile - Use this option to view power profile for SDB frames in timed-based
mode. Refer to plot_power_profile in Joules Command Reference for more
information
■ Activity Distribution - Use this option to plot output pin activity distribution of selected
leaf instances. Refer to plot_activity_distribution in Joules Command Reference for
more information.
■ Activity Profile - Use this option to view the activity profile of specified SDB frames over
a time interval. Refer to plot_activity_profile in Joules Command Reference for more
information.
■ Net Distribution - Use this option to plot net distribution histogram for fanout, load
(capacitance), or resistance. Refer to plot_net_distribution in Joules Command
Reference for more information.
■ Inst Distribution - Use this option to plot instance distribution in a design.
■ Slack Profile - Use this option to plot slack and timing profile for the design. Refer to
plot_slack_profile in Joules Command Reference for more information.
■ Libscore - Use the following associated sub-options:
❑ Lib Quality - to plot waterfall chart of cell types and drive_strengths for a library
❑ Cell Sensitivity - to plot cell sensitivity for trend analysis using gnuplot.
❑ Drive Profile - to plot the driving strength of design cells.
Refer to plot_lib_quality, plot_cell_sensitivity and plot_drive_profile in Joules Command
Reference for more information.

Debug

Has options to compare Joules databases, libraries, and memories. These options are not
supported in the current release.

Tools

Has option to dump power or activity profiles and display the waveform data in its native
format in SimVision, a graphical waveform viewer.

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Refer to “Viewing Waveform Signals using SimVision” on page 185 for more information.

Tab List
Click the icon to open any of the following windows in a new tab:
■ Layout Viewer
■ Schematic Viewer
■ HDL Viewer
■ Hierarchy Browser
■ Object Attributes
■ Setup Wizard
■ Run Wizard

Working with these windows is explained in the section Tab List Windows on page 162.

Joules Flow Tabs


These tabs enable you to execute the recommended Joules flow steps through GUI.

Refer to Running Joules Flow through GUI on page 187 for more information

Tab List Windows


These windows are accessible by clicking the sign next to the Setup Wizard.

Layout Viewer
Use this window to view the design layout and set color, visibility and selectability preferences
for design objects.

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Figure 13-2 Layout Viewer

Click the Control button ( ) to view the design object in the Layout window. The following
figure displays a sample design in the Layout window.

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Figure 13-3 Sample Design in Layout Viewer

Floorplan editing Toolbar Icons Control Button


toolbar

Auto Query Current


Type & name of selected object cursor position
Design status

No. of objects selected Recent Actions

You can either click an individual object to select it, or select multiple objects by clicking the
first object, pressing Shift, click the last item to highlight the range, and then release Shift.

The taskbar displays the type and name of the selected object (or the first object in case of
multiple selected objects) as well as the total number of selected objects.

The following table lists the icons in the Layout window along with their functions

Toolbar Icon Function


Highlight Selected - Highlights the object(s) selected in the
display area.

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Toolbar Icon Function


Clear Highlight - Clears the highlight from those objects that
are highlighted with the current highlight set.
Clear All Highlight - Clears all highlights from the display
area.
Clear Selected - Clears highlight from the selected object in
the display area.
Zoom Selected - Enlarge the selected set of objects.
Zoom In - Display a smaller area of the design in greater
detail. Each click zooms in one level.
Zoom Out - Display a larger area of the design in less detail.
Each click zooms out one level.
Fit - Display the entire design within the design display area.
Previous - Toggle the display between previous location/
zoom level and the current location/zoom level.
Redraw - Update the display with the selected preference
settings.
Hierarchy Browser - Open the selected object in Hierarchy
Browser.
Attribute Editor- Open the Object Attributes window for the
selected object. If no object is selected, clicking this icon
opens the Object Attributes window for the design.
Deselect All - Deselect all the objects in the display area.
Auto Query - Displays, as bubble text, the cell-level
information, such as name, type, width, and height, of the
design object on which you hover the mouse pointer, as
shown in Figure 13-4 on page 130.
Additionally, the object type and name is also displayed in the
textbox adjacent to this icon (which otherwise displays the
type and name of selected object), as shown in Figure 13-4
on page 130.
Recent Actions - Displays the list of recent actions
performed on the Layout window.

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Toolbar Icon Function


Clear All Rulers - Disables all rulers set in the layout
window.
Floorplan Editing Toolbar - Has options to modify the
floorplan to optimize the design for better routability and
timing.
Refer to Features of Viewer Windows in Genus GUI Guide
for more information.

Figure 13-4 Auto Query Button Displaying Cell-level Information for Object

Right clicking an object in the Layout window opens a context-sensitive help that displays the
object type followed by these options:
■ Object Attributes - Opens the Object Attributes window for the selected object. Refer
to “Object Attributes” on page 182 for more information on this window.
■ Hierarchy Browser (for an instance) - Displays the selected object in the Hierarchy
Browser. Refer to “Hierarchy Browser” on page 174 for more information.
■ Schematic View (Cone) (for an instance) - Sub-options:
❑ In Main - Opens the instance in the Schematic View window.
❑ In New - Opens the instance in a new Schematic Cone View window.

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❑ In Append - Adds the instance to the display of an open Schematic View window.
Refer to “Schematic Viewer” on page 170 for more information on this window.

The following figure displays the selected instance, inst:rct/mul_23_26/g119, in a new


Schematic Cone View window.

Figure 13-5 Cross-probing Object to Schematic View (Cone)

■ Schematic View (Module) (for an instance) - Sub-options


❑ In Main - Opens the module associated with the selected object in the main
Schematic View window.
❑ In New - Opens the module for the selected instance in a new Schematic View
window. The following figure displays the module for selected object, inst:rct/
mul_23_26/g119, in a new Schematic View window.

Refer to “Schematic Viewer” on page 170 for more information on this window.

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Figure 13-6 Cross-probing Object to Schematic View (Module)

■ Copy Name - Copies the name of the selected object to clipboard for later use.
■ Get Coordinate - Copies the co-ordinates of the cursor to the clipboard for later use.
■ Highlight Instance Nets (for an instance) - Highlights all the nets of the selected
instance in red.
■ Dehighlight Instance Nets (for an instance) - Reverts the highlighting of the nets of the
selected instance.

Setting Color, Visibility, and Selectability for Design Objects


To set advanced color options, click the All Colors button on the control panel to open the
Color Preferences window.

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Figure 13-7 Color Preferences Window

The Color Preferences window has three tabs:


Note: The visibility settings between the tabs and the layout display area are synchronized.
That is, as soon you change any setting on any page, the corresponding changes are applied
in the main window. For example, if you change the visibility setting of blocks, the changes
are immediately applied to any blocks in the layout display area.

Objects

The Objects window includes the settings for design objects that can be viewed and
selected. The following information is displayed for each object type:
■ The current color that identifies the object in the display area. You can change the color
by clicking the Color button.
■ Whether the object type is visible in the display area.
■ Whether the object type is selectable.

Wire

The Wire window includes the visibility and selectability controls for wires in the design. You
can set the color, visibility, and selectability preferences for the listed wires as mentioned in
the previous section.

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View-Only Page

The View-Only page includes the color and selectability controls for objects that can be
displayed but not selected in the display area. You can change the settings as mentioned in
the previous section.

Schematic Viewer
The Schematic window is used to view and/or analyze the circuit. It provides a graphical view
of the circuit and is accompanied by several tools to aid in analysis.

Figure 13-8 Sample Design in Schematic Window

Gates Cluster Logic Box

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In addition to design objects, the Schematic Viewer also displays a logic box (highlighted in
the figure above) containing the cluster of all combinational and sequential gates in the
design.

When you hover the mouse over any inst or hinst in the Schematic, its name and power
numbers (leakage, internal, switching) are displayed near the cursor. For rest of the design
objects, hovering the mouse over them displays their names.

The following table lists the icons on the Schematic Toolbar and their functions:

Toolbar Icon Function


Zoom Selected - Enlarge the selected object(s) in the display
area
Zoom In - Enlarge the entire Schematic window display
Zoom Out - Reduce the entire Schematic View display
Fit - View the circuit in its initial display settings
Redraw - refresh the circuit display
Up Hierarchy - Display the object that is one level higher than the
selected object in the design hierarchy.
Deselect All - Deselect all the selected objects in the display area.
Search - Search for different object types - Instances, net, and
ports, in the Schematic window display. You can then highlight the
objects displayed in search result.
Save Image - Save the required Schematic window display as an
image file.
Print Image - Print the required Schematic window display.

Right clicking anywhere (including any object) in the Schematic View window displays the
following context-sensitive help:
■ Deselect All - Deselects all selected objects and refreshes the display
■ Grey Mode On - Turns grey mode on, which helps distinguish the highlighted items
■ Grey Mode On - Turns grey mode off

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HDL Viewer
You can access any HDL file in this window. Open a new file by clicking the icon on the
toolbar.

Figure 13-9 Sample File in HDL Viewer

Row and Column Information

The following table lists the icons on the window toolbar and their functions:

Toolbar Icon Function


Open HDL File - Open a new HDL file
Search Text - Search for a text in the open HDL file. The line
containing the searched text is highlighted.
Enable cross probe out of HDL viewer - Enable cross probing
the selected object to Object Attributes or Hierarchy Browser
window.

The section in the right displays the row and column information of the
cursor in the open file.

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Cross-Probing Objects from HDL Viewer

Select and cross-probe objects to the Object Attributes window and Hierarchy Browser by
right-clicking the object and then selecting Object Attributes or Hierarchy Browser from
the context-sensitive menu. Refer to Object Attributes on page 182 and Hierarchy Browser on
page 174 for information on these windows.

Important
Before cross-probing you need to:
❑ Set the hdl_track_filename_row_col attribute to true by typing the following
on Joules console:
set ::legacy:: set_attribute hdl_track_filename_row_col true

or
set_db hdl_track_filename_row_col true

Note: This step is also required before design elaboration.


❑ Click the Enable cross probe out of HDL viewer icon on the HDL viewer toolbar

The following figure displays cross-probing a sample object from HDL viewer to Object
Attribute window.

Figure 13-10 Cross-Probing to Object Attributes Window

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The following figure displays cross-probing a sample object from HDL viewer to Hierarchy
Browser window.

Figure 13-11 Cross-Probing to Hierarchy Browser Window

Hierarchy Browser
The Hierarchy Browser window displays the design hierarchy, including all its objects, as a
tree view. You can click the + sign next to an object type to view its details. The Hierarchy
Browser also displays power numbers (Leakage, Internal, Switching, Total, and Percentage)
after power has been computed for the design.

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Figure 13-12 Sample Hierarchy in Hierarchy Browser

The following table lists the icons on the window toolbar and their functions:

Toolbar Icon/
Function
Button
Previous page - Moves to the previous page in the hierarchy
browser.
Next page - Moves to the next page in the hierarchy browser.
Top Page - Displays the first page of the hierarchy browser.
Enable Sorting for current page - Allows you to sort the
displayed objects.
Sort based on alphabetical order/cell count - Allows you to
sort the objects based on increasing or decreasing alphabet order.
The Enable Sorting for current page option needs to be enabled
before using this button.
Compact - Click this button to view only hierarchical and leaf
instances.

When you right-click an object in the Hierarchy Browser window, the context-sensitive help
displays the options shown in the following figure.

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Figure 13-13 Displaying Context-sensitive Menu from Hierarchy Browser

The context-sensitive menu options are explained below.


■ Top Page - Displays the first page of the hierarchy browser.
■ Previous page (if applicable) - Moves to the previous page in the hierarchy browser.
This is equivalent to clicking the button on the browser toolbar.
■ Next page (if applicable) - Moves to the next page in the hierarchy browser. This is
equivalent to clicking the button in the browser toolbar.
■ HDL Viewer
❑ In Main - Opens the selected object in the main HDL Viewer window.
❑ In New - Opens the selected object in a new HDL Viewer window. The following
figure displays a sample selected object in a new HDL Viewer window.

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Figure 13-14 Cross-Probing to HDL Viewer

■ Object Attributes - Displays the Object Attributes window for the selected object.
Refer to Object Attributes on page 182 for more information on this window.
The following figure displays a sample selected object in Object Attributes window.

Figure 13-15 Cross-Probing to Object Attributes Window

■ Copy Name - Copies the name of the object to clipboard for later use.

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■ Power No.s - Reports power numbers for the selected object, as shown in the following
figure.

Figure 13-16 Power No.s for Selected Instance

■ Report Power - This additional option for modules opens the Report Power form where
you can select various options for reporting power, as shown in the following figure.

Figure 13-17 Report Power Options for Selected Instance

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■ Open Power Density Treemap- This option, visible for hierarchical instances or design
top, generates the power density treemap for the selected object.
Power density treemap is an interface to visually depict design hierarchy, with area being
the basis to decide the size of the rectangle representing an instance of the design.
Additionally, various Power densities are used as the criteria color the rectangles.
A sample power density treemap window, with its components, is shown in the following
figure.

Figure 13-18 Power Density for Selected Instance

Configuration Toolbar

Treemap
Canvas

Hovering the mouse pointer over an instance in the treemap canvas displays a tooltip
including leakage power, internal power, switching power, area, and total power density for
that instance.

The main components of the treemap window are:


■ Treemap canvas

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This is the area where treemap for the selected instance is drawn. By default, the tool
draws 1 level (configurable) deep in the hierarchy from the selected hierarchy level.
Macros are always visible in the treemap. If the macro is deeper than the visible level, it
is shown by dotted lines. You can traverse down in the hierarchy exploring deeper levels.
All the leaf instance are clubbed together in a box called "<Parent's Name> Leaf Insts".
Right-clicking on an instance on the treemap displays the context-sensitive menu with
following options:
❑ Step Into - Dives into the selected hierarchical instance and shows further 'n' levels
of this hierarchical instance in the Tree map, where n is the hierarchy levels selected
in the toolbar. Can also be achieved by double clicking rectangle (instance) of
interest.
❑ Step Out to Root - Come out of the current hierarchical instance's perspective to
root's perspective.
❑ Step Out One Level - Come out of the current hierarchical instance's perspective
to a level up in the design hierarchy.
❑ Open in - Displays options to cross probe the selected instance in Hierarchy
Browser, HDL Viewer, and Object Attributes window.
❑ Zoom In - Zooms in the canvas by one unit.
❑ Zoom Out - Zooms out the canvas by one unit.
■ Configuration toolbar
This toolbar contains the following options.

Option Function
Visible Hierarchy Levels - define the number of
levels down from the current hierarchical level to be
drawn on the treemap.
Coloring Criterion - define different color scheme
for different power components such as Leakage
Power Density and Total Power Density by selecting
the components from this dropdown.

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Option Function
Configure the power range and the associated color
scheme for the treemap using this option. There are
three color boxes through which you can set the
colors, as follows:
■ If the power density percentage in the treemap is
less than the first entry box value, use the color in
colorbox1.
■ If the power density percentage is between the
first and second entry box values, use the color in
colorbox2.
■ If the power density percentage is more than the
second entry box value, use the color set in the
colorbox3.
Display the power range as relative percentage of
power density for the selected instance. This option is
selected by default.
You can deselect this option, select the power unit,
and specify absolute power values in the power
range fields.
Let us consider that the instance under consideration
has 'PD' power density. 'PDmax' and 'PDmin' are the
maximum and minimum power density across all the
instances through all the levels down from the top
instance (for which Power Density treemap is
originally drawn), respectively. Then, relative
percentage of power density for instance under
consideration will be:
PDrel = (PD - PDmin) / (PDmax - PDmin) * 100

In the example above, all the instances with relative


Total power density less than 33% are green, 33.33%
to 66.67% are mustard and more 66.67% are red.
Clicking this button applies the changes done to any
of the options in the Treemap configuration toolbar.

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Option Function
Clicking this button moves you out of the current
hierarchical instance's perspective to a level up in the
design hierarchy. This is equivalent to selecting Step
Out One Level from the context-sensitive menu for
the instance.
Clicking this button moves you out of the current
hierarchical instance's perspective to root's
perspective. This is equivalent to selecting Step Out
to Root from the context-sensitive menu for the
instance.
Using this Zoom bar, you can zoom in or zoom out of
the canvas. You can alternatively select Zoom In or
Zoom Out from the context-sensitive menu for the
instance.
Selecting this option allows you to use gradient colors
as color scheme for the treemap.

Object Attributes
The Objects Attributes window displays all attributes, along with their values, for the
selected object.

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Figure 13-19 Sample Object Attributes Window

Apply new value to all occurrences


Object Type Display by attribute category of selected attribute

Calculate count of selected attribute


Represents editable attribute

You can search for a specific attribute type by selecting the appropriate category from the
Category drop-down list. For example, the following figure shows a sample list of attributes
when you select netlist from the Category drop-down list.

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Figure 13-20 Searching for Object Category

Use the icon to dive into the objects listed in the Value column and display their Attributes.
by clicking the Calculate button. The value of the attribute is displayed in the Nr column. For
example, if you click the Calculate button against the Pin attribute type, Joules will calculate
the total count of pins in the design, show the number in the Nr column, and show all pin
values in the Value column.

For attributes that have only the Calculate button against them, you can compute their value
by clicking the Calculate button. For example, you can calculate the design yield probability
by clicking the Calculate button against the Yield attribute.

Attributes whose values can be edited have the icon against them. You can edit the value
for such attributes in either of the two ways:
■ To edit the value of each attribute separately, click on the value against the attribute and
select another value from the drop-down list/enter a new value.
■ To edit the value of all occurrences of an attribute in one go, select the Common
checkbox on the window toolbar, as shown in the following figure. Now when you enter/
select a new value for the attribute and click the Update button (at the bottom), it is
applied to all occurrences of that attribute.

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Figure 13-21 Editing Object Attributes

Setup Wizard
This displays the Setup Wizard that contains various tabs for executing different Joules flow
steps. Refer to Running Joules Flow through GUI on page 187 for more information on how
to use the Setup Wizard.

Run Wizard
Once the setup is complete using the Setup Wizard, you can execute the run part of Joules
power flow using this option. Refer to Run on page 195 for information on the steps involved.

Viewing Waveform Signals using SimVision


Using Joules GUI, you can dump power or activity profiles and view the waveform data in its
native format in SimVision, a graphical waveform viewer.

Selecting Tools - SimVision - Load Waveforms from the main menu displays the dialog,
as shown below, where you can select the profile, activity profile or power profile, that you
want to view in SimVision.

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Figure 13-22 SimVision Dialog

Select the profile and enter other options such as stim ID and design root, and click OK. The
tool executes the dump_power_profile or dump_activity_profile command,
launches Simvision, as shown below. , and displays the waveform data in its default window.

Figure 13-23 SimVision window

When you select the component and type of data for which you want to view the waveform
from Design Browser, the right pane of the SimVision window displays the data in waveform
format. For example, in the following figure, the SimVision window displays waveform data for

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leakage power and switching power for the selected component, each represented by
different cursors.

Figure 13-24 Sample Waveform Data in SimVision window

Running Joules Flow through GUI


The Setup Wizard tab mimics the setup section for Joules recommended power flow in a step-
by-step manner. This wizard includes six tabs, all of which are explained in this section.

Library
This step includes reading of libraries, LEF, capacitance table/QRCTech, MMMC script files,
and mapping timing/power libraries.

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Figure 13-25 Library Tab of Setup Wizard

Various sections in this window are:

Library

Reads libraries in multiple domains. If no domain is specified, the default domain library is
read. Click Add to add the selected libraries to read cache; a list pops up showing all read
and cached libraries along with the domain. All the cached libraries are in a pending read
state and are read when this step is complete, that is, when you click the Next button.

Refer to read_libs in Joules Command Reference for more information.

Map Library Domain

Specify the name of the library domain with which the libraries to be used for timing and power
analysis are associated (mapped). Mapping is done at completion of the step, that is, when
you click the Next button.

This is equivalent to setting the power_library attribute by specifying:

set_db power_library

Refer to power_library in Genus Attribute Reference for more information.

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LEF

Reads LEF files. The order of files to be read is important. The files are read at completion of
step, that is, when you click the Next button.

This is equivalent to setting the lef_library attribute by specifying:

set_db lef_library

Refer to lef_library in Genus Attribute Reference for more information.

Capacitance Table

Reads capacitance tables. If QRC Tech files are also read, then these files will be ignored.
The files are read at completion of step, that is, when you click the Next button.

This is equivalent to setting the cap_table_file attribute by specifying:

set_db cap_table_file

Refer to cap_table_file in Genus Attribute Reference for more information.

QRCTech

Reads QRC Tech files. The files are read at completion of step, that is, when you click the
Next button.

Refer to read_qrc in Genus Command Reference for more information.

Multi Mode Multi Corner

Reads MMMC script files. The files are read at completion of step, that is, when you click the
Next button.

Refer to read_mmmc in Genus Command Reference for more information.

Design
This step reads design files (RTL/Netlist/DB), design constraints, and power intent files.

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Figure 13-26 Design Tab of Setup Wizard

Various sections in this window are:

Design

Reads design files as RTL, netlist, or previously dumped DB. After selecting the files, click
Add to read them into Joules. You need to repeat this step to read multiple files. You can also
specify an input HDL file by selecting the HDL File Path option. The selected files which are
not added are read on the step completion.

Refer to read_hdl and read_netlist in Joules Command Reference for more information.

Power Intent

Reads power intent from CPF/UPF files. The files are read at completion of the step.

Refer to read_power_intent in Joules Command Reference for more information.

Elaborate
This step sets pre-elaborate attributes for power constraints, elaborates design, applies and
commits power intent post elaboration.

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Figure 13-27 Elaborate Tab of Setup Wizard

Various sections in this window are:

Power Constraints

Set these flags before elaboration as recommended by Joules Power Flow. Attributes are set/
unset on elaboration or step completion.

This is equivalent to setting the lp_insert_clock_gating and lp_infer_enables


attributes by specifying:

set_db lp_insert_clock_gating

or

set_db lp_infer_enables

Refer to these attributes in Genus Attribute Reference for more information.

Elaborate

Elaborates the design. Select the design top to be elaborated and the file to dump the
elaborated DB.

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Selecting the Enable Cross Probing to HDL checkbox tracks the file name, row and column
information which is used to cross probe to HDL file viewer from other GUI widgets. This is
equivalent to setting the hdl_track_filename_row_col attribute by specifying:

set_db hdl_track_filename_row_col

Refer to elaborate in Joules Command Reference and hdl_track_filename_row_col


in Genus Attribute Reference for more information.

Power Intent

Applies and commits previously read power intent (CPF/UPF) file.

Refer to read_power_intent in Joules Command Reference for more information.

Stimulus
This step reads stimulus.

Figure 13-28 Stimulus Tab of Setup Wizard

Stimulus files are read along with other constraints only when you click the Load button.
Select the Write SDB as option to dump the SDB file after stimulus is read.

Refer to read_stimulus in Joules Command Reference for more information.

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Pre Synth
This step applies extra settings before synthesis/power map is implemented.
Note: The options in this tab are valid only when a Post Layout netlist is read, and are hidden
in RTL flow.

Figure 13-29 Pre Synth Tab of Setup Wizard

All the files/settings are applied upon step completion, that is, on clicking the Next button.
Various sections in this window are:

Physical

Reads physical information from DEF files with relevant options. The files are read at
completion of the step.

Refer to read_def in Genus Command Reference for more information.

Parasitics

Reads parasitic information from SPEF files with relevant options. You can also adjust the
scaling for capacitance and resistance. The information is read at completion of the step.

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Refer to read_spef in Joules Command Reference and


scale_of_cap_per_unit_length/ scale_of_res_per_unit_length attribute in
Genus Attribute Reference for more information.

MBCI

Applies multibit cell inferencing settings for the design. The settings are applied at completion
of the step. This is equivalent to setting the _*multibit* attributes. Refer to these
attributes in the Genus Attributes Reference for more information.

Clock Gating

Applies clock gating settings for the design. The settings are applied at completion of the step.

This is equivalent to setting the lp_clock_gating_* attributes. Refer to these attributes


in the Genus Attributes Reference for more information.

Power Map
This step applies settings for DFT and power map.

Figure 13-30 Power Map Tab of Setup Wizard

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Various sections in this window are:

DFT

Reads DFT files. You can also source the selected files and save database after sourcing a
DFT script.

Refer to Genus Design for Test Guide for more information.

Power Map

Performs power map with the selected options, which is implemented when you click the
Power Map button. You can also save the mapped DB using the Save DB as option.

Refer to power_map in Joules Command Reference for more information.

Run
Once the setup is complete and DB(s) have been dumped, you can move to the Run Wizard
to execute the flow with all the applied settings. This can be done by clicking Run button in
the Power Map tab window of the Setup Wizard or by selecting the Run tab from tab list (the
icon).

Like Setup Wizard, the Run wizard is also a step-by-step mimic of the run part in the Joules
recommended power flow.

Step1: Initialize

This step initializes and sets up RTL stim-to-gate settings. Tasks involved:
1. Read the elaborated DB.
2. Provide the conformal map file containing rules or add the rules one by one in the Rules
section.

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Figure 13-31 Step1 of Run Wizard

Refer to rtlstim2gate in Joules Command Reference for more information.

Step 2: DB and SDB

Tasks involved:
1. After reading elaborated DB and applying rules to RTLStim2Gate, read mapped DB as
netlist or DB.
If you are reading the mapped DB as netlist, read the relevant SDC files in the Design
Constraints sub section.
2. Read dumped SDB file from Setup Wizard or read stimulus as described in Setup wizard.
Note: There is no indication of action completed for the step.

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Figure 13-32 Step2 of Run Wizard

Step 3: Compute Power

This step generates clock trees, estimates data buffers, and finally computes power for further
analysis.

Figure 13-33 Step3 of Run Wizard

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Steps involved:
1. Generate clock trees. Max skew/sink slew/insertion delay have a unit as frac which
implies the value entered would be considered as a fraction and not absolute.
Refer to gen_clock_tree in Joules Command Reference for more information.
2. Select maximum fanout and estimate data buffers. The report is displayed on Joules
console.
Refer to estimate_data_buffers in Joules Command Reference for more information.
3. Select the appropriate power mode, scale factor, and auto tune settings, and compute
power for the design by clicking the Power Map button.
Refer to compute_power in Joules Command Reference for more information.

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14
Accessing Reports through Joules Smart
Tables

This chapter discusses the following:


■ Introduction
■ Widget Components
■ Plotting Data in GUI Widget
■ Cross-probing from Widget Window

Introduction
Joules has the ability to show output reports in form of interactive GUI widget for the following
commands:
■ cdn_table
■ collate_power -report
■ report_clocks
■ report_icgc_effeciency
■ report_libcells
■ report_libs
■ report_net_switching
■ report_power [-by_hier/-by_leaf_instance/-by_category/-
by_function_type]
■ report_ppa
■ report_sdb_annotation

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The GUI widget shows data in a dynamically sortable table that also supports filtering and
plotting of the data based on specified criteria.

To display output in GUI widget for a command, specify <command name> -widget.

Widget Components
The following figure represents a typical widget window.

Figure 14-1 Widget Window

Menu Bar Header Dynamic Data

Summary Bar Static Table

The window comprises of the following components:


1. Menu Bar comprises of:
❑ File Menu - has options to save and close the table.
❑ View Menu - has show or hide options for any column, header, and the table
displaying total at the bottom.

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❑ Filters Menu - has options to filter data or clear applied filters.


❑ Plot Menu - has plot options such as Line Graph, Bar Graph, and Histogram.
2. Header has general information such as Units, Instance, Frame, Duration, and Design
relevant to the underlying command.
3. This is a dynamic table of data. Data in this table can be sorted, filtered, and plotted.
Column Headers are interactive as follows:
❑ Left Click : Selects the column data and shows relevant summary on the Summary
Bar at the bottom.
❑ Double Left Click: Toggles between sort orders.
❑ Right Click: Displays a context menu to perform Sort, Select, and Hide actions.
4. This is a static table to show sum and averages of respective columns.
5. Summary Bar is the bottom most section of the widget and shows cell data of the
selected cell or summary of the selected column.

Plotting Data in GUI Widget


The Plot menu item in the Widget window provides option to create the following types of plots
and charts for data analysis
■ Line Graph /Scatter Plot
This format displays one or more numerical column on Y-axis against one X numerical
column in form of line or Scatter Plot. The Plot Line Graph dialog is shown below.

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Figure 14-2 Plot Line Graph Dialog

Selecting the Normalize option normalizes all lines to their respective maximum values.
Sample normalized line and scattered graphs are shown below.

Figure 14-3 Sample Normalized Line Graph

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Figure 14-4 Sample Scatter Graph

■ Bar Graph
This format displays one or more numerical column on Y-axis against any column or
respective row number in form of Bars. It can also plot Data Frequency (non-continuous)
of any column. Plot Bar Graph dialog is shown below.

Figure 14-5 Bar Graph Dialog

Selecting Normalize option normalizes all bars to their respective maximum values.

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Sample bar graph and data frequency graph are shown below.

Figure 14-6 Sample Bar Graph

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Figure 14-7 Sample Data Frequency Graph

■ Histogram
This format displays distribution of numerical data on a continuous scale in specified
intervals. Plot Histogram dialog is shown below.

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Figure 14-8 Histogram Dialog

In this dialog, you can also specify the range between the histogram to be plotted.
A sample histogram is shown below.

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Figure 14-9 Sample Histogram

Cross-probing from Widget Window


You can cross probe instances in a widget window to the following windows in Joules GUI:
■ Object Attributes window - displays all attributes, along with their values, for the
selected object. Refer to “Object Attributes” on page 182 for more information.
■ Hierarchy Browser - displays the design hierarchy, including all its objects, as a tree
view. Refer to “Hierarchy Browser” on page 174 for more information.

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Right clicking an instance displays the context-sensitive menu for cross probing, as shown in
the following figure.

Figure 14-10 Menu for Cross Probing

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The following figure shows the instance cross probed in Object Attributes window.

Figure 14-11 Object Attributes Window

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The following figure shows the instance cross-probed in Hierarchy Browser.

Figure 14-12 Hierarchy Browser

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15
Design Navigation and Power Debug

This chapter discusses the following:


■ Getting List of Design Instances
■ Getting Instance Pins (or Ports)

Joules offers a rich set of commands for design navigation and data mining, integrating both
RTL and gate-level view of the design, and spanning power, timing, area, and activity through
the design and its elements. The capabilities include:
■ Traversal by hierarchy, clock domain, power domain (CPF/1801)
■ Design element categorization by RTL constructs, for example, adder, multiplier,
registers
■ Extraction of design data including: delay, slack, area, power, activity
■ Library cell distinction by function class (and, or, not, xor, mux, etc.), drive strength
■ Data type association for pins (clock, reset, data, address, etc.)
■ Reporting and plotting

There are four types of commands in Joules:


■ is_* commands – these check some property of the design element and returns 0 or
1. For example: is_register, is_icgc, is_seq, is_comb.
■ get_* commands – these return property value(s) of design elements. For example:
get_insts, get_libraries, get_inst_width, get_inst_power. Return value of
-1 indicates error.
■ report_* commands – these report multiple properties for groups of design elements
in a tabular format. For example: report_libcells, report_power,
report_activity. These commands return 0 for success, and 1 for failure.
■ plot_* commands – these commands use gnuplot to plot data and are useful for data
trend analysis. For example: plot_power_profile, plot_cell_sensitivity.
These commands return 0 for success and 1 for failure.

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This chapter discusses some useful commands for design navigation and data mining.

Getting List of Design Instances


One of the key commands is the get_insts command that returns a list of instances using
a variety of properties. Instead of a Tcl list, the command can also return an iterator that can
significantly speed-up instance processing in Tcl. Refer to get_insts in Joules Command
Reference for information on command syntax and usage.

Getting Instance Pins (or Ports)


Given an instance (hierarchical or leaf), get_inst_pins command returns the list of pins
(or ports) of the instance. Refer to get_inst_pins in Joules Command Reference for
information on command syntax and usage.

Associated Nets, Net Drivers, and Sink Pins


The following commands link pins and nets of the design:
■ get_associated_net <pin>
Returns full pathname of the net associated with the specified pin.
■ get_net_driver <net>
Returns full pathname of the driver pin of the specified net.
■ get_net_sinks <net>
Returns list of sink pins (full pathnames) of the specified net.

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Joules Power Bridge - Interface with
Other Cadence Tools

This chapter discusses the following:


■ Overview
■ Joules Interface for Other Cadence Tools

Overview
From inception to signoff, a design is refined through several levels of abstraction - starting
from System level, to RTL, to netlist (mapping, placement, clock-tree synthesis, routing), and
finally GDS. The flow spans three design disciplines - Verification, Implementation, and
Signoff. Verification teams verify the functionality of the design, the Implementation teams
take the design from RTL to GDS, and the Signoff teams validate that the implemented design
meets IC manufacturing requirements. Power analysis across the entire design flow has
always been a challenge for IC design companies.

Joules is built to serve as a bridge to enable a consistent power analysis methodology across
Verification, Implementation, and Signoff teams, as depicted in the following figure. Each of
these teams use different tools, require different input data, and generate different output.

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Figure 16-1 Joules Power Bridge

■ Verification teams simulate the design to test functionality. They use simulation and
emulation tools at the System and RTL levels for this purpose, and generate large activity
files that are post processed to debug the design. System-level designers responsible for
setting timing/power targets early tradeoffs, work with the Verification teams. Together,
they often seek to estimate power of the system using activity generated from the
system- level tests.
For Verification teams, Joules provides RTL power estimation that uses an embedded
timing-aware credible synthesis engine, clock-tree, and P&R buffer estimation.
■ Implementation teams responsible to deliver a design with specific timing/power targets
need to use activity generated by Verification teams for power optimization. The problem
they face is that the annotation from RTL activity from Verification teams on the post
synthesis netlist is typically very low. Synthesis tools dissolve hierarchies, split RTL
registers across single bit and multi-bit flops, insert clock gating cells (ICGCs), and insert
DFT logic. This causes mismatch in signal names stored in RTL stimuli (activity file) and
name of RTL objects in the netlist, resulting in poor annotation.
For Implementation teams, Joules' rtlstim2gate feature can map RTL stimulus on a
netlist with very high annotation. Use of Joules' rtlstim2gate in Cadence-based design
flows is seamless.

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■ Signoff teams work with post P&R design which encapsulates large amount of data -
netlist, cell and pin placement, net parasitics and routing across multiple metal layer, etc.
Data activity is needed for peak current and voltage drop analysis. However, as the
design data is large, signoff analysis can only be done for 10-100 cycles of peak activity.
Joules can identify and peak frames from RTL activity with large number of cycles, and
use rtlstim2gate to generate 10-100 cycles of equivalent gate-level time-based activity in
VSDB format (refer to section Support for Activity Formats) for signoff analysis using
Voltus. Joules can also merge peak activity from different blocks to emulate peak activity
scenario for signoff analysis. For thermal analysis, user can break up the design across
tiles and have Joules generate power profile over time for each tile.

The following Joules capabilities help facilitate data flow for power analysis across the entire
design flow:
■ Support for Activity Formats
Joules can read input activity in the following formats: VCD, FSDB (Version 5.3), SHM
(generated using IES 15.2+), PHY (generated using UXE 14.1+, and VXE 15.1+), TCF,
SDPD (State Dependent Path Dependent), and SAIF (Version 2.0). Refer to
read_stimulus in Joules Command Reference for more information.
Joules can write out activity in the following formats: TCF, SAIF, and VSDB (Voltus
Stimulus DB). VSDB is binary time-based activity format that Voltus can read. Refer to
write_stimulus in Joules Command Reference for more information.
Joules can also dump activity and power profile of the design hierarchy by category
(memory, register, latch, logic, clock, pad, etc.) in SHM for debug using SimVision, and
FSBB (Version 5.1) for debug using Verdi.
Given Joules' support for different stimulus formats, it can be used to translate activity
from any format into TCF or SAIF.
■ rtlstim2gate
Joules' rtlstim2gate is a rule-based system that supports separate set of naming rules
for simulation (for example, how generate statements are unrolled, VHDL records, SV
structs are expanded), and synthesis (for example, hierarchy separator, register naming,
generate statement unrolling). Naming rules used by Cadence tools - Incisive Simulator,
Palladium Emulator, Genus Synthesis tool, Innovus P&R tool are predefined in Joules,
making use of rtlstim2gate in Cadence-based design flows seamless. Refer to
rtlstim2gate in Joules Command Reference for more information.
■ Peak Frame Identification
Joules' frame-based architecture is well suited for identifying peak power frame very
quickly. We recommend doing the peak frame analysis in two or more passes. Say you

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have a 100K cycle stimuli and want to identify a 1K cycle peak window that includes a
25-cycle peak frame. In the first pass, break the 100K cycle stimuli into 100 1K frames
and identify the peak 1K frame. Let's say frame#62 was the peak frame. In the second
pass, process the 3K cycle window with frame#61, frame#62, and frame#63, break it up
into 120 x 25-cycle sub-frames and identify the 25-cycle peak sub-frame. Then look for
a 1K cycle window around the 25-cycle peak sub-frame with max average power. You
can then write VSDB for the 1K cycle peak frame and use Voltus for signoff analysis
(peak current, dI/dT, etc.)

Joules Interface for Other Cadence Tools


The following section discusses Joules’ interfaces for specific tools.
■ Palladium Interface
Palladium is Cadence's emulation box, used by customers to run large simulation vectors
(millions of cycles) on big designs. The Palladium box supports both RTL and netlist
designs and is over 1000x faster than simulation. The emulation activity is captured in a
binary database called PHY, and can be converted into other industry standard activity
formats such as TCF, SAIF, or FSDB using the DPA (Dynamic Power Analysis) tool.
❑ Direct PHY Read (refer to Reading PHY Database from Palladium on page 74 for
more information)
While average formats TCF and SAIF can be generated reasonably fast from PHY,
generation of FSDB can take a long time. For time-based processing, Joules' Direct
PHY read (tPR) is 10x faster than PHY -> FSDB + FSDB read (tFW + tFR).
Note: Direct PHY Read requires a DPA license.

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Figure 16-2 Palladium Interface

❑ DPA/Joules
DPA is an offline tool that reads the PHY and generates activity waveforms of two
kinds: (i) NTC - Native toggle count, or raw toggle count, and (ii) WTC - Weighted
toggle count, where the toggles are weighted based on power of different object
types such as flops, and, or, not gates. The toggle waveforms are useful in detecting
peak activity frames in the stimulus. Though toggle waveforms provide an indication
of power consumption, Palladium users often want to view actual power waveforms
and identify peak power frames from the stimulus.
DPA has integrated Joules to augment its NTC and WTC activity profiles with power
profiles generated from Joules. For RTL designs, Joules performs fast timing aware
synthesis, models clock-tree, and placement buffers, and estimates power at RTL
within 15% of signoff power.
■ Incisive (IES) Interface
Incisive is Cadence's HDL simulation tool. It captures the simulation activity in a binary
database called SHM. Activity formats VCD and SAIF can be generated from SHM
through Cadence's SimVision tool. IES can also generate VCD, SAIF, and TCF formats
natively (without having to go through SHM). There are, however, several limitations in
the native VCD generation for IES. The natively generated VCD excludes memory input/
output pin activity and multi-dimensional arrays (MDAs). FSDB can be generated natively
through use of Synopsys FSDB APIs. IES can also read Forward SAIF (FSAIF) and
generate SDPD (State Dependent Path Dependent) SAIF that includes arc counts of LIB
cells included in the input FSAIF file. This is a new feature introduced in IES 16.1 release
and is currently under beta testing.

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❑ Direct SHM Read (refer to Reading SHM Database on page 80 for more
information)
Joules' read_stimulus command can read SHM directly and is a complete
interface that extracts activities for all objects including memories, MDAs (multi-
dimensional arrays), SV structs, and VHDL records. Direct SHM read is fast and
eliminates the need to generate VCD from SHM using SimVision, a buggy and
cumbersome process.
❑ Power and Activity Profile by Design Hierarchy and Object Category
Joules' dump_power_profile and dump_activity_profile commands (refer
to dump_power_profile and dump_activity_profile in Joules Command Reference
for more information) can generate SHM database that contains power and activity
profiles respectively for all hierarchies of the design and by object category
(memory, register, logic, clock, etc.). This can then be loaded into SimVision for
graphical viewing and debug.
■ Genus/Innovus Interface
Genus is Cadence' logic synthesis tool that performs technology mapping for an RTL
design and creates a gate-level netlist optimized for timing, power, and area. Innovus is
Cadence' P&R tool that does placement, clock-tree synthesis, and routing. For power
optimization, both Genus and Innovus require typical activity for flops and logic gates.
Both tools can read TCF (average activity) and VCD (time-based activity) activity files. If
the activity is from gate-level simulation, the annotation is high, but is low from RTL
activity files.
❑ Converting RTL Activity into Gate TCF
Joules can load Genus DB, and use rtlstim2gate along with write_stimulus
-format TCF to translate the RTL activity file into a gate-level TCF file
consumption by Genus and/or Innovus with high annotation.
❑ Joules Integration with Genus
In the next release, Joules will be integrated with Genus. All of Joules functionality
will be available from Genus shell, including Joules activity propagation and power
engines. Joules license will be checked out for use of Joules' specific features such
as FSDB, SHM, PHY read, multi-stimulus read, and framing.
■ Voltus Interface
Voltus is Cadence' power signoff tool that can compute power, perform peak current,
voltage drop, and rail analysis, on a signoff netlist. For signoff analysis, it needs a time-
based activity. As the signoff designs have large volume of data, signoff analysis is

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typically performed over short windows (10-100 cycles). Similar to implementation tools,
Voltus also has a problem consuming RTL activity files.
Joules can process large RTL activity files, identify peak power frames, use
rtlstim2gate to convert RTL activity to level, and write_stimulus command to
write a binary time-based activity file called VSDB (Voltus Stimulus DB) for consumption
by Voltus.
■ Sigrity Interface
Sigrity is Cadence's thermal analysis tool. It uses board and package models, die
dimensions and tiling information, and power profile per tile as input, and generates a
thermal model which is used for transient thermal simulation. The thermal profile
generated from simulation is used to determine the location of heat sinks and thermal
sensors on the chip. Power of a digital device depends on temperature. When the heat
dissipated from the chip exceeds the capacity of the heat sinks on the chip, the
temperature of the chip rises, which can affect the power consumption - resulting in a
cross dependency between thermal profile and power. This requires a close loop
analysis.

Figure 16-3 Thermal Analysis Flow

The above figure shows the flow for early thermal analysis. Genus-Physical can be used
to generate a placed netlist from the RTL, and RTL activity can be generated using IES
simulation (SHM) or Palladium emulation (PHY). Joules can read these and generate

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Power Profile By Tile (PPBT) using command report_power -by_tile. The


generated PPBT can then be fed to Sigrity for thermal analysis.

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17
RTLScore Shell

This chapter discusses the following:


■ RTL Shell (RTLSH): An Overview
❑ Benefits
❑ Features
❑ Customization
■ RTLSH Quick Reference

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RTL Shell (RTLSH): An Overview


RTL Shell (RTLSH) is an independent module developed in C that integrates TCL scripting
interface and TCL Shell (TCSH) command editing capabilities of Genus with some additional
functionality. RTLSH is easily configurable with clear interfaces and allows for product-based
customization and easy integration into any Cadence product.

Benefits
Using RTLSH as the user shell provides the following benefits:
■ All the output of the tool (everything users see on their screen), is captured in the log file.
This makes it easy to review and diagnose issues.
■ All commands executed in the tool are captured in the cmd file.
Note: If a script is sourced, contents of the source script should be expanded and saved in
the cmd file. This will make it easy to report bugs and for development teams to reproduce it
onsite.
■ TCL scripting (inherited from Genus) is embedded in RTLSH. This enables users to build
customized scripts and utilities for their environment.
■ TCSH command line editing (inherited from Genus) is embedded in RTLSH. This
significantly enhances user experience in interactive use of the tool.

Features
RTLSH provides the following features:
■ TCL command interface for script development and interactive use.
■ TCSH command line editing. This includes command completion, file command
completion, getting commands from history, command option help, and command
redirection.
■ Notion of a Work directory (configurable). This is where all tool output (such asc log file
and cmd file) is stored so that your work directory is not cluttered.
■ Notion of INI files for tool setup using TCL commands. Multiple levels are supported for
easy customization across multiple groups at user site.
■ Cmd file that captures all the typed commands and expanded sourced files. This helps
reproduce runs at the factory for bug fixes.

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■ Log file that captures all TCL command output. All output from the tool can be logged
using RTLSH functions, RTLSH_Fprintf() and RTLSH_Printf().

Customization
A product-specific definitions (.h) file configures the following in the RTLSH package:
■ Product name (for example, 'joules')
■ Product version (for example, '14.2')
■ Release date (for example, 'Nov 15, 2010')
■ Product installation root environment variable (for example, 'RTLSCORE_ROOT')
■ Product INI environment variable (for example, 'JOULES_INI')
■ Primary RTLSH prompt (for example, 'Joules> ')
■ Secondary RTLSH prompt (for example, ' % ')
■ RTLSH variables available in the tool as TCL variables (names are configurable)

Default values of most entries are set using the product definitions, and several of these are
user configurable through the use of predefined TCL variables. These include:
■ Default work directory is set to ./<product>_work/
❑ You can configure work directory using TCL variable <product>WorkDir
■ Default log file is set to <product>.log (saved in the work directory)
❑ You can configure log file using TCL variable <product>LogFile
■ Default cmd file name is <product>.cmd (saved in work directory)
❑ You can configure cmd file using TCL variable <product>CmdFile

INI Files

.ini files typically contain product setup commands such as setting work directory, naming
log and cmd files, and copying required input files for the product. RTLSH looks for and
sources the .ini files in the following order. Files read last override previous settings.
1. $INSTALLATION_ROOT/config/<product>.ini is read. Each product is expected
to have a default .ini file that resides here.
2. $HOME/<product>.ini file, if present, is read - This file allows for customization.

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3. $PWD/<product>.ini file, if present, is read - This file allows for run customization
4. File pointed to by $<INI_VARIABLE>, if present, is read. This file is typically used for
project-based customization.

A sample .ini file is shown below:

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Invocation of the tool with embedded RTLSH looks as follows:

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RTLSH Quick Reference


The following table provides a quick reference to working with RTLSH:

Table 17-1 RTLSH Quick Reference

Special TCL variables joulesWorkDir : default ./


joules_work/

joulesLogFile : default
$joulesWorkDir/joules.log

joulesCmdFile : default
$joulesWorkDir/joules.cmd

INI file read order 1. $RTLSCORE_ROOT/joules.ini


2. $HOME/joules.ini
3. $PWD/joules.ini
4. $JOULES_INI (if set)
Command completion/listing Enter partial command and press <tab>
Command options listing Enter complete command and press <tab>
Command history Previous command:

<up-arrow> or <ctrl-p>

Next command:

<dn-arrow> OR <ctrl-n>
Save 50 commands in history history keep 50 (TCL command)

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Command-line editing back one char: <left-arrow> or <ctrl-b>

forward one char:<right-arrow> or <ctrl-f>

back one word: <esc-b>

forward one word: <esc-f>

beginning of command line: <ctrl-a>

end of command line: <ctrl-e>

delete left char: <delete> or <backspace>

delete current char: <ctrl-d>

delete rest of line (deleted portion saved in buffer):


<ctrl-k>

insert from buffer: <ctrl-y>


File command completion/listing Type command and partial filename and press
<tab>
Command output redirection joules> puts "line 1" > foo.txt
joules> puts "line 2" >> foo.txt

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18
Frequently Asked Questions

Synthesis tools consider cell static (leakage) power for clock gating. It is more
meaningful to consider dynamic (internal + switching) power for clock gating. How can
Joules help?

Synthesis tools perform clock-gating as follows:


■ User-specified clock gating (coded in RTL) is performed first, taking into account the CG
min_width constraint (minimum number of flops to gate per ICGC).
■ User-specified CG opportunities that do not meet the CG min_width constraint, are
considered for Enhanced Clock Gating (ECG), where the tool tries to extract common
enables from groups of ungated flops to satisfy the CG min_width constraint.
■ For flops that do not have user-specified gating (in RTL), the tool tries to create a gating
signal. For example, the tool can select low activity flops, and generate an enable by
XOR-ing the D-input and Q-outputs.
■ Other methods of generating enables include propagating existing flop enables
upstream and downstream across register stages. This necessitates formal verification
of the transformation.
■ Then there are methods to strengthen enables. For example, if an enable A & B can be
replaced by just A, you have strengthened the enable. Strengthening enables for high
impact ICGCs (the ones that gate significant downstream flops), can reduce dynamic
power significantly.
For opportunities (iii), (iv), and (v), it is important to consider dynamic power savings
across multiple design operational scenarios that synthesis tools are not equipped to do.
Joules’ frame-based architecture is well suited for such analysis and identification of the
correct ECG candidates.

Is it possible to scale the leakage numbers of the library/library cells in Joules?

Joules can scale the power numbers by: (i) power type (leakage, internal, switching), (ii)
hierarchy, (iii) clock domain, and (iv) power domain via set_power_scale_factor.

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Scaling by library is not supported as of now.

What are the appropriate scenarios to use compute_power –auto_tune?

You should use this option when:


■ Stimulus is from RTL simulation
■ Annotation on RTL Driver Nets is low
■ Logic has high proportion of xor/xnor gates

In Voltus, there is an option (set_power_analysis_mode -x_transition_factor ) to


control how to count the X transitions in a VCD stimuli. Is there a similar option in
Joules? Also, how to control glitches?

To handle X, set the following attributes before read_stimulus:


■ set_attr stim_set_x_0 1 -> will consider all X as 0
■ set_attr stim_set_x_1 1 -> will consider all X as 1

There is an option in read_stimulus, –compat voltus|pt, which models X behavior as


Voltus and PTPX.

To control glitches, use the option read_stim –filter_zero_delay_glitch.

In Joules GUI, why are datapath components always displayed in dotted lines on top
level of the treemap? This can be very confusing if there are many datapath
components in many hierarchy levels. Can this be switched off?

All the macros are always visible in Treemap and are displayed by dotted lines if they lie
deeper in hierarchy than the current visible levels.

This cannot be turned off.

Can we read incomplete and/or inconsistent code into Joules? It would use Genus
proto_hdl attribute automatically trying to resolve mismatches as port direction, bus
width, port name upper/lower case, missing modules, etc…

Whatever is supported by Genus proto_hdl attribute under express_flow limited feature, is


supported in Joules.

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Does Joules require a Genus_Physical_Opt license to read in a DEF?

read_def requires a Genus license to be picked up via the -add_license option.

If we are using library_domains to define different library sets to sub-blocks, will


gen_clock_tree respect the library_domains when selecting cells for clock trees within
each sub-block

Yes, the gen_clock_tree command will use cells from the specified library.

What is the recommended way for reporting the quality of powermap? How can we
check that Joules powermap netlist has come close to meeting timing to give
confidence that the power number is reasonable?

Run compare_db -compute_stats to compute and report a 50 point score. A score of


greater than 40 is considered good.

I am getting the following error on running read_stimulus -format phy:

Error: xeDebug binary for PHY read: not found in $PATH.

Is there any other packages that need to be in the path with Joules?

You need xeDebug in the path. It is a binary from Palladium which is used to generate full view
waveform of all nodes in the design. PHY only has waveform of state points and primary
inputs.

Is there a way to get a report of which instances have been categorized as pads and/
or bbox?

Yes. Use:
get_insts -rtl_type bbox
get_insts -rtl_type pad

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Can Joules leverage an MMMC setup for RTL analysis?

In other words, if a customer is already running Voltus with analysis views defined, can
Joules leverage those setup files to run the same corner and conditions as Voltus?

Joules honors MMMC setup in common ui mode. The view that is specified for power in
set_analysis_view command will be used for power analysis.

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A
Acronyms and Definitions

The following table explains the commonly-used acronyms in Joules.

Acronym Definition
ALU Arithmetic Logic Unit
AOCV Advanced On-chip Variation
ATPG Automatic Test Pattern Generation
BIST Built-in Self Test
BSDL Boundary Scan Description Language
CCD Conformal Constraint Designer
CDFG Control Data Flow Graph
CFG Control Flow Graph
CG Clock Gating
CGI Clock Gating Instances
CGIC Clock Gating Integrated Circuit
CGLAR Clock Gate Low Activity Register
CLP Conformal Low Power
CMOS Complementary Metal Oxide Semiconductor
CPF Common Power Format
CTG Clock Tree Generation
CTL Core Test Language
CUI Common User Interface
DACGE Data Aware Clock Gating Efficiency

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Acronyms and Definitions

Acronym Definition
DBU Database Unit
DEF Design Exchange Format
DFT Design For Test
DFM Design for Manufacturing
DPA Dynamic Power Analysis
DUT Design Under Test
DVFS Dynamic Voltage Frequency Scaling
ECG Enhanced Clock Gating
ELAB Elaboration
ETT Encounter True Time
FNP Flexible Numbering Plan
FSDB Fast Signal Database
FSM Finite State Machine
HDL Hardware Description Language
IC Integrated Circuit
ICGC Integrated Clock Gating Cell
(ICGC and CGIC are used interchangeably)
ILM Interface Logic Model
IMPL Implementation
JDB Joules Database
LBIST Logic Built-in Self Test
LEC Logical Equivalence Checker
LEF Library Exchange Format
LIB LIBerty (Library) format
LSSD Level Sensitive Scan Design
MBCI Multi-bit Cell Inferencing
MBIF MBIST Information File

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Acronym Definition
MDA Multi-dimensional Array
MMMC Multi-Mode Multi-Corner
MSV Multiple Supply Voltages
NCSim NC Simulator
NTC Native Toggle Count
PHY PHYsical probes
(Waveform data that is directly captured in Palladium
trace buffer. Based on the physical probes, users
compute the waveform for the entire design)
PLE Physical Layout Estimation
PMBIST Programmable Memory Built-in Self Test
PPA Power Performance Area
PPBT Power Profile By Tile
PRDB Power Regression DB
PSO Power Shutoff
PTAM Power Test Access Mechanism
PVT Process Factor, Volume, and Temperature
RTC Raw Toggle Count
RTL Register-transfer-level
RTLSH RTL Shell
SAIF Switching Activity Interchange Format
SDB Stimulus DB
SDC Synopsis Design Constraints
SDPD State-Dependent and Path-Dependent
SHM Simulation History Manager
SPEF Standard Parasitic Exchange Format
STIM STIMulus
TCF Toggle Count Format

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Acronyms and Definitions

Acronym Definition
TCSH Tcl Shell
TNS Total Negative Slack
TUI Tcl User Interface
UPF Unified Power Format
VCD Values Change Dump
VDIR Virtual Directory
WTC Weighted Toggle count

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