Audio Processing on the Xilinx ML403 Virtex-4 Evaluation Board

By

Ross Snider, Ph.D.

Associate Professor
Electrical and Computer Engineering Department
Montana State University

Spring 2009

Note: this is just an initial draft.....

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 Audio Processing on the Xilinx ML403 Virtex-4 Evaluation Board
The ML403 board contains the LM4550 (National Semiconductor), which is an AC ‘97 Audio
Codec. The LM4550 is circled in yellow as shown below. The microphone and line-in inputs
are shown as well as the line-out and headphone outputs.

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The physical connections to the LM4550 can be seen in the Audio Codec page of the ML403

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Schematics and can be seen in the following figure. The microphone and line-in inputs are
shown in the schematics as well as the line-out and headphone outputs. The LM4550 is capable
of additional audio I/O, but these are not connected in the ML403.

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Table of Contents goes here.....

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 4 3 2 1

1 C125 1 C124 VCC5 VCC5_AUDIO

AUDIO_SDATA_OUT
AUDIO_BIT_CLK 33PF 33PF FB0805
D 2 2 D
AUDIO_SYNC R121
FLASH_AUDIO_RESET_N 1 2
1 2

2
1M 1 C22 FB7 1 C21
0805 0805
24.576MHZ

R120
3.3K
FB0805
2 2

R119
3.3K
1UF 1UF

1
1 2
FB8

GND_AUDIO
VCC3V3

X4

XTAL_SMD
AUDIO_SDATA_IN

C12
1UF
6.81K 0805 1 C113 1 C23
LINE_INPUT_JACK 1 C115
2 1 1 C117 1 C13 0.1UF

1
2
1 R111 2 2

2
0.1UF 1UF
0.1UF 2
0805
5 2 2 1UF

R112
0805

12
11
10
9
8
7
6
5
4
3
2
1
C18
220UF
D
4

1
6.81K
C C
3

1
2 2
2

J14

SYNC_10
DVDD2_9
DVSS2_7
DVSS1_4
DVDD1_1
1 C122

XTL_IN_2

BIT_CLK_6
XTL_OUT_3

C14
PC_BEEP_12
RESET_N_11
SDATA_IN_8

1UF
J12 6.81K 0805 10K

SDATA_OUT_5
R118

220PF 2
2
1

2 1 3

1
2
R114

2
C17
220UF
D

4
0805

R113
13 48 NC 1UF 2 5
13_PHONE_IN CIN_JS1_48
14 47 NC
1
2

14_AUX_L EAPD_JS0_47

1
6.81K
2

15 15_AUX_R LM4550 ID1_46 46 NC 1

16 45 NC C19 1 1 C121
16_VIDEO_L ID0_45 HEADPHONE_JACK
17 17_VIDEO_R LQFP48 NC_AVSS3_44 44 NC
10K
R117

MICROPHONE_JACK 18 43 NC 220PF
18_CD_L NC_AVDD3_43 2

C9
19 42 NC

1UF
19_CD_GND_REF NC_42
1

1 1K 0805 20 41
20_CD_R HP_OUT_R_41
21 21_MIC1 HP_OUT_C_AVSS2_40 40
5 2 1 22 39

1
2
R107 22_MIC2 HP_OUT_L_39
23 23_LINE_IN_L NC_AVDD2_38 38 NC
4 24 37 NC
24_LINE_IN_R MONO_OUT_37
C16

2
1UF

3
0805

R108
49.9K
1
2

B B
2

J13

1
1 C114 1 C120
J11
10K
R116

0.1UF 220PF 2
2 2
1

DEVICE=LM4550VH 3
PKG_TYPE=LQFP48
C15

PARTS=1 4
1UF

25_AVDD1
26_AVSS1
27_VREF
28_VREFOUT
29_NC_AFILT1
30_NC_AFLIT2
31_NC_FILT_R
32_NC_FILT_L
33_3DN_RX3D
34_3DP_CX3D
35_LINE_OUT_L
36_LINE_OUT_R
47R 2.2K LEVEL=STD

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0805

25
26
27
28
29
30
31
32
33
34
35
36
2 1 2 1
1
2

R110 R109
2

1 C10 1
1 C119
220PF U14 LINE_OUTPUT_JACK

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2 10K

NC
NC
NC
NC
R115

220PF
2
1

1 C403

2.2UF 1 C123 1 C380

2
0805

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0.1UF
2 2 1UF
0.022UF
C118
0603

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VCC5_AUDIO
10K
1
2

Title:
A 2 1
R240 Audio Codec
1 C11 1 C116
A
2.2UF 0.1UF Date: Ver:
2 2
Sheet Size: B Rev: B

Sheet of Drawn By
17 24 BF

4 3 2 1
 The user guide description of the audio codec (p. 24) is shown below:

Detailed Description
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11. Stereo AC97 Audio Codec

The ML40x board has an AC97 audio codec (U14) to permit audio processing. The
National Semiconductor LM4550 Audio Codec supports stereo 16-bit audio with up to
48-kHz sampling. The sampling rate for record and playback can be different.
Note: The reset for the AC97 codec is shared with the reset signal for the flash memory chips and
is designed to be asserted at power-on or upon system reset.
Separate audio jacks are provided for Microphone, Line In, Line Out, and Headphone. All
jacks are stereo except for Microphone. The Headphone jack is driven by the audio codec's
internal 50-mW amplifier. Table 12 summarizes the audio jacks.

Table 12: ML40x Audio Jacks

Reference
Function Stereo/Mono
Designator
J11 Microphone - In Mono
J12 Analog Line - In Stereo
J13 Analog Line - Out Stereo
J14 Headphone - Out Stereo

12. RS-232 Serial Port

The ML40x board contains one male DB-9 RS-232 serial port allowing the FPGA to

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communicate serial data with another device. The serial port is wired as a host (DCE)
device. Therefore, a null modem cable is normally required to connect the board to the
serial port on a PC. The serial port is designed to operate up to 115200 Bd. An interface chip

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is used to shift the voltage level between FPGA and RS-232 signals.

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Note: The FPGA is only connected to the TX and RX data pins on the serial port. Therefore, other
RS-232 signals, including hardware flow control signals, are not used. Flow control should be
disabled when communicating with a PC.

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A secondary serial interface is available by using header J27 to support debug of the USB
controller chip. Header J27 brings out RS-232 voltage level signals for ground, TX data, and
RX data.

13. 16-Character x 2-Line LCD

The ML40x board has a 16-character x 2-line LCD (Lumex LCM-S01602DTR/M) on the
board to display text information. Potentiometer R1 adjusts the contrast of the LCD. The
data interface to the LCD is connected to the FPGA to support 4-bit mode only. A level
translator chip is used to shift the voltage level between the FPGA and the LCD.
Caution! Care should be taken not to scratch or damage the surface of the LCD window. The
protective layer of tape on the top of the screen should be left on for added protection of the
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 Signal Path Control Settings
The following register descriptions refer to the signal path block diagram below
and on page xxxx where the control setting numbers refer to the boxed num-
bers on the signal path.
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Control Setting #1 - Microphone Input Selection

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The microphone #1 or #2 can be selected by setting the general purpose register 20h.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

20h General POP x 3D x x x MIX MS LPBK x x x x x x x 0000h
Purpose

BIT NameValue Function

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D15 POP 0 Go through 3D block
1 Bypass 3D block
D13 3D 0 3D sound off

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1 3D sound on

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D9 MIX 0 Mono output = Mix (not connected)
1 Mono output = Mic (not connected)

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D8 MS 0 Mic select = MIC1
1 Mic select = MIC2
D7 LPBK 0 No ADC/DAC Loopback
1 Enable ADC/DAC Loopback
Default: 0000h (MIC1 input)
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Control Setting #2 - Microphone Gain Control

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The microphone input can have a 20dB volume boost by setting bit D6 in the microphone vol-
ume register 0Eh.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

0Eh Mic Mute x x x x x x x x 20 dB x GN4 GN3 GN2 GN1 GN0 8008h
Volume

BIT Value Function

D6 0 0 dB Gain
1 20 dB Gain in microphone input
Mute (Bit D15) GN4:GN0 (Bits D4:D0) Function

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0 0_0000 +12 dB gain
0 0_1000 0 dB gain
0 1_1111 34.5 dB attenuation

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1 x_xxxx mute

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Default: 8008h (mute, 0 dB gain)
Note 1: Bit D6 controls the 20dB boost on the input that gets routed to the input

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selection mux. The other bits (mute and gain/attenuation) control input into mixer 1.
Note 2: The mute only works for signal input into mixer 1 (it doesn’t mute the mic
input going to the input selection mux)
Note 3: The bits in D4:D0 control the gain from +12 dB to -34.5 dB in steps of -1.5
dB into mixer 1.
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Control Setting #3 - Input Selection Control

The input selection multiplexer controls which input is selected and is controlled via register 1Ah.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

1Ah Record x x x x x SL2 SL1 SL0 x x x x x SR2 SR1 SR0 0000h
Select

SL2:SL0 Source for Left SR2:SR0 Source for Right

Channel ADC Channel ADC
0 - 000b Mic input 0 - 000b Mic input
1 - 001b CD input 1 - 001b CD input
2 - 010b Video input 2 - 010b Video input

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3 - 011b Aux input 3 - 011b AUX input
4 - 100b Line-in 4 - 100b Line-in
5 - 101b Stereo Mix 5 - 101b Stereo Mix

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6 - 110b Mono Mix 6 - 110b Mono Mix

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7 - 111b Phone input 7 - 111b Phone input
Default: 0000h (Mic input on both left and right channels)

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Note 1: The CD, Video, Aux, Phone inputs are not connected.
Note 2: The left and right channels can be independently selected.
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Control Setting #4 - Input Gain Control

The selected input can have up to a 22.5dB gain boost by setting the record gain register 1Ch.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

0Eh Record Mute x x x GL3 GL2 GL1 GL0 x x x x GR3 GR2 GR1 GR0 8000h
Gain

Mute (Bit D15) Gx4:Gx0 Function

(Bits D11:D8 - Left)
(Bits D3:D0 - Right)
0 0000 0 dB gain
0 1111 22.5 dB gain

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1 xxxx mute (-86 dB)
Default: 8000h (mute, 0 dB gain)
Note 1: Bit D15 when set will mute the input.

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Note 2: The bits in Gx4:Gx0 control the gain from 0 dB to +22.5 dB in steps

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of +1.5 dB.

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 L M4 5 5 0

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Control Setting #5 - Input Sample Rate

The input can be sampled from 4 KHz to 48 KHz by setting both the ADC sample rate control register
32h and the extended audio status/control register 2Ah.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

2Ah Extended Audio x x x x x x x x x x x x x x x VRA 0000h
Control/Status

VRA (Bit D0) Function

0 VRA off (Frame Rate Sampling)
1 VRA on (Sampling Rate is programmed in sample rate control register 32h )
Default: 0 (VRA off)

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REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
32h PCM SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
ADC

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Rate

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SR15:SR0 Function
0FA0h 4 KHz (minimum rate)
BB80h 48 KHz (maximum rate)

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Default: BB80h (48 KHz)
Note 1: The sample rate can be programmed, in 1 Hz increments, to be any value from 4 KHz
to 48 KHz. The value required is the hexadecimal value of the desired sample rate, e.g. 8000
Hz would be specifed as 800010 = 1F40h.
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 Control Setting #6 - Output Sample Rate

The output can be sampled from 4 KHz to 48 KHz by setting both the DAC sample rate control
register 2Ch and the extended audio status/control register 2Ah.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

2Ah Extended Audio x x x x x x x x x x x x x x x VRA 0000h
Control/Status

VRA (Bit D0) Function

0 VRA off (Frame Rate Sampling)
1 VRA on (Sampling Rate is programmed in sample rate control register 32h )
Default: 0 (VRA off)

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

2Ch PCM SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
DAC
Rate

SR15:SR0 Function
0FA0h 4 KHz (minimum rate)
BB80h 48 KHz (maximum rate)
Default: BB80h (48 KHz)
Note 1: The sample rate can be programmed, in 1 Hz increments, to be any value from 4 KHz
to 48 KHz. The value required is the hexadecimal value of the desired sample rate, e.g. 8000
Hz would be specifed as 800010 = 1F40h.

Control Setting #7 - Output Volume Control

The output volume can be controlled by setting the PCM out volume register 18h.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

0Eh PCM Mute x x GL4 GL3 GL2 GL1 GL0 x x x GR4 GR3 GR2 GR1 GR0 8808h
Out
Volume

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Mute (Bit D15) Gx4:Gx0 Function
(Bits D12:D8 - Left)

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(Bits D4:D0 - Right)

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0 0_0000 +12 dB gain
0 0_1000 0 dB gain

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0 1_1111 34.5 dB attenuation
1 x_xxxx mute (-86 dB)
Default: 8808h (mute, 0 dB gain on both channels)
Note 1: The bits in Gx4:Gx0 control the gain from +12 dB to -34.5 dB in steps of
-1.5 dB.
 Control Setting #8 & #9 - Output 3D Sound Path Control

The output can be routed through the National 3D Sound block by setting the general purpose
register 20h.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

20h General POP x 3D x x x MIX MS LPBK x x x x x x x 0000h
Purpose

BIT Name Value Function

D15 POP 0 Go through 3D block
1 Bypass 3D block
D13 3D 0 3D sound off
1 3D sound on
D9 MIX 0 Mono output = Mix (not connected)
1 Mono output = Mic (not connected)
D8 MS 0 Mic select = MIC1
1 Mic select = MIC2
D7 LPBK 0 No ADC/DAC Loopback
1 Enable ADC/DAC Loopback
Default: 0000h (Go through 3D block, 3D sound off, MIC1 input, no loopback)

Control Setting #10 - Line-Out Volume Control

The line-out volume is set in the master volume control register 02h.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

02h Master Mute x x ML4 ML3 ML2 ML1 ML0 x x x MR4 MR3 MR2 MR1 MR0 8000h
Volume

Mute (Bit D15) Mx4:Mx0 Function

(Bits D12:D8 - Left)

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(Bits D4:D0 - Right)
0 0_0000 0 dB attenuation
0 1_1111 46.5 dB attenuation

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1 x_xxxx mute on both channels (-86 dB)

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Default: 8000h (mute, 0 dB attenuation on both channels)
Note 1: The bits in Mx4:Mx0 control the gain from 0 dB to -46.5 dB in steps of -1.5 dB.

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 Control Setting #11 - Headphone Volume Control

The Headphone volume is set in the headphone volume control register 04h.

REG Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

04h Head- Mute x x ML4 ML3 ML2 ML1 ML0 x x x MR4 MR3 MR2 MR1 MR0 8000h
phone
Volume

Mute (Bit D15) Mx4:Mx0 Function

(Bits D12:D8 - Left)
(Bits D4:D0 - Right)
0 0_0000 0 dB attenuation
0 1_1111 46.5 dB attenuation
1 x_xxxx mute on both channels (-86 dB)
Default: 8000h (mute, 0 dB attenuation on both channels)
Note 1: The bits in Mx4:Mx0 control the gain from 0 dB to -46.5 dB in steps of -1.5 dB.

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Designing the AC97 Digital Controller

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The Virtex-4 FPGA communicates and controls the LM4550 via five digital I/O lines that can be
seen on the previous page and their description is given below:

Digital I/O Line FPGA Function

Pin #
AUDIO_SDATA_OUT C8 Input to codec (play sound)
This is the input for AC Link Output Frames from an AC ’97
Digital Audio Controller to the LM4550 codec. These frames
(output from controller) can contain both control data and DAC PCM audio data.
This input is sampled by the LM4550 on the falling edge of
BIT_CLK.
AUDIO_SDATA_IN AD16 Output from codec (record sound)
This is the output for AC Link Input Frames from the LM4550
codec to an AC ’97 Digital Audio Controller. These frames
(input to controller) can contain both codec status data and PCM audio data
from the ADCs. The LM4550 clocks data from this output on
the rising edge of BIT_CLK.
AUDIO_BIT_CLK AE10 AC Link clock
An OUTPUT when in Primary Codec mode. This pin pro-
vides a 12.288 MHz clock for the AC Link. The clock is de-
(input to controller, rived (internally divided by two) from the 24.576 MHz signal
clock signal for timing, at the crystal input (XTL_IN). This pin is an INPUT when the
sample rates, etc.) codec is configured in any of the Secondary Codec modes
and would normally use the AC Link clock generated by a
Primary Codec.
AUDIO_SYNC D9 AC Link frame marker and Warm Reset
This input defines the boundaries of AC Link frames. Each
frame lasts 256 periods of BIT_CLK. In normal operation
(This signal goes high SYNC is a 48 kHz positive pulse with a duty cycle of 6.25%
for 16 clock cycles dur- (16/256). SYNC is sampled on the rising edge of BIT_CLK
ing the TAG slot and and the codec takes the first positive sample of SYNC as
indicates the start of a defining the start of a new AC Link frame. If a subsequent
new frame) SYNC pulse occurs within 255 BIT_CLK periods of the
frame start it will be ignored. SYNC is also used as an active
high input to perform an (asynchronous) Warm Reset. Warm
Reset is used to clear a power down state on the codec AC
Link interface.

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FLASH_AUDIO_ AD10 Cold Reset
RESET_N This active low signal causes a hardware reset which returns
the control registers and all internal circuits to their default

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conditions. RESET# must be used to initialize the LM4550
(resets registers to

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after Power On when the supplies have stabilized. Cold
default) Reset also clears the codec from both ATE and Vendor test
modes. In addition, while active, it switches the PC_BEEP

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mono input directly to both channels of the LINE_OUT ste-
reo output.
AC Link Serial Interface Protocol

1 Input/Output Frame = 13 time slots

= 1 Tag + 12 Data slots
= 16 bits + 12 x 20 bits
= 256 bits
= 48 KHz (max, default) repetition rate

Note: The PCM audio data are represented as

18-bit two’s complement numbers that are MSB
justified in their 20-bit slot

Note: The LM4550 expects to receive data MSB first, The time slots 5-12 are not used
in a MSB justified format. Set output bits to zero.

Sending Data to the AC97 (Playing a sound)

Perform the following steps (all bits are zero unless otherwise noted):

1. Set bit 15 (first bit sent in 16-bit TAG slot) of TAG data (slot 0) to ‘1’ to indicate that the frame
has at least one slot of valid data. This is bit 0 counting to 255. AUDIO_SYNC must be held

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high (‘1’) for the duration of the 16 clock cyles that comprise the TAG slot.
2. Set bit 12 of TAG data to ‘1’ to indicate that slot 3 has PCM data for the left channel. This is
bit 3 counting to 255.

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3. Set bit 11 of TAG data to ‘1’ to indicate that slot 4 has PCM data for the right channel. This is

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bit 4 counting to 255.
4. Insert the Left PCM data into slot 3. The 18-bit two’s complement number is sent MSB first
where bit 17 of the PCM data is sent as the first bit of slot 3 (bit 19). These are bits 56:73 count-

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ing to 255. The last two bits of slot 3 are set as zero (don’t care since the DACs are 18 bit and
only read the first 18 bits). These are bits 73:75 counting to 255. 10097206

5. Insert the Right PCM data into slot 4. This is done in a similar fashion to the left PCM data.
FIGURE 4. AC Link Output Frame
These are bits 76:93 counting to 255.
Reading Data from the AC97 (Recording a sound)

Perform the following steps:

1. Read bit 15 (first bit of the 16-bit TAG slot) of TAG status data (slot 0). A ‘1’ indicates the
AC Link interface is ready. This is bit 0 counting to 255.
2. Read bit 12 of TAG data. A ‘1’ to indicates that slot 3 has valid PCM data from the left chan-
nel. This is bit 3 counting to 255.
3. Read bit 11 of TAG data. A ‘1’ to indicates that slot 4 has valid PCM data from the right chan-
nel. This is bit 4 counting to 255.
4. Read the Left PCM data from slot 3. The 18-bit two’s complement number is sent MSB first
where the data is located in bits 19:2. These are bits 56:73 counting to 255.
5. Read the Right PCM data from slot 4. The 18-bit two’s complement number is sent MSB first
where the data is located in bits 19:2. These are bits 76:93 counting to 255.

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 Sending Commands to the AC97 (Writing to Registers)

Perform the following steps (all bits are zero unless otherwise noted):

1. Set bit 15 (first bit sent in 16-bit TAG slot) of TAG data (slot 0) to ‘1’ to indicate that the frame
has at least one slot of valid data. This is bit 0 counting to 255. AUDIO_SYNC must be held
high (‘1’) for the duration of the 16 clock cyles that comprise the TAG slot. Note: this is most
likely already being done when sending sound out.
2. Set bit 14 of TAG data to ‘1’ to indicate that slot 1 has the control address (register address).
This is bit 1 counting to 255.
3. Set bit 13 of TAG data to ‘1’ to indicate that slot 2 has the control data (register data). This is
bit 2 counting to 255.
4. Insert the control address into slot 1. First, set bit 19 to ‘0’ to indicate a write. The 7-bit reg-
ister address is then sent out in slot bits 18:12 of slot 1. These are bits 17:23 counting to 255.
The rest of the bits in the slot are set to zero.
5. Insert the register data into slot 2. The 16-bit register data is loaded into bits 19:4 of slot 2.
These are bits 36:51 counting to 255.

TAG Slot #0 Description (16 bits)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

VF CRA CRD LDD3 RDD4 NU LDD6 LDD7 RDD8 RDD9 NU NU NU NU ID1 ID0

Bit Description Function

15 VF Valid Frame 1 = Valid Data in at least one slot in frame
14 CRA Control Register Address 1 = Valid Control Address in Slot 1

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13 CRD Control Register Data 1 = Valid Control Data in Slot 2
12 LDD3 Left DAC Data in Slot 3 1 = Valid PCM Data in Slot 3 = Left Channel Audio

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11 RDD4 Right DAC Data in Slot 4

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10 NU Not Used
9 LDD6 Left DAC Data in Slot 6
8 LDD7 Left DAC Data in Slot 7

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7 RDD8 Right DAC Data in Slot 8
6 RDD9 Right DAC Data in Slot 9
5 NU Not Used
4 NU Not Used
3 NU Not Used
2 NU Not Used
1 ID1
0 ID0
The FPGA Pin # is the is the physical pin of the FPGA connected to the LM4550 I/O. An ex-
ample user constraint file (UCF) is given below:

NET “ac97_bit_clk” LOC = “AE10” ;

NET “ac97_input” LOC = “AD16” ;
NET “ac97_output” LOC = “C8” ;
NET “ac97_reset” LOC = “AD10” ;
NET “ac97_sync” LOC = “D9” ;
NET “sys_clk” LOC = “AE14” ;
NET “sys_rst” LOC = “D6” ;

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