Data Sheet

STM32F101x6
STM32F101x8 STM32F101xB
Access line, advanced ARM-based 32-bit MCU with Flash memory,
six 16-bit timers, ADC and seven communication interfaces
Preliminary Data
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 36 MHz, 45 DMIPS with 1.25 DMIPS/MHz
LQFP48 LQFP64 LQFP100
– Single-cycle multiplication and hardware 7 x 7 mm 10 x 10 mm 14 x 14 mm
division
– Temperature sensor
– Nested interrupt controller with 43
maskable interrupt channels ■ Up to 80 fast I/O ports
– Interrupt processing (down to 6 CPU – 32/49/80 5 V-tolerant I/Os
cycles) with tail chaining – All mappable on 16 external interrupt
vectors
■ Memories
– Atomic read/modify/write operations
– 32-to-128 Kbytes of Flash memory
– 6-to-16 Kbytes of SRAM ■ Up to 6 timers
■ Clock, reset and supply management – Up to three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 2.0 to 3.6 V application supply and I/Os
– 2 x 16-bit watchdog timers (Independent
– POR, PDR and programmable voltage
and Window)
detector (PVD)
– 4-to-16 MHz high-speed quartz oscillator – SysTick timer: 24-bit downcounter
– Internal 8 MHz factory-trimmed RC ■ Up to 7 communication interfaces
– Internal 32 kHz RC – Up to 2 x I2C interfaces (SMBus/PMBus)
– PLL for CPU clock – Up to 3 USARTs (ISO 7816 interface, LIN,
– Dedicated 32 kHz oscillator for RTC with IrDA capability, modem control)
calibration – Up to 2 SPIs (18 Mbit/s)
■ Low power
Table 1. Device summary
– Sleep, Stop and Standby modes
Reference Root part number
– VBAT supply for RTC and backup registers
STM32F101x6 STM32F101C6, STM32F101R6
■ Debug mode
STM32F101C8, STM32F101R8
– Serial wire debug (SWD) and JTAG STM32F101x8
STM32F101V8
interfaces
STM32F101xB STM32F101RB, STM32F101VB
■ DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
■ 12-bit, 1 µs A/D converter (16-channel)
– Conversion range: 0 to 3.6 V
July 2007 Rev 2 1/64

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.st.com 1
change without notice.
Contents STM32F101xx
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 26
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 27
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.7 Internal Clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 40
5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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STM32F101xx Contents
5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.1 Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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List of tables STM32F101xx
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Device features and peripheral counts (STM32F101xx access line) . . . . . . . . . . . . . . . . . . 7
Table 3. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Maximum current consumption in Run and Sleep modes (TA = 85 °C) . . . . . . . . . . . . . . . 28
Table 12. Maximum current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Typical current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Typical current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. High-speed user external (HSE) clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 17. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 21. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 22. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 24. Flash endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 25. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 26. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 27. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 28. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 29. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 30. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 31. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 32. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 33. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 34. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 35. SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 36. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 37. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 38. ADC accuracy (fPCLK2 = 10 MHz, fADC = 10 MHz, RAIN < 10 kΩ, VDDA = 3.3 V) . . . . . . . . 55
Table 39. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 40. LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 58
Table 41. LQFP64 – 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 59
Table 42. LQFP48 – 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 60
Table 43. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 44. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 45. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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STM32F101xx List of figures
List of figures
Figure 1. STM32F101xx access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. STM32F101xx access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. STM32F101xx access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. STM32F101xx access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Unused I/O pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 18. SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 19. SPI timing diagram - slave mode and CPHA=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 20. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 21. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 22. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 23. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 56
Figure 24. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 56
Figure 25. LQPF100 – 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 26. LQFP64 – 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 27. LQFP48 – 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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Introduction STM32F101xx
1 Introduction
This datasheet contains the description of the STM32F101xx access line family features,
pinout, Electrical Characteristics, Mechanical Data and Ordering information.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10x Flash Programming Reference Manual
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual.
2 Description
The STM32F101xx access line family incorporates the high-performance ARM Cortex™-M3
32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash
memory up to 128Kbytes and SRAM up to 16 Kbytes), and an extensive range of enhanced
peripherals and I/Os connected to two APB buses. All devices offer standard communication
interfaces (two I2Cs, two SPIs, and up to three USARTs), one 12-bit ADC and three general
purpose 16-bit timers.
The STM32F101 family operates in the −40 to +85°C temperature range, from a 2.0 to 3.6 V
power supply. A comprehensive set of power-saving mode allows to design low-power
applications.
The complete STM32F101xx access line family includes devices in 3 different package
types: from 48 pins to 100 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F101xx access line microcontroller family suitable for a
wide range of applications:
● Application control and user interface
● Medical and handheld equipment
● PC peripherals, gaming and GPS platforms
● Industrial applications: PLC, inverters, printers, and scanners
● Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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STM32F101xx Description
2.1 Device overview

Table 2. Device features and peripheral counts (STM32F101xx access line)
Peripheral STM32F101Cx STM32F101Rx STM32F101Vx
Flash - Kbytes 32 64 32 64 128 64 128
SRAM - Kbytes 6 10 6 10 16 10 16
Communication Timers
General purpose 2 3 3 3
SPI 1 2 1 2 2
2
I C 1 2 1 2 2
USART 2 3 2 3 3
12-bit synchronized ADC 1 1

number of channels 10 channels 16 channels
GPIOs 32 49 80
CPU frequency 36 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature -40 to +85 °C
Packages LQFP48 LQFP64 LQFP100
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Description STM32F101xx
2.2 Overview
ARM® CortexTM-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F101xx access line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Embedded Flash memory

Up to 128 Kbytes of embedded Flash is available for storing programs and data.
Embedded SRAM
Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)

The STM32F101xx access line embeds a nested vectored interrupt controller able to handle
up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)
and 16 priority levels.
● Closely coupled NVIC gives low latency interrupt processing
● Interrupt entry vector table address passed directly to the core
● Closely coupled NVIC core interface
● Allows early processing of interrupts
● Processing of late arriving higher priority interrupts
● Support for tail-chaining
● Processor state automatically saved
● Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
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External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detectors lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect external line with pulse
width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16
external interrupt lines.
Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is
monitored for failure. During such a scenario, it is disabled and software interrupt
management follows. Similarly, full interrupt management of the PLL clock entry is available
when necessary (for example with failure of an indirectly used external oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz.
Boot modes
At startup, boot pins are used to select one of five boot options:
● Boot from User Flash
● Boot from System Memory
● Boot from SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using the USART.
Power supply schemes

● VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
● VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
and PLL. In VDD range (ADC is limited at 2.4 V).
● VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded Programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The
interrupt service routine can then generate a warning message and/or put the MCU into a
safe state. The PVD is enabled by software.
Refer to Table 9: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
9/64
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
● MR is used in the nominal regulation mode (Run)
● LPR is used in the Stop modes
● Power down is used in Standby Mode: the regulator output is in high impedance: the
kernel circuitry is powered-down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after RESET. It is disabled in Standby Mode, providing high
impedance output.
Low-power modes
The STM32F101xx access line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode allows to achieve the lowest power consumption while retaining the content
of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI
and the HSE RC oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
● Standby mode
The Standby mode allows to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby
mode, SRAM and registers content are lost except for registers in the Backup domain
and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers
TIMx and ADC.
10/64
RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers (ten 16-bit registers)
can be used to store data when VDD power is not present.
The Real-Time Clock provides a set of continuously running counters which can be used
with suitable software to provide a clock calendar function, and provides an alarm interrupt
and a periodic interrupt. It is clocked by an external 32.768 kHz oscillator, the internal low
power RC oscillator or the high-speed external clock divided by 128. The internal low power
RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512Hz
output to compensate for any natural quartz deviation. The RTC features a 32-bit
programmable counter for long term measurement using the Compare register to generate
an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application time out
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0.
● Programmable clock source
General purpose timers (TIMx)

There are up to 3 synchronizable standard timers embedded in the STM32F101xx access
line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit
prescaler and feature 4 independent channels each for input capture, output compare, PWM
or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on
the largest packages. They can work together via the Timer Link feature for synchronization
or event chaining.
The counter can be frozen in debug mode.
Any of the standard timers can be used to generate PWM outputs. Each of the timers has
independent DMA request generations.
11/64
I²C bus
Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
GPIOs (general purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as Peripheral Alternate Function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
ADC (analog to digital converter)

The 12-bit Analog to Digital Converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature.
The conversion range is between 2V < VDDA < 3.6V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
12/64
Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Figure 1. STM32F101xx access line block diagram
Trace
JTAG & SWD pbus POWER
Controller
VDD = 2 to 3.6V
JNTRST VOLT. REG.
VSS
Flash obl
JTDI Cortex M3 CPU Ibus 3.3V TO 1.8V
Interface
FLASH 128 KB
JTCK/SWCLK
JTMS/SWDIO 64 bit @VDD
JTDO Fmax: 36 MHz Dbus
as AF NVIC
BusMatrix
SRAM
NVIC System
16 KB @VDD
PCLK1 OSC_IN
GP DMA PCLK2 PLL & XTAL OSC OSC_OUT
CLOCK 4-16 MHz
7 channels HCLK MANAGT
FCLK
AHB:Fmax=36 MHz
RC 8 MHz
IWDG
RC 32 kHz
@VDDA
Standby
@VDDA interface
SUPPLY VBAT
NRST SUPERVISION
@VBAT
VDDA POR / PDR Rst OSC32_IN
VSSA XTAL 32 kHz
OSC32_OUT
PVD Int
RTC Backup
AHB2 AHB2 reg ANTI_TAMP
APB2 APB1 AWU
Backup interface
EXTI
80AF
WAKEUP
TIM2 4 Channels
PA[15:0] GPIOA
TIM3 4 Channels
PB[15:0] GPIOB
TIM4 4 Channels
APB1 : Fmax=24 / 36 MHz
PC[15:0] GPIOC
RX,TX, CTS, RTS,
USART2
PD[15:0] GPIOD SmartCard as AF
RX,TX, CTS, RTS,
APB2 : Fmax= 36 MHz
USART3
PE[15:0] GPIOE SmartCard as AF
2x(8x16bit)SPI2
MOSI,MISO,SCK,NSS
as AF
MOSI,MISO, I2C1 SCL,SDA,SMBAL

SCK,NSS as AF SPI1 as AF
I2C2 SCL,SDA
RX,TX, CTS, RTS,
as AF
SmartCard as AF USART1
@VDDA
16AF
VREF+ 12bit ADC1 IF WWDG
VREF-
Temp sensor
ai14385
1. AF = alternate function on I/O port pin.

2. TA = –40 °C to +85 °C (junction temperature up to 125 °C).
13/64
Pin descriptions STM32F101xx
3 Pin descriptions
Figure 2. STM32F101xx access line LQFP100 pinout
BOOT0
VDD_3
VSS_3
PC12
PC11
PC10
PA15
PA14
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD_2
PE3 2 74 VSS_2
PE4 3 73 NC
PE5 4 72 PA 13
PE6 5 71 PA 12
VBAT 6 70 PA 11
PC13-ANTI_TAMP 7 69 PA 10
PC14-OSC32_IN 8 68 PA 9
PC15-OSC32_OUT 9 67 PA 8
VSS_5 10 66 PC9
VDD_5 11 65 PC8
OSC_IN 12
LQFP100 64 PC7
OSC_OUT 13 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0-WKUP 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA3
VSS_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
VDD_4
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
ai14386
14/64
STM32F101xx Pin descriptions
BOOT0
VDD_3
VSS_3
PC12
PC11
PC10
PA15
PA14
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT 1 48 VDD_2
PC13-ANTI_TAMP 2 47 VSS_2
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PD0 OSC_IN 5 44 PA11
PD1 OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9
LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0-WKUP 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PA3
VSS_4
PC5
VDD_4
PA4
PA5
PA6
PA7
PC4
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
ai14387

BOOT0
VDD_3
VSS_3
PA15
PA14
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48 47 46 45 44 43 42 41 40 39 38 37
VBAT 1 36 VDD_2
PC13-ANTI_TAMP 2 35 VSS_2
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PD0 OSC_IN 5 32 PA11
PD1 OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0-WKUP 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
ai14378
15/64
Table 3. Pin definitions

Pins
I / O level(2)
Main
Type(1)
LQFP100
LQFP48
LQFP64
Pin name function(3) Default alternate functions(3)

(after reset)
- - 1 PE2/TRACECK I/O FT PE2 TRACECK

- - 2 PE3/TRACED0 I/O FT PE3 TRACED0
1 1 6 VBAT S VBAT
2 2 7 PC13-ANTI_TAMP(4) I/O PC13 ANTI_TAMP
PC14-
3 3 8 PC14-OSC32_IN(4) I/O
OSC32_IN
PC15-
4 4 9 PC15-OSC32_OUT(4) I/O
OSC32_OUT
- - 10 VSS_5 S VSS_5
- - 11 VDD_5 S VDD_5
5 5 12 OSC_IN I OSC_IN
6 6 13 OSC_OUT O OSC_OUT
7 7 14 NRST I/O NRST
- 8 15 PC0/ADC_IN10 I/O PC0 ADC_IN10
8 12 19 VSSA S VSSA
- - 20 VREF- S VREF-
- - 21 VREF+ S VREF+
9 13 22 VDDA S VDDA
PA0-WKUP/USART2_CTS/ WKUP/USART2_CTS(7)/ ADC_IN0/
10 14 23 I/O PA0
ADC_IN0/TIM2_CH1_ETR TIM2_CH1_ETR(7)
PA1/USART2_RTS/ADC_ USART2_RTS(7)/ADC_IN1/
11 15 24 I/O PA1
IN1/TIM2_CH2 TIM2_CH2(7)
PA2/USART2_TX/ADC_IN2/ USART2_TX(7)/ADC_IN2/
12 16 25 I/O PA2
TIM2_CH3 TIM2_CH3(7)
PA3/USART2_RX/ADC_IN3/ USART2_RX(7)/ADC_IN3/
13 17 26 I/O PA3
- 18 27 VSS_4 S VSS_4
- 19 28 VDD_4 S VDD_4
16/64
Table 3. Pin definitions (continued)

Pins
I / O level(2)
Main
Type(1)
LQFP100
LQFP48
LQFP64

(after reset)
PA4/SPI1_NSS/ SPI1_NSS/USART2_CK(7)/
14 20 29 I/O PA4
USART2_CK/ADC_IN4 ADC_IN4
15 21 30 PA5/SPI1_SCK/ADC_IN5 I/O PA5 SPI1_SCK/ADC_IN5
PA6/SPI1_MISO/ADC_IN6/ SPI1_MISO/ADC_IN6/
16 22 31 I/O PA6
PA7/SPI1_MOSI/ADC_IN7/ SPI1_MOSI/ADC_IN7/
17 23 32 I/O PA7
18 26 35 PB0/ADC_IN8/TIM3_CH3 I/O PB0 ADC_IN8/TIM3_CH3(7)
19 27 36 PB1/ADC_IN9/TIM3_CH4 I/O PB1 ADC_IN9/TIM3_CH4(7)
20 28 37 PB2/BOOT1 I/O FT PB2/BOOT1
- - 38 PE7 I/O FT PE7
- - 39 PE8 I/O FT PE8
- - 40 PE9 I/O FT PE9
- - 41 PE10 I/O FT PE10
- - 42 PE11 I/O FT PE11
- - 43 PE12 I/O FT PE12
- - 44 PE13 I/O FT PE13
- - 45 PE14 I/O FT PE14
- - 46 PE15 I/O FT PE15
PB10/I2C2_SCL
21 29 47 I/O FT PB10 I2C2_SCL(5)/USART3_TX(5) (7)
USART3_TX
PB11/I2C2_SDA
22 30 48 I/O FT PB11 I2C2_SDA(5)/USART3_RX(5) (7)
USART3_RX
23 31 49 VSS_1 S VSS_1
24 32 50 VDD_1 S VDD_1
PB12/SPI2_NSS/ SPI2_NSS(5) (7)/I2C2_SMBAl(5)/
25 33 51 I/O FT PB12
I2C2_SMBAl/USART3_CK USART3_CK(5) (7)
PB13/SPI2_SCK/
26 34 52 I/O FT PB13 SPI2_SCK(5)(7)/USART3_CTS(5)(7)
USART3_CTS
PB14/SPI2_MISO/
27 35 53 I/O FT PB14 SPI2_MISO(5)(7)/USART3_RTS(5)(7)
USART3_RTS
28 36 54 PB15/SPI2_MOSI I/O FT PB15 SPI2_MOSI(5) (7)
- - 55 PD8 I/O FT PD8
17/64

Pins
I / O level(2)
Main
Type(1)
LQFP100
LQFP48
LQFP64

(after reset)
- - 56 PD9 I/O FT PD9

- - 57 PD10 I/O FT PD10
- - 58 PD11 I/O FT PD11
- - 59 PD12 I/O FT PD12
- - 60 PD13 I/O FT PD13
- - 61 PD14 I/O FT PD14
- - 62 PD15 I/O FT PD15
- 37 63 PC6 I/O FT PC6
38 64 PC7 I/O FT PC7
39 65 PC8 I/O FT PC8
- 40 66 PC9 I/O FT PC9
29 41 67 PA8/USART1_CK/MCO I/O FT PA8 USART1_CK/MCO
30 42 68 PA9/USART1_TX I/O FT PA9 USART1_TX(7)
31 43 69 PA10/USART1_RX I/O FT PA10 USART1_RX(7)
32 44 70 PA11/USART1_CTS I/O FT PA11 USART1_CTS
33 45 71 PA12/USART1_RTS I/O FT PA12 USART1_RTS
34 46 72 PA13/JTMS/SWDIO I/O FT JTMS-SWDIO PA13
- - 73 Not connected
35 47 74 VSS_2 S VSS_2
36 48 75 VDD_2 S VDD_2
37 49 76 PA14/JTCK/SWCLK I/O FT JTCK/SWCLK PA14
38 50 77 PA15/JTDI I/O FT JTDI PA15
- 51 78 PC10 I/O FT PC10
- 52 79 PC11 I/O FT PC11
- 53 80 PC12 I/O FT PC12
5 5 81 PD0 I/O FT OSC_IN(6)
6 6 82 PD1 I/O FT OSC_OUT(6)
54 83 PD2/TIM3_ETR I/O FT PD2 TIM3_ETR
- - 84 PD3 I/O FT PD3
- - 85 PD4 I/O FT PD4
- - 86 PD5 I/O FT PD5
- - 87 PD6 I/O FT PD6
18/64

Pins
I / O level(2)
Main
Type(1)
LQFP100
LQFP48
LQFP64

(after reset)
- - 88 PD7 I/O FT PD7

39 55 89 PB3/JTDO/TRACESWO I/O FT JTDO PB3/TRACESWO
40 56 90 PB4/JNTRST I/O FT JNTRST PB4
41 57 91 PB5/I2C1_SMBAl I/O PB5 I2C1_SMBAl
42 58 92 PB6/I2C1_SCL/TIM4_CH1 I/O FT PB6 I2C1_SCL(7)/TIM4_CH1(5) (7)
43 59 93 PB7/I2C1_SDA/TIM4_CH2 I/O FT PB7 I2C1_SDA(7)/TIM4_CH2(5) (7)
44 60 94 BOOT0 I BOOT0
45 61 95 PB8/TIM4_CH3 I/O FT PB8 TIM4_CH3(5) (7)
46 62 96 PB9/TIM4_CH4 I/O FT PB9 TIM4_CH4(5) (7)
- - 97 PE0/TIM4_ETR I/O FT PE0 TIM4_ETR(5)
- - 98 PE1 I/O FT PE1
47 63 99 VSS_3 S VSS_3
48 64 100 VDD_3 S VDD_3
1. I = input, O = output, S = supply, HiZ= high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. Refer to Table 2 on page 7.
4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.
6. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
however the functionality of PD0 and PD1 can be remapped by software on these pins.
7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
UM0306, available from the STMicroelectronics website: www.st.com.
19/64
Memory mapping STM32F101xx
4 Memory mapping
The memory map is shown in Figure 5.
Figure 5. Memory map

APB memory space
0xFFFF FFFF
reserved
0xE010 0000
reserved
0x6000 0000
reserved 4K
0x4002 3400
reserved 1K
0xFFFF FFFF 0x4002 3000
reserved 3K
0x4002 2400
0xFFFF F000
0x4002 2000 Flash interface 1K
7 0x4002 1400 reserved 3K

RCC 1K
0xE010 0000 0x4002 1000
Cortex-M3 internal 3K
0xE000 0000 peripherals 0x4002 0400 reserved
DMA 1K
0x4002 0000
reserved 1K
6
0x4001 3C00
USART1 1K
0x4001 3800
0xC000 0000 reserved 1K
0x4001 3400
SPI1 1K
0x4001 3000
reserved 1K
0x4001 2C00
5 reserved 1K
0x4001 2800
ADC1 1K
0xA000 0000 0x4001 2400
reserved 2K
0x4001 1C00
Port E 1K
4 0x1FFF FFFF 0x4001 1800
reserved Port D 1K
0x1FFF F9FF 0x4001 1400
Port C 1K
0x8000 0000 0x4001 1000
Option bytes 1K
0x1FFF F800 0x4001 0C00 Port B
0x4001 0800 Port A 1K
3 System memory 0x4001 0400 EXTI 1K
0x4001 0000 AFIO 1K

0x1FFF F000
0x6000 0000 reserved 35K
0x4000 7400
PWR 1K
0x4000 7000
2 BKP 1K
0x4000 6C00
reserved 1K
reserved 0x4000 6800
Peripherals reserved
0x4000 0000 0x4000 6400 1K
reserved 1K
0x4000 6000
reserved 1K
0x4000 5C00
1 I2C2 1K
0x4000 5800
0x4000 5400 I2C1 1K
SRAM
0x2000 0000
0x0801 FFFF reserved 2K
0x4000 4C00
0x4000 4800 USART3 1K
0 Flash memory
0x4000 4400 USART2 1K
Code 0x0800 0000

0x0000 0000 reserved 2K
0x4000 3C00
SPI2 1K
0x4000 3800
reserved 1K
Reserved 0x4000 3400
IWDG 1K
0x4000 3000
0x4000 2C00 WWDG 1K
0x4000 2800 RTC 1K
reserved 7K
0x4000 0C00
0x4000 0800 TIM4 1K
0x4000 0400 TIM3 1K
0x4000 0000 TIM2 1K

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20/64
STM32F101xx Electrical characteristics
5 Electrical characteristics
5.1 Test conditions

Unless otherwise specified, all voltages are referred to VSS.
5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 6.
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 7.
21/64
Electrical characteristics STM32F101xx
Figure 6. Pin loading conditions Figure 7. Pin input voltage
STM32F101 PIN STM32F101 PIN
C=50pF VIN
ai14123 ai14124
5.1.6 Power supply scheme
Figure 8. Power supply scheme
VBAT 3.3 V
Backup circuitry
Po wer swi tch (OSC32K,RTC,
1.8-3.6V
Wake-up logic
Backup registers)
Level shifter
OUT
IO
GP I/Os Logic
IN Kernel logic
(CPU,
Digital
VDD
VDD & Memories)
1/2/3/4/5 Regulator
5 × 100 nF VSS
+ 1 × 10 µF 1/2/3/4/5
3.3V
VDD
VDDA
VREF
VREF+
10 nF Analog:
10 nF VREF- ADC
+ 1 µF RCs, PLL,
+ 1 µF
...
VSSA
ai14125
22/64
5.1.7 Current consumption measurement
Figure 9. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
23/64
5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics,
Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 4. Voltage characteristics

Symbol Ratings Min Max Unit
External 3.3 V supply voltage (including

VDD−VSS −0.3 4.0
VDDA and VDD)(1)
V
Input voltage on five volt tolerant pin(2) VSS −0.3 +5.5
VIN
Input voltage on any other pin(2) VSS − 0.3 VDD+0.3
|∆VDDx| Variations between different power pins 50 50
Variations between all the different ground mV
|VSSX − VSS| 50 50
pins
see Section 5.3.11: Absolute
Electrostatic discharge voltage (human
VESD(HBM) maximum ratings (electrical
body model)
sensitivity)
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
supply.
2. IINJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is
induced by VIN<VSS.
Table 5. Current characteristics

Symbol Ratings Max. Unit
IVDD Total current into VDD power lines (source)(1) 150

IVSS Total current out of VSS ground lines (sink)(1) 150
Output current sunk by any I/O and control pin 25
IIO
Output current source by any I/Os and control pin −25
Injected current on NRST pin ±5 mA
Injected current on High-speed external OSC_IN and Low-

IINJ(PIN) (2)(3) ±5
speed external OSC_IN pins
Injected current on any other pin(4) ±5
ΣIINJ(PIN)(2) Total injected current (sum of all I/O and control pins)(4) ± 25
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V
supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC
characteristics.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
24/64
Table 6. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature (see Thermal characteristics)
25/64
5.3 Operating conditions
5.3.1 General operating conditions
Table 7. General operating conditions

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency 0 36

fPCLK1 Internal APB1 clock frequency 0 36 MHz
fPCLK2 Internal APB2 clock frequency 0 36
VDD Standard operating voltage 2 3.6 V
VBAT Backup operating voltage 1.8 3.6 V
TA Ambient temperature range −40 85 °C
5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 8 are derived from tests performed under the ambient
temperature condition summarized in Table 7.
Table 8. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Typ Max Unit
20 µs/V
tVDD VDD rise/fall time
20 ms/V
26/64
5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 9 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 7.
.
Table 9. Embedded reset and power control block characteristics
PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V

PLS[2:0]=000 (falling edge) 2 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V
Programmable voltage PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V

VPVD
detector level selection PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3 V
VPVDhyst PVD hysteresis 100 mV
Power on/power down reset Falling edge 1.8 1.88 1.96 V

VPOR/PDR
threshold Rising edge 1.84 1.92 2.0 V
VPDRhyst PDR hysteresis 40 mV
tRSTTEMPO Reset temporization 1.5 2.5 3.5 ms
5.3.4 Embedded reference voltage

Table 10. Embedded internal reference voltage

VREFINT Internal reference voltage -45 °C < TA < +85 °C 1.16 1.20 1.24 V
27/64
5.3.5 Supply current characteristics

The current consumption is measured as described in Figure 9: Current consumption
measurement scheme.
Maximum current consumption

The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at VDD or VSS (no load)
● All peripherals are disabled except if it is explicitly mentioned
● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 36 MHz)
Table 11. Maximum current consumption in Run and Sleep modes (TA = 85 °C)(1)
Symbol Parameter Conditions FHCLK Typ (2) Max(3) Unit
External clock with PLL, code running from 36 MHz 22 TBD

Flash, all peripherals enabled (see RCC register
description): fPCLK1= fHCLK/2, fPCLK2=fHCLK 24 MHz 21 TBD
External clock, PLL stopped, code running from

Flash, all peripherals enabled (see RCC register 8 MHz 10 TBD
Supply current in description): fPCLK1= fHCLK/2, fPCLK2=fHCLK
Run mode
External clock with PLL, code running from RAM, 36 MHz 13 18
all peripherals enabled (see RCC register
description): fPCLK1= fHCLK/2, fPCLK2=fHCLK 24 MHz 11 15
IDD External clock, PLL stopped, code running from mA

RAM, all peripherals enabled (see RCC register 8 MHz 4.5 TBD
description): fPCLK1= fHCLK/2, fPCLK2=fHCLK
External clock with PLL, code running from RAM 36 MHz 13 22
or Flash, all peripherals enabled (see RCC
register description): fPCLK1= fHCLK/2, 24 MHz 10 17
Supply current in fPCLK2=fHCLK
Sleep mode External clock, PLL stopped, code running from
RAM or Flash, all peripherals enabled (see RCC
8 MHz 3.5 TBD
register description): fPCLK1= fHCLK/2,
fPCLK2=fHCLK
1. TBD stands for to be determined.
2. Typical values are measured at TA = 25 °C, and VDD = 3.3 V.
3. Data based on characterization results, tested in production at VDmax, fHCLK max. TAmax, and code executed from RAM.
28/64
Table 12. Maximum current consumption in Stop and Standby modes(1)

Typ(2) Max(3)
Symbol Parameter Conditions Unit
VDD/ VBAT VDD/VBAT
TA = 85 °C
= 2.4 V = 3.3 V
Regulator in Run mode,

Low-speed and high-speed internal
RC oscillators and high-speed TBD 24 TBD
oscillator OFF (no independent
Supply current in watchdog)
Stop mode Regulator in Low Power mode,
IDD Low-speed and high-speed internal
RC oscillators and high-speed TBD(4) 14(4) TBD(4) µA
oscillator OFF (no independent
watchdog)
Low-speed internal RC oscillator and
Supply current in
independent watchdog OFF, low- TBD(4) 2(4) TBD(4)
Standby mode(5)
speed oscillator and RTC OFF
IDD_VBA Backup domain
Low-speed oscillator and RTC ON 1(4) 1.4(4) TBD(4)
T supply current
2. Typical values are measured at TA = 25 °C, VDD = 3.3 V, unless otherwise specified.
3. Data based on characterization results, tested in production at VDD max, fHCLK max. and TA max.
4. Values expected for next silicon revision.
5. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when
VDD is present the Backup Domain is powered by VDD supply).
29/64
Typical current consumption

The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at VDD or VSS (no load)
● All peripherals are disabled except if it is explicitly mentioned
● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 36 MHz)
Table 13. Typical current consumption in Run and Sleep modes(1)

Symbol Parameter Conditions fHCLK Typ(2) Unit
36 MHz TBD
Oscillator running at 8 MHz with PLL, code running
from Flash, all peripheral disabled (see RCC register 24 MHz 13 mA
description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK
16 MHz TBD
8 MHz 7.8
4 MHz 7
Running on HSI clock, code running from Flash, all
peripheral disabled (see RCC register description): 2 MHz 6.3
mA
fPCLK1= fHCLK/2, fPCLK2 = fHCLK. AHB pre-scaler used 1 MHz 6.2
Supply current in to reduce the frequency
500 kHz 6.1
Run mode
125 kHz 5.95
8 MHz 2.3
4 MHz 1.6
Running on HSI clock, code running from RAM, all
IDD peripheral disabled (see RCC register description): 2 MHz 1.2
mA
fPCLK1= fHCLK/2, fPCLK2 = fHCLK. AHB pre-scaler used 1 MHz 1
to reduce the frequency
500 kHz 0.88
125 kHz 0.82
36 MHz TBD
Oscillator running at 8 MHz with PLL, code running
from Flash, all peripheral disabled (see RCC register 24 MHz TBD mA
description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK
16 MHz 1
Supply current in 8 MHz TBD

Sleep mode Running on HSI clock, code running from Flash, all 4 MHz TBD
peripheral disabled (see RCC register description):
2 MHz TBD mA
fPCLK1= fHCLK/2, fPCLK2 = fHCLK. AHB pre-scaler used
to reduce the frequency 1 MHz TBD
500 kHz TBD
2. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
30/64
Table 14. Typical current consumption in Stop and Standby modes(1)

Symbol Parameter Conditions VDD Typ(2) Unit
Regulator in Run mode, 3.3 V 24

Low-speed and high-speed internal RC
oscillators OFF
High-speed oscillator OFF (no 2.4 V TBD
Supply current in Stop independent watchdog)
µA
mode Regulator in Low Power mode, 3.3 V 14(3)
Low-speed and high-speed internal RC
oscillators OFF,
High-speed oscillator OFF (no 2.4 V TBD(3)
IDD independent watchdog)
Low-speed internal RC oscillator and 3.3 V 2(3)

independent watchdog OFF 2.4 V TBD(3)
Supply current in Low-speed internal RC oscillator and 3.3 V 3.1(3)

µA
Standby mode(4) independent watchdog ON 2.4 V TBD(3)
Low-speed internal RC oscillator ON, 3.3 V 2.9(3)

independent watchdog OFF 2.4 V TBD(3)
3.3 V 1.4(3)
Low-speed oscillator and RTC ON
Backup domain 2.4 V 1(3)
IDD_VBAT µA
supply current 3.3 V 0.5(3)
Low-speed oscillator OFF, RTC ON
2.4 V TBD(3)
2. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
3. Values expected for next silicon revision.
4. To obtain Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator, RTC ON) to IDD Standby.
31/64
5.3.6 External clock source characteristics

High-speed user external clock
The characteristics given in Table 15 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 7.
Table 15. High-speed user external (HSE) clock characteristics

User external clock source

fHSE_ext 8 25 MHz
frequency(1)
OSC_IN input pin high level
VHSEH 0.7VDD VDD
voltage
V
OSC_IN input pin low level
VHSEL VSS 0.3VDD
voltage
tw(HSE)
OSC_IN high or low time(1) 16
tw(HSE)
ns
tr(HSE)
OSC_IN rise or fall time(1) 5
tf(HSE)
OSC_IN Input leakage
IL VSS ≤ VIN ≤ VDD ±1 µA
current
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
Low-speed user external clock

The characteristics given in Table 16 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
Table 16. Low-speed user external clock characteristics

User external clock source

fLSE_ext 32.768 1000 kHz
frequency(1)
OSC32_IN input pin high level
VLSEH 0.7VDD VDD
voltage
V
OSC32_IN input pin low level
VLSEL VSS 0.3VDD
voltage
tw(LSE)
OSC32_IN high or low time(1) 450
tw(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time(1) 5
tf(LSE)
OSC32_IN Input leakage
IL VSS ≤ VIN ≤ VDD ±1 µA
current
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
32/64
Figure 10. High-speed external clock source AC timing diagram
VHSEH
90%
10%
VHSEL
tr(HSE) tW(HSE) t
tf(HSE) tW(HSE)
THSE
EXTER NAL fHSE_ext

IL
CLOCK SOURC E OSC _IN
STM32F101
ai14127
Figure 11. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
tr(LSE) tW(LSE) t
tf(LSE) tW(LSE)
TLSE
EXTER NAL fLSE_ext

OSC32_IN IL
CLOCK SOURC E
STM32F101
ai14140b
33/64
High-speed external clock

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 17. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 17. HSE 4-16 MHz oscillator characteristics(1)

fOSC_IN Oscillator frequency 4 8 16 MHz

RF Feedback resistor 200 kΩ
Recommended load capacitance
CL1
versus equivalent serial RS = 30 Ω 30 pF
CL2(2)
resistance of the crystal (RS)(3)
VDD = 3.3 V
i2 HSE driving current VIN = VSS with 30 pF 1 mA
load
gm Oscillator transconductance Startup 25 mA/V
tSU(HSE)
(4) Startup time VSS is stabilized 2 ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.),
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board
capacitance).
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Figure 12. Typical application with an 8 MHz crystal
RESONATOR WITH
IN TEGRATED CAPAC ITORS
CL1
OSC_IN fHSE
Bias
8 MH z controlled
RF
resonator gain
OSC_OU T STM32F101xx
CL2 REXT(1)
ai14128
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
34/64
Low-speed external clock

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 18. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 18. LSE oscillator characteristics (fLSE = 32.768 kHz)

RF Feedback resistor 5 MΩ
Recommended load capacitance
CL1
versus equivalent serial RS = 30 KΩ 15 pF
CL2
resistance of the crystal (RS)(1)
VDD = 3.3 V
I2 LSE driving current 1.4 µA
VIN = VSS
gm Oscillator transconductance 5 µA/V
tSU(LSE)(2) Startup time VSS is stabilized 3 s
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Figure 13. Typical application with a 32.768 kHz crystal
RESONATOR WITH
IN TEGRATED CAPAC ITORS
CL1
OSC32_IN fLSE
Bias
32.768 KH z controlled
RF
resonator gain
OSC32_OU T STM32F101xx
CL2
ai14129
35/64
5.3.7 Internal Clock source characteristics

High-speed internal (HSI) RC oscillator
Table 19. HSI oscillator characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max(3) Unit
fHSI Frequency 8 MHz

TA = –40 to 85 °C TBD ±3 TBD %
ACCHSI Accuracy of HSI oscillator
at TA = 25 °C TBD ±1 TBD %
tsu(HSI) HSI oscillator startup time 1 2 µs
HSI oscillator power
IDD(HSI) 80 100 µA
consumption
1. VDD = 3.3 V, TA = −40 to 85 °C unless otherwise specified.
3. Values based on device characterization, not tested in production.
LSI Low Speed Internal RC Oscillator
Table 20. LSI oscillator characteristics (1)

fLSI Frequency 30 60 kHz

tsu(LSI) LSI oscillator start up time 85 µs
LSI oscillator power
IDD(LSI) 0.65 1.2 µA
consumption
1. VDD = 3 V, TA = −40 to 85 °C unless otherwise specified.
2. Value based on device characterization, not tested in production.
36/64
Wakeup time from low power mode

The wakeup times given in Table 21 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
● Stop or Standby mode: the clock source is the RC oscillator
● Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 7.
Table 21. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Typ Max Unit
tWUSLEEP(2) Wakeup from Sleep mode Wakeup on HSI RC clock 0.75 TBD µs
Wakeup from Stop mode

HSI RC wakeup time = 2 µs 4 TBD
(regulator in run mode)
tWUSTOP(2) HSI RC wakeup time = 2 µs, µs
Wakeup from Stop mode
Regulator wakeup from LP 7 TBD
(regulator in low power mode)
mode time = 5 µs
HSI RC wakeup time = 2 µs,
tWUSTDBY(3) Wakeup from Standby mode Regulator wakeup from power 40 TBD µs
down time = 38 µs
2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which
the user application code reads the first instruction.
3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device
exits from reset.
5.3.8 PLL characteristics

Table 22. PLL characteristics(1)

Value
Test
Symbol Parameter Unit
conditions
Min Typ Max(2)
PLL input clock 8.0 MHz

fPLL_IN
PLL input clock duty cycle 40 60 %
fPLL_OUT PLL multiplier output clock 16 36 MHz
tLOCK PLL lock time 200 µs
Cycle to cycle jitter (+/-3Σ peak to
tJITTER VDD is stable TBD TBD %
peak)
2. Data based on device characterization, not tested in production.
37/64
5.3.9 Memory characteristics

Flash memory
The characteristics are given at TA = −40 to 85 °C unless otherwise specified.
Table 23. Flash memory characteristics(1)

tprog Word programming time TA = −40 to +85 °C 20 40 µs

tERASE Page (1kB) erase time TA = −40 to +85 °C 20 40 ms
tME Mass erase time TA = −40 to +85 °C 20 40 ms
Read mode
fHCLK = 36MHz with
20 mA
2 wait states, VDD =
3.3 V
Write / Erase modes
IDD Supply current
fHCLK = 36 MHz, 5 mA
VDD = 3.3 V
Power-down mode /
HALT, 50 µA
VDD=3.0 to 3.6 V
2. Values based on characterization and not tested in production.
Table 24. Flash endurance and data retention

Value
Min(1) Typ Max
NEND Endurance 1 10 kcycles

tRET Data retention TA = 85° C 30 Years
1. Values based on characterization not tested in production.
38/64
5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
● Electrostatic Discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard.
● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 25. They are based on the EMS levels and classes
defined in application note AN1709.
Table 25. EMS characteristics(1)

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, TA=+25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHCLK = 36 MHz TBD
induce a functional disturbance
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA=+25 °C,
VEFTB applied through 100pF on VDD and VSS pins fHCLK = 36 MHz 4A
to induce a functional disturbance conforms to IEC 1000-4-4
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
● Corrupted program counter
● Unexpected reset
● Critical Data corruption (control registers...)
39/64
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J
1752/3 standard which specifies the test board and the pin loading.
Table 26. EMI characteristics(1)

Max vs.
Monitored [fHSE/fHCLK]
frequency band
8/36 MHz
0.1 MHz to 30 MHz TBD

VDD = 3.3 V, TA = 2 5°C, 30 MHz to 130 MHz TBD dBµV
SEMI Peak level LQFP100 package compliant
with SAE J 1752/3 130 MHz to 1GHz TBD
SAE EMI Level TBD -
5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size is
either 3 parts (cumulative mode) or 3 parts × (n + 1) supply pins (non-cumulative mode).
The human body model (HBM) can be simulated. The tests are compliant with JESD22-
A114A standard.
For more details, refer to the application note AN1181.
Table 27. ESD absolute maximum ratings(1)

Symbol Ratings Conditions Maximum value(2) Unit
Electrostatic discharge voltage (human

VESD(HBM) 2000
body model)
TA = +25 °C V
Electrostatic discharge voltage (charge
VESD(CDM) TBD
device model)
2. Values based on characterization results, not tested in production.
40/64
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin
● A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.
Table 28. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C II level A
41/64
5.3.12 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 29 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7.
All unused pins must be held at a fixed voltage, by using the I/O output mode, an external
pull-up or pull-down resistor (see Figure 14).
Table 29. I/O static characteristics(1)

VIL Input low level voltage(2) –0.5 0.8

IO TC input high level V
TTL ports 2 VDD+0.5
VIH voltage(2)
IO FT high level voltage(2) 2 5.5V
VIL Input low level voltage(2) –0.5 0.35 VDD
CMOS ports V
VIH Input high level voltage(2) 0.65 VDD VDD+0.5
IO TC Schmitt trigger voltage
200 mV
hysteresis(3)
Vhys
IO TC Schmitt trigger voltage
5% VDD(4) mV
hysteresis(3)
VSS ≤VIN ≤VDD
±1
Standard I/Os
(4)
Ilkg Input leakage current µA
VIN = 5 V
3
5 V tolerant I/Os
Weak pull-up equivalent
RPU VIN = VSS 30 40 50 kΩ
resistor(5)
Weak pull-down equivalent
RPD VIN = VDD 30 40 50 kΩ
resistor(6)
CIO I/O pin capacitance 5 pF
1. VDD = 3.3 V, TA = −40 to 85 °C unless otherwise specified.
2. Values based on characterization results, and not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. With a minimum of 100 mV.
5. Leakage could be higher than max. if negative current is injected on adjacent pins.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
42/64
Figure 14. Unused I/O pin connection
VDD
1 0 kΩ
STM32F101
UNU SED I/O PORT
STM32F101
UNU SED I/O PORT
10 kΩ
ai14130
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed VOL).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 5).
● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 5).
43/64
Output voltage levels

Table 7.
Table 30. Output voltage characteristics

Output Low level voltage for an I/O pin

VOL(1) TTL port, IIO = 0.4
when 8 pins are sunk at same time
+8 mA, V
Output High level voltage for an I/O pin 2.7 V < VDD < 3.6 V
VOH(2) VDD–0.4
when 4 pins are sourced at same time
Output low level voltage for an I/O pin
VOL(1) CMOS port 0.4
when 8 pins are sunk at same time
IIO = +8 mA V
Output high level voltage for an I/O pin
VOH(2) 2.7 V < VDD < 3.6 V 2.4
VOL(1) 1.3
when 8 pins are sunk at same time IIO = +20 mA
V
(2) Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V
VOH VDD–1.3
VOL(1) 0.4
when 8 pins are sunk at same time IIO = +6 mA
V
Output high level voltage for an I/O pin 2 V < VDD < 2.7 V
VOH(2) VDD–0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 5
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 15 and
Table 31, respectively.
Table 7.
Table 31. I/O AC characteristics(1)

I/O
Symbol Parameter Conditions Max Unit
mode(1)
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 2 MHz

Output high to low level fall
tf(IO)out 125
10 time(3)
CL = 50 pF, VDD = 2 V to 3.6 V ns
Output low to high level rise
tr(IO)out 125
time(3)
fmax(IO)out Maximum frequency(2) CL= 50 pF, VDD = 2 V to 3.6 V 10 MHz
tf(IO)out 25
01 time(3)
CL= 50 pF, VDD = 2 V to 3.6 V ns
tr(IO)out 25
time(3)
CL= 30 pF, VDD = 2.7 V to 3.6 V 50 MHz
Fmax(IO)out Maximum Frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz
CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V 5
11 tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V 8
time(3)
CL = 50 pF, VDD = 2 V to 2.7 V 12
ns
CL = 30 pF, VDD = 2.7 V to 3.6 V 5
tr(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V 8
time(3)
CL = 50 pF, VDD = 2 V to 2.7 V 12
Pulse width of external signals
- tEXTIpw 10 ns
detected by the EXTI controller
1. Refer to the Reference user manual UM0306 for a description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 15.
3. Values based on design simulation and validated on silicon, not tested in production.
45/64
Figure 15. I/O AC characteristics definition
90% 10%
50% 50%
10% 90%
EXT ERNAL tr(I O)out tr(I O)out

OUTPUT
ON 50pF T
Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
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46/64
5.3.13 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 29).
Table 7.
Table 32. NRST pin characteristics(1)

VIL(NRST) NRST Input low level voltage –0.5 0.8

V
VIH(NRST) NRST Input high level voltage 2 VDD+0.5
NRST Schmitt trigger voltage
Vhys(NRST) 200
hysteresis
RPU Weak pull-up equivalent resistor(2) VIN = VSS 30 40 50 kΩ
VF(NRST) NRST Input filtered pulse(3) 100 ns
VNF(NRST) (3)
NRST Input not filtered pulse 300 µs
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
3. Values guaranteed by design, not tested in production.
Figure 16. Recommended NRST pin protection
VDD
External
reset circuit
RPU Internal Reset
NRST
FILTER
0.1 µF
STM32F101xx
ai14132b
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 32. Otherwise the reset will not be taken into account by the device.
47/64
5.3.14 TIM timer characteristics

performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 33. TIMx characteristics

Symbol Parameter TIMx(1) Conditions Min Max Unit
1 tTIMxCLK
Timer resolution
tres(TIM) x = 2, 3, 4
time fTIMxCLK = 36 MHz 27.8 ns
Timer external clock 0 fTIMxCLK/2 MHz
fEXT frequency on CH1 to x = 2, 3, 4
CH4 fTIMxCLK = 36 MHz 0 18 MHz
ResTIM Timer resolution 16 bit

16-bit counter clock 1 65536 tTIMxCLK
tCOUNTER period when internal x = 2, 3, 4
clock is selected fTIMxCLK = 36 MHz 0.0278 1820 µs
65536 ×
tTIMxCLK
Maximum possible 65536
tMAX_COUNT x = 2, 3, 4
count
fTIMxCLK = 36 MHz 119.2 s
1. x gives the TIM concerned; where x = 2, TIM2 is concerned, etc.
48/64
5.3.15 Communications interfaces

I2C interface characteristics
performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions
The STM32F101xx access line I2C interface meets the requirements of the standard I2C
communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present. In addition, there is a protection
diode between the I/O pin and VDD. As a consequence, when multiple master devices are
connected to the I2C bus, it is not possible to power off the STM32F101xx while another I2C
master node remains powered on. Otherwise, the ST device would be powered by the
protection diode.
The I2C characteristics are described in Table 34. Refer also to Section 5.3.12: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 34. I2C characteristics

Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol Parameter Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 1.3

µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
th(SDA) SDA data hold time 0(3) 0(4) 900(3)
tr(SDA) ns
SDA and SCL rise time 1000 20+0.1Cb 300
tr(SCL)
tf(SDA)
SDA and SCL fall time 300 20+0.1Cb 300
tf(SCL)
th(STA) Start condition hold time 4.0 0.6
Repeated Start condition setup µs
tsu(STA) 4.7 0.6
time
tsu(STO) Stop condition setup time 4.0 0.6 µs
Stop to Start condition time (bus
tw(STO:STA) 4.7 1.3 µs
free)
Cb Capacitive load for each bus line 400 400 pF
2
1. Values based on standard I C protocol requirement, not tested in production.
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
49/64
Figure 17. I2C bus AC waveforms and measurement circuit
VDD VDD
4 .7 kΩ 4 .7 kΩ STM32F101
100 Ω
SDA
I²C bus 100 Ω
SCL
S TART REPEATED
S TART
tsu(STA) S TART
SDA
tf(SDA) tr(SDA) tsu(SDA)
S TOP tsu(STA:STO)
th(STA) tw(SCKL) th(SDA)
SCL
tw(SCKH) tr(SCK) tf(SCK) tsu(STO)
ai14127b
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 35. SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V)(1)(2)(3)
fSCL I2C_CCR value

(kHz) RP = 4.7 kΩ
400 TBD
300 TBD
200 TBD
100 TBD
50 TBD
20 TBD
1. TBD = to be determined.
2. RP = External pull-up resistance, fSCL = I2C speed,
3. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
50/64
SPI interface characteristics

performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 36. SPI characteristics(1)

fSCK Master mode TBD TBD

SPI clock frequency MHz
1/tc(SCK) Slave mode 0 TBD
tr(SCK)
SPI clock rise and fall time Capacitive load: C = 50 pF TBD
tf(SCK)
tsu(NSS)(2) NSS setup time Slave mode 0
th(NSS)(2) NSS hold time Slave mode 0
(2)
tw(SCKH) Master mode, fPCLK = TBD,
SCK high and low time TBD
tw(SCKL)(2) presc = TBD
tsu(MI) (2) Master mode TBD

Data input setup time
tsu(SI)(2) Slave mode TBD
Master mode TBD
th(MI) (2) Slave mode TBD

Data input hold time
th(SI)(2) Master mode, fPCLK = TBD TBD(3)
ns
Slave mode, fPCLK = TBD TBD(3)
Slave mode TBD TBD
ta(SO)(2)(4) Data output access time
Slave mode, fPCLK = TBD TBD TBD
(2)(5)
tdis(SO) Data output disable time Slave mode TBD TBD
Slave mode (after enable edge) TBD
tv(SO) (2)(1) Data output valid time
fPCLK = TBD TBD
Master mode (after enable edge) TBD
tv(MO)(2)(1) Data output valid time
fPCLK = TBD TBD TBD
(2)
th(SO) Slave mode (after enable edge) TBD
Data output hold time
(2)
th(MO) Master mode (after enable edge) TBD
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Depends on fPCLK. For example, if fPCLK= 8 MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
51/64
Figure 18. SPI timing diagram - slave mode and CPHA=0
NSS input
tSU(NSS) tc(SCK) th(NSS)
CPHA= 0
SCK Input
CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1
tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
th(SI)
ai14134
Figure 19. SPI timing diagram - slave mode and CPHA=11)
NSS input
tSU(NSS) tc(SCK) th(NSS)
CPHA=1
SCK Input
CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1
tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI) th(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
ai14135
52/64
Figure 20. SPI timing diagram - master mode
High
NSS input
tc(SCK)
CPHA= 0
SCK Input
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
SCK Input
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN
th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTUT
tv(MO) th(MO)
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53/64
5.3.16 12-bit ADC characteristics

performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 7.
Note: It is recommended to perform a calibration after each power-up.
Table 37. ADC characteristics(1)

VDDA ADC power supply 2.4 3.6 V
VREF+ Positive reference voltage 2.0 VDDA V
fADC ADC clock frequency 0.6 14 MHz
fS Sampling rate TBD 0.05 1 MHz

823 kHz
fTRIG External trigger frequency fADC = 14 MHz
17 1/fADC
VAIN Conversion voltage range 2) VSSA VDDA V
RAIN External input impedance kΩ
External capacitor on analog TBD(2)(3)
CAIN pF
input
VIN < VSS, | IIN |<
Negative input leakage current on
Ilkg 400 µA on adjacent 5 6 µA
analog pins
analog pin
RADC Sampling switch resistance 1 kΩ
Internal sample and hold
CADC 5 pF
capacitor
5.9 µs
tCAL Calibration time fADC = 14 MHz
83 1/fADC
0.214 µs
tlat Injection conversion latency fADC = 14 MHz
3 1/fADC
tS Sampling time fADC = 14 MHz 0.107 17.1 µs
tSTAB Power-up time 0 0 1 µs
1 18 µs
Total conversion time (including 14 (1.5 for sampling
tCONV fADC = 14 MHz
sampling time) +12.5 for successive 1/fADC
approximation)
2. Depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and reduced to
allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤14 MHz.
3. During the sample time the input capacitance CAIN (5 max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
54/64
Table 38. ADC accuracy (fPCLK2 = 10 MHz, fADC = 10 MHz, RAIN < 10 kΩ, VDDA =
3.3 V)(1)
Symbol Parameter Conditions Typ Max Unit
|ET| Total unadjusted error(2) 3 TBD

|EO| (2)
Offset error 1 TBD
(2)
|EG| Gain Error 2 TBD LSB
|ED| Differential linearity error(2) 3 TBD
(2)
|EL| Integral linearity error 2 TBD
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
Figure 21. ADC accuracy characteristics
EG
(1) Example of an actual transfer curve
1023
(2) The ideal transfer curve
1022 V –V (3) End point correlation line
DDA SSA
1LSB = -----------------------------------------
1021 IDEAL 1024
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
0
1 2 3 4 5 6 7 1021 1022 1023 1024
VSSA VDDA ai14395
Figure 22. Typical connection diagram using the ADC
VDD STM32F101
VT
0.6V
RAIN AINx RADC
12-bit A/D
conversion
VT
VAIN CAIN(1) 0.6V IL±1mA CADC
ai14139
1. Refer to Table 37 for the values of RADC and CADC.

2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion
accuracy. To remedy this, fADC should be reduced.
55/64
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 23 or Figure 24,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 23. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F101xx
V REF+
1 µF // 10 nF V DDA
1 µF // 10 nF
V SSA/V REF-
ai14380
1. VREF+ and VREF- inputs are available only on 100-pin packages.
Figure 24. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F101xx
VREF+/VDDA
1 µF // 10 nF
VREF–/VSSA
ai14380
1. VREF+ and VREF- inputs are available only on 100-pin packages.
56/64
5.3.17 Temperature sensor characteristics
Table 39. TS characteristics

TL VSENSE linearity with temperature ±1.5 °C
Avg_Slope Average slope 4.478 mV/°C

V25 Voltage at 25°C 1.4 V
tSTART Startup time 4 10 µs
57/64
Package characteristics STM32F101xx
6 Package characteristics
Figure 25. LQPF100 – 100-pin low-profile quad flat package outline
A
D
D1
A2
A1
E1 E
c
L1
L
h
ai14382
Table 40. LQPF100 – 100-pin low-profile quad flat package mechanical data
mm inches
Dim.
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.22 0.27 0.007 0.009 0.011
C 0.09 0.20 0.004 0.008
D 16.00 0.630
D1 14.00 0.551
E 16.00 0.630
E1 14.00 0.551
e 0.50 0.020
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
Number of pins
N 100
58/64
STM32F101xx Package characteristics
Figure 26. LQFP64 – 64-pin low-profile quad flat package outline
D A
D1 A2
A1
E1 E
e
c
L1
ai14383 L
Table 41. LQFP64 – 64-pin low-profile quad flat package mechanical data
mm inches
Dim.
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.22 0.27 0.007 0.009 0.011
c 0.09 0.20 0.004 0.008
D 12.00 0.472
D1 10.00 0.394
E 12.00 0.472
E1 10.00 0.394
e 0.50 0.020
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
Number of pins
N 64
59/64
Package characteristics STM32F101xx
Figure 27. LQFP48 – 48-pin low-profile quad flat package outline
D A
D1 A2
A1
E1 E e
c
L1
L
ai14384
Table 42. LQFP48 – 48-pin low-profile quad flat package mechanical data
mm inches(1)
Dim.
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.22 0.27 0.007 0.009 0.011
C 0.09 0.20 0.004 0.008
D 9.00 0.354
D1 7.00 0.276
E 9.00 0.354
E1 7.00 0.276
e 0.50 0.020
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
Number of pins
N 48
1. Values in inches are converted from mm and rounded to 3 decimal digits.
60/64
STM32F101xx Package characteristics
6.1 Thermal characteristics

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the
following equation:
TJ = TA + (PD x ΘJA) (1)
Where:
● TA is the ambient temperature in ° C,
● ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
● PD is the sum of PINT and PI/O (PD = PINT + PI/O),
● PINT is the product of IDD and VDD, expressed in Watts. This is the chip internal power.
PI/O represents the power dissipation on input and output pins;
Most of the time for the application PI/O < PINT and can be neglected. On the other hand, PI/O
may be significant if the device is configured to drive continuously external modules and/or
memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273 °C) (2)
Therefore (solving equations 1 and 2):
K = PD x (TA + 273 °C) + ΘJA x PD2 (3)
where:
K is a constant for the particular part, which may be determined from equation (3) by
measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ
may be obtained by solving equations (1) and (2) iteratively for any value of TA.
Table 43. Thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

46
LQFP 100 - 14 x 14 mm / 0.5 mm pitch
ΘJA 45 °C/W
LQFP 64 - 10 x 10 mm / 0.5 mm pitch
55
LQFP 48 - 7 x 7 mm / 0.5 mm pitch
61/64
Order codes STM32F101xx
7 Order codes
Table 44. Order codes

Flash program SRAM
Partnumber memory memory Package
Kbytes Kbytes
STM32F101C6T6 32 6
LQFP48
STM32F101C8T6 64 10
STM32F101R6T6 32 6
STM32F101R8T6 64 10 LQFP64
STM32F101RBT6 128 16
STM32F101V8T6 64 10
LQFP100
STM32F101VBT6 128 16
7.1 Future family enhancements

Further developments of the STM32F101xx access line will see an expansion of the current
options. Larger packages will soon be available with up to 512KB Flash, 48KB SRAM and
with extended features such as EMI support, DAC and additional timers and USARTS.
62/64
STM32F101xx Revision history
8 Revision history
Table 45. Document revision history

Date Revision Changes
06-Jun-2007 1 First draft.

IDD values modified in Table 11: Maximum current consumption in Run
and Sleep modes (TA = 85 °C).
VBAT range modified in Power supply schemes.
VREF+ min value, tSTAB, tlat and fTRIG added to Table 37: ADC
characteristics. Table 33: TIMx characteristics modified.
Note 5 modified and Note 7, Note 4 and Note 6 added below Table 3:
Pin definitions.
Figure 11: Low-speed external clock source AC timing diagram,
Figure 8: Power supply scheme, Figure 16: Recommended NRST pin
protection and Figure 17: I2C bus AC waveforms and measurement
circuit modified.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static
latch-up. 25 °C and 85 °C conditions removed and class name modified
20-Jul-07 2 in Table 28: Electrical sensitivities.
tSU(LSE) changed to tSU(LSE) in Table 17: HSE 4-16 MHz oscillator
characteristics.
In Table 24: Flash endurance and data retention, typical endurance
added, data retention for TA = 25 °C removed and data retention for TA =
85 °C added. Note removed below Table 7: General operating
conditions.
VBG changed to VREFINT in Table 10: Embedded internal reference
voltage. IDD max values added to Table 11: Maximum current
consumption in Run and Sleep modes (TA = 85 °C).
IDD(HSI) max value added to Table 19: HSI oscillator characteristics.
RPU and RPD min and max values added to Table 29: I/O static
characteristics. RPU min and max values added to Table 32: NRST pin
characteristics (two notes removed).
Datasheet title corrected. USB characteristics section removed.
Features on page 1 list optimized. Small text changes.
63/64
STM32F101xx
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STM32F101x6

July 2007 Rev 2 1/64

5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. STM32F101xx access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1 Device overview

Flash - Kbytes 32 64 32 64 128 64 128

12-bit synchronized ADC 1 1

CPU frequency 36 MHz

Operating voltage 2.0 to 3.6 V

Operating temperature -40 to +85 °C

Packages LQFP48 LQFP64 LQFP100

Embedded Flash memory

Nested vectored interrupt controller (NVIC)

External interrupt/event controller (EXTI)

Clocks and startup

Power supply schemes

Power supply supervisor

RTC (real-time clock) and backup registers

General purpose timers (TIMx)

Universal synchronous/asynchronous receiver transmitter (USART)

Serial peripheral interface (SPI)

GPIOs (general purpose inputs/outputs)

ADC (analog to digital converter)

Serial wire JTAG debug port (SWJ-DP)

Figure 1. STM32F101xx access line block diagram

MOSI,MISO, I2C1 SCL,SDA,SMBAL

1. AF = alternate function on I/O port pin.

Figure 2. STM32F101xx access line LQFP100 pinout

Figure 3. STM32F101xx access line LQFP64 pinout

Figure 4. STM32F101xx access line LQFP48 pinout

Table 3. Pin definitions

Pin name function(3) Default alternate functions(3)

- - 1 PE2/TRACECK I/O FT PE2 TRACECK

Table 3. Pin definitions (continued)

Pin name function(3) Default alternate functions(3)

Table 3. Pin definitions (continued)

Pin name function(3) Default alternate functions(3)

- - 56 PD9 I/O FT PD9

Table 3. Pin definitions (continued)

Pin name function(3) Default alternate functions(3)

- - 88 PD7 I/O FT PD7

Figure 5. Memory map

7 0x4002 1400 reserved 3K

0x4001 0800 Port A 1K

3 System memory 0x4001 0400 EXTI 1K

0x4001 0000 AFIO 1K

Code 0x0800 0000

0x4000 2800 RTC 1K

0x4000 0400 TIM3 1K

0x4000 0000 TIM2 1K

5.1 Test conditions

5.1.1 Minimum and maximum values

5.1.2 Typical values

5.1.3 Typical curves

5.1.4 Loading capacitor

5.1.5 Pin input voltage

Figure 6. Pin loading conditions Figure 7. Pin input voltage

STM32F101 PIN STM32F101 PIN

5.1.6 Power supply scheme

Figure 8. Power supply scheme

5.1.7 Current consumption measurement

Figure 9. Current consumption measurement scheme

5.2 Absolute maximum ratings