74LS00 NAND

74LS02 NOR
74LS04 NOT
74LS08 AND
74LS32 OR
74LS86 XOR
 2. Implementar las siguientes funciones de conmutación, debe de
especificar la tabla lógica, el circuito usando solo los circuitos integrados
mencionados en la pregunta N° 1 y un determinado diagrama de
temporización.

2.1 ̅̅̅̅
̅𝑸
𝒇 = (𝑷 ̅̅̅̅
̅ + 𝑹)(𝑷𝑹̅ + 𝑸)

Tabla Logica
P Q R PQ PQ + R PR PR + Q f
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0
0 1 0 0 0 0 1 0
0 1 1 0 1 0 1 1
1 0 0 0 0 0 0 0
1 0 1 0 1 1 1 1
1 1 0 1 0 0 1 1
1 1 1 1 1 1 1 1

Circuito (CKTO)

Diagrama de Temporizacion:
P 0 0 0 0 1 1 1 1
Q 0 0 1 1 0 0 1 1
R 0 1 0 1 0 1 0 1

1 1 1 1
f
0 0 0 0
2.2 F= ( PQ R)(Q  P  R)

P Q R P Q R PQ PQR QP (Q  P  R) F

0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 0 1 0 1 1 1
0 1 0 1 0 1 0 0 1 1 1
0 1 1 1 0 0 0 0 1 1 1
1 0 0 0 1 1 0 0 0 0 0
1 0 1 0 1 0 0 0 0 1 1
1 1 0 0 0 1 0 0 1 1 1
1 1 1 0 0 0 0 0 1 1 1

P Q R
0

U2:B
4
6
5

74LS32

U1:C f
U3:C 9
8
7 6 10

74LS08
4009
U2:C
9
8
U2:A 10
1
3 74LS32
2

74LS32

U1:B
4
6
5

74LS08

P 1 0 0 1 0 1 0 0 0 1 0 1 1

Q 1 0 1 0 0 1 1 0 0 1 1 1 0

R 0 0 1 1 1 1 0 1 1 0 1 0 0

f 0 0 0 0 1 0 0 1 1 0 0 0 1
F 1 0 1 1 1 1 1 1 1 1 1 1 0
2.3 𝑓 = ( 𝑅𝑄 + 𝑃 )( 𝑃𝑅 + 𝑄 )

𝑃 𝑄 𝑅 𝑄 𝑅𝑄 𝑃𝑅 (𝑅𝑄 + 𝑃) (𝑃𝑅 + 𝑄) 𝐹

0 0 0 1 1 1 1 1 1
0 0 1 1 0 1 0 1 0
0 1 0 0 1 1 1 1 1
0 1 1 0 1 1 1 1 1
1 0 0 1 1 1 1 1 1
1 0 1 1 0 0 1 0 0
1 1 0 0 1 1 1 1 1
1 1 1 0 1 0 1 1 1

Circuito:

Diagrama de temporización:

P 1 0 0 1 0 1 0 0 0 1 0 1 1

Q 1 0 1 0 0 1 1 0 0 1 1 1 0

R 0 0 1 1 1 1 0 1 1 0 1 0 0

Ff 01 01 01 0 10 01 01 10 10 01 01 01 11
 2.4 ̅+𝑹
𝒇 = (𝑸 + 𝑷 ̅̅̅̅
̅ )(𝑹𝑷̅ + 𝑸)

P Q R 𝑃̅ 𝑅̅ 𝑄 + 𝑃̅ + 𝑅̅ 𝑅𝑃̅ 𝑅𝑃̅ + 𝑄 f
0 0 0 1 1 1 1 1 1
0 0 1 1 0 1 0 0 0
0 1 0 1 1 1 1 1 1
0 1 1 1 0 1 0 1 0
1 0 0 0 1 1 1 1 1
1 0 1 0 0 0 1 1 1
1 1 0 0 1 1 1 1 1
1 1 1 0 0 1 1 1 1
Circuito:

U2:A
1 2

U1:A
SW1 74LS04
1
P 1 8 3
2 7 2
Q 3 6
4 5 74LS32 U1:B
R 4
SW-DIP4 U2:B 6
5
3 4
74LS32 U3:A
1
74LS04
3 f
2
U1:C
9 74LS08
8
U3:B U2:C 10
4
6 5 6 74LS32
5
74LS04
74LS08

Diagrama de Temporizacion:

P 0 1 0 1 1 1 1 0 0 0 1 1 0

Q 0 0 1 1 0 1 1 1 0 0 0 0 1

R 0 1 1 0 0 1 0 0 1 0 1 0 1

f 1 1 0 1 1 1 1 1 0 1 1 1 0
 ̅̅̅̅̅̅̅̅
2.5 𝒇 = (𝑷 ̅̅̅̅̅̅̅̅
+ 𝑸)𝑺 + 𝑷(𝑸 +𝑺 ̅)

P Q S 𝑃 +𝑄 𝑃 +𝑄 𝑄+ 𝑃 𝑄+ f
0 0 0 1 0 1 0 0 0
0 0 1 1 1 0 1 0 1
0 1 0 0 0 1 0 0 0
0 1 1 0 0 0 0 0 0
1 0 0 0 0 1 1 1 1
1 0 1 0 0 0 0 0 0
1 1 0 0 0 1 0 0 0
1 1 1 0 0 0 0 0 0
Circuito:
U1:A U3:A
1
3 1 2
2
U2:A
74LS04
74LS32 1
SW1 3
P 1 8 2
2 7
Q 3 6 U1:C
74LS08
4 5 9
S 8 f
SW-DIP4 10

74LS32
U2:B
4
U1:B U3:C 6
4 5
6 5 6
U3:B 5 74LS08
74LS04
3 4 74LS32

74LS04

Diagrama de Temporizacion:

P 1 0 0 1 0 1 0 0 0 1 0 1 1

Q 1 0 1 0 0 1 1 0 0 1 1 1 0

R 0 0 1 1 1 1 0 1 1 0 1 0 0

f 0 0 0 0 1 0 0 1 1 0 0 0 1
2.6 𝑓 = 𝑃 ( 𝑄 + )+𝑃𝑄

𝑃 𝑄 𝑄+ 𝑄+ 𝑃𝑄 𝑃𝑄 𝑃(𝑄 + ) 𝐹
0 0 0 1 0 0 0 0 0
0 0 1 0 1 0 0 1 1
0 1 0 1 0 0 0 0 0
0 1 1 1 0 0 0 0 0
1 0 0 1 0 1 0 0 0
1 0 1 0 1 1 1 0 1
1 1 0 1 0 0 0 0 0
1 1 1 1 0 0 0 0 0

Circuito:

Diagrama de temporización:

P 1 0 0 1 0 1 0 0 0 1 0 1 1

Q 1 0 1 0 0 1 1 0 0 1 1 1 0

SR 0 0 1 1 1 1 0 1 1 0 1 0 0

Ff 00 00 00 01 11 00 00 11 11 00 00 00 10
2.7 F= Q( P  S )  P( S  Q)

P Q S Q (P  S ) Q( P  S ) P ( S  Q) P (Q  S ) F
0 0 0 1 1 1 0 1 0 1
0 0 1 1 0 0 0 0 0 0
0 1 0 0 1 0 0 0 0 0
0 1 1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 1 1 1
1 0 1 1 0 0 1 0 0 0
1 1 0 0 0 0 1 0 0 0
1 1 1 0 0 0 1 0 0 0

U3:A
3 2
U1:A
1
4009 U1:B
3
P 0 U3:B 2 4
6
5 4 74LS08 5
Q 0
74LS08
4009 U1:C f
R 0 U3:C 9
8
7 6 10

74LS08
4009 U2:A
1
3 U2:B
2 4
6
74LS32 5

74LS32

P 1 0 0 1 0 1 0 0 0 1 0 1 1

Q 1 0 1 0 0 1 1 0 0 1 1 1 0

R 0 0 1 1 1 1 0 1 1 0 1 0 0

Ff 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1