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Writer : Majed Al-Jemmieh

Exercise 4
Draw the block diagrams for the systems depicted by the following register transfer statements
c) xT: R1<-R1 + R2
x'T: R1<-R2

What register transfer is it?


The following control inputs are active in the bus system shown in the figure below. For each case, specify the
register transfer that will be executed during the next clock transition.
S2 S1 S0 LD(x) Memory Adder The register transfer statement
1 1 1 IR READ - IR <- M[AR]
1 1 0 PC - - PC <- TR
1 0 0 DR WRITE - DR <- AC, M[AR] <- AC
0 0 0 AC - ADD AC <- AC + DR

What register transfer is it?


The following control inputs are active in the bus system shown in the figure below. For each case, specify the
register transfer that will be executed during the next clock transition.
S2 S1 S0 LD(x) Memory Adder The register transfer statement
1 1 1 IR READ - IR <- M[AR]
1 1 0 PC - - PC <- TR
1 0 0 DR WRITE - DR <- AC, M[AR] <- AC
0 0 0 AC - ADD AC <- AC + DR

Assembly to instruction, no parameters (BASIC COMPUTER)


Fill in the following table by writing in the binary and hex values for the given assembly commands
Assembly command Binary Hex
INC 0111 0000 0010 0000 7020
CMA 0111 0010 0000 0000 7200
HLT 0111 0000 0000 0001 7001
INP 1111 1000 0000 0000 F800
SKI 1111 0010 0000 0000 F200
CIL 0111 0000 0100 0000 7040
Assembly to instruction, with parameters (BASIC COMPUTER)
Fill in the following table by writing in the binary and hex values for the given assembly commands. Use the
symbol address table below:
SYMBOL Address
CNT 0x0400
PRG 0x00b5
VAR 0x016a
PA1 0x0271
PT2 0x02e8
SUB 0x00d9

Assembly command Binary Hex


LDA VAR 0010 0001 0110 1010 216A
ADD PA1 0001 0010 0111 0001 1271
BSA SUB 0101 0000 1101 1001 50D9
BUN CNT 0100 0100 0000 0000 4400
STA PT2 I 1011 0010 1110 1000 B2E8
BUN PRG I 1100 0000 1011 0101 C0B5
BUN 0 I 1100 0000 0000 0000 C0000
Instruction to assembly (BASIC COMPUTER)
Translate the following basic language instructions to assembly. What do each of them do separately? What do
they do when executed one after another? How could you improve the code? (means: do the same thing with
less instructions)
0111 1000 0000 0000 = CLA
0001 0101 1100 1111 = ADD 5CFh
0111 0010 0000 0000 = CMA
0111 0000 0010 0000 = INC
1011 0101 1101 0000 = STA 5D0h I
1010 0101 1101 0001 = LDA 5d1h I
1001 0101 1101 0000 = ADD 5D0h I
0111 0000 0000 0010 = SZE
0101 0111 0011 1100 = BSA 73Ch
1100 0000 0110 0100 = BUN 064h I
Improved version: LDA 5CFh
CMA
INC
ADD 5D1h I
SZE
BSA 73Ch
BUN 064h I
How is this done? Clearing the accumulator to zero and then adding some value to it is exactly the same as
moving the value directly over the contents of the accumulator. Secondly, storing a value to replace it by another
just to add the stored value again is pointless - we can simply add the other value directly to obtain an answer.

Exercise 5
PART 1 - Understanding instruction execution
Instruc on execu on 1
The content of AC in the basic computer is hexadecimal A937 and the ini al value of E is 1.Determine the contents
of AC, E, PC, AR and IR in hexadecimal after the execution of the CLA instruction. The initial value of PC is
hexadecimal 021.
Initial conditions:
AC = A937h
E=1
PC = 021h
Solution:
Execute CLA (Instruc on code 8 700h)
Fetch:
AR <- PC ; => (AR) = (PC) = 021h
IR <- M[AR] , PC <- PC + 1 ; => (IR)=7800h, (PC) = 022h
Decode:
D0,...,D7 <- decode IR(12-14)
AR <- IR(0-11), I <- IR(15) ; =>(AR) = 800h (12 address bits)
Execute:
AC <- 0 ; (AC) = 0
Summary:
(AC) = 0h, (AR) = 800h, (PC) = 022h, (IR) = 7800h, E= 1
Instruc on execu on 2
A basic computer is star ng to perform instruc on ADD 100 I. Given precondi ons are (values are hex decimals):
 PC = 190
 AC = 3
 M[100] = 200
 M[200] = fffe
a) Describe what happens during the instruction cycle. Include all phases from fetch to execute.
b) If an I/O device requests for an interrupt during the instruction cycle, what happens? Describe the events
starting from the fetch phase of the current instruction until the machine is ready to branch to the interrupt
subroutine of the I/O device.
Solution:
Before fetch, we branch to the instruc on cycle (R = 0).
Fetch:
R'T0: AR <- PC ; AR = PC = 190
R'T1: IR <- M[AR] , PC <- PC + 1 ; IR = 9100, PC = 191

Decode:
R'T2: D0,...,D7 <- decode IR(12-14) ; D1 = 1
AR <- IR(0-11), I <- IR(15) ; I = 1, AR = 100
Determine whether instruc on is memory reference, register or I/O. Because D1 was set to 1, all other decoder
outputs Dn are set to 0 (see figure 5-6). Therefore the instruc on is a memory-reference instruction.
Indirect:
D7'IT3: AR <- M[AR] ; AR = 200

Execute:
D1T4: DR <- M[AR] ; DR = fffe
D1T5: AC <- AC + DR, ; AC = 1
E <- C(out), SC <- 0 ;E=1
Remember that SC (Sequence Counter) is incremented on every clock pulse Tn.
Instruc on execu on 3
The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The content of AC is 7EC3. The
content of memory at address 3AF is 932E. The content of memory at address 32E is 09AC. The content of memory
at address 9AC is 8B9F.
a) What is the instruction that will be fetched and executed next?
b) Show the binary operation that will be performed in the AC when the instruction is executed
c) Give the contents of registers PC, AR, DR, AC and IR in hexadecimal and the values of E, I and the sequence
counter SC in binary at the end of the instruction cycle.
Solution:
a) (PC) = 3AF => next instruc on that will be fetched is 932E that is indirect ADD instruc on (from table 5
-2). The
address of the operand is at address 32E (instruc on bits 0- 11).
b) Address of the operand is 09AC at address 32E => operand is at address 09AC => operand is 8B9F
ADD command:
DR <- M[AR]
AC <- AC + DR ; operand is in DR
E <- Cout , SC <- 0 ; E = 1 if carry out

=> (AC) = (AC) + 8B9F = 7EC3 + 8B9F


=>

7EC3 = 0111 1110 1100 0011


+ 8B9F = 1000 1011 1001 1111
---------------------------------
1 0000 1010 0110 0010 = 0A62 (carry discarded)
c)
(PC) = 3B0 ; 3AF + 1
(AR) = 9AC ; Address of the last memory reference
(DR) = 8B9F ; 2'nd operand
(AC) = 0A62 ; The result of addi on
(IR) = 932E ; Last instruc on fetched = ADD
E = 1 ; we had carry out
(SC) = 0 ; Cleared at the end of ADD command
I = 1 ; indirect ADD
PART 2: Let's code assembly!
Warming up...
a)How do you jump unconditionally to label STR?
Solution: BUN STR
b)How do you jump to label SUB and save the return address?
Solution: BSA SUB
c)After that, how do you return from that subroutine? (i.e. how do you use the return address?)
Solution: BUN SUB I
Coding assignment - loops
Write simple loops in basic computer assembly.
a) A loop that iterates until the value of memory location denoted by symbol CND is zero
Solution:
LOP, LDA CND

SZA

BUN LOP

b) A loop that iterates 20 mes. This loop doesn't need to do anything else- just loop and waste time
Solution:
TJU, -21 DEC

LOP, ISZ TJU

BUN LOP
c) A loop inside a loop. The outside loop should iterate 17 mes, and the internal loop 9 mes during each
iteration of the outside loop. The loop doesn't need to do anything more than that.
Solution:
LC1, -18 DEC

LCV, -9 DEC

LC2, 0

LOP, LDA LCV

STA LC2

LO2, ISZ LC2

BUN LO2

ISZ LC1

BUN LOP