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2013 IEEE XXXIII International Scientific Conference Electronics and Nanotechnology (ELNANO)

FPGA Based Capacitive Touch Pad/Interface

Radovan Stojanović, Nedjeljko Lekić, Zoran Mijanović, Jovan Kovačević


Faculty of Electrical Engineering
University of Montenegro
Podgorica, Montenegro
stox@ac.me

Abstract — This paper reports a sensing principle and FPGA II. SENSING PRINCIPLE AND SYSTEM DESIGN
design of a capacitive touch pad/interface where the sensing pad
is connected to the I/O pin via an external resistor. The circuit A. Sensing Principle
transforms the change in pad capacitance into voltage amplitude In single-touch configuration the sensing pad is connected
during charging, discharging and sharing phases. By using
to the bidirectional FPGA pin Pn via resistance R, Fig. 1. The
multiple pins and resistors, a multipad system is achieved. The
sensing algorithm is implemented in VHDL code. The read-out direction of pin, input or outpud, is determined by DIR
cycle is parallel and short, what results in a high noise immunity register, while the input state is read by IN register. Cp is a pin
in low frequency range. The silicon/hardware requirements are capacitance and for FPGAs has value of about 4pF. Cb is
minimal. The interface can be easily embedded into a system-on- body-ground capacitance, typically in the range 100pF-150
chip and used for human-machine, bio-chemical and mechanical pF, but can be as high as 400pF. Cx0 and Cx1 are the
sensor interfacing.
capacitances of untouched and touched pad, respectively.
Keywords— FPGA; capacitive pad; sensor; touch interface Usually, Cb>>Cx1, expressing the equivalent capacitance pad-
finger-ground system as Cx≈Cx0+Cx1. Cxo has the value of
I. INTRODUCTION 6.5pF for D=10m, while Cx1 decreases from 7pF-1.5pF for
The capacitive sensors have long history of use in industrial 0.1mm<dx1<1mm.
measurements, but only during the last two decades they
started to make inroads into human-computer interaction. The
expansion of multifunctional and multimedia digital devices
and gadgets, such as smart phones, iPads and different mobile
and desktop instruments have opened huge opportunities for
commercialization and further development of these types of
interaction.
In the open literature and available to us applications
different capacitive sensing techniques can be identified:
oscillator-based, resistor-based, approaches based on switched
capacitors and programmable current sources etc. [1, 2]. The
read-out circuits are usually implemented in microcontroller [3,
4] or ASSP (Application Specific Standard Products) chips [5].
Essentially, none of the elaborated approaches and systems
can fully and satisfactorily answer main requirements of
today's and future capacitive sensing interfaces: i) serving
almost infinite number of sensor pads; ii) reading pads
quickly; iii) achieving high noise immunity; iv) embedding
interface in same chip with the rest of digital system and v)
Fig. 1. FPGA based capacitive pad/interface
reaching a competitive cost.
FPGA (Field Programmable Gate Arrays) technology with The sensing process starts with “CHARGE” phase, Fig. 2,
full parallelism, huge capacity of digital circuits, high operating by setting logical “1” (3.3V) to the pin Pn for time tc=0.75us-
speed, on-chip signal processing possibilities and affordable 2us, long enough to charge Cp and Cx to the values
price, shows a potential to solve some of the above issues. V1=V2=3.3V. Dashed line indicates situation for increased
This paper presents an FPGA based methodology for value of Cx, pad touched. During the “DISCHARGE” phase,
capacitive sensing which includes minimal number of external Cp discharges totally, because of V1=0V, while V2 declines by
components and appears to be suitable for human-machine, time constant RCx reaching the end value V2(td) after the
bio-chemical and mechanical multi sensor interface. discharging time td. td may be chosen between 200ns-750ns.

978-1-4673-4672-6/13/$31.00 ©2013 IEEE 399


2013 IEEE XXXIII International Scientific Conference Electronics and Nanotechnology (ELNANO)
The remaining charge on Cx, after time td, is:

During the “SHARE” phase, with duration of ts, pin Pn is


switched to the high impedance mode (Z mode) and QCx(td )
shares proportionally to Cp and Cx. At the end of the sharing
V1≈V2, i≈0 and voltage onto pin Pn has analytical value:

“MEASURE” phase begins with delay tm, when IN register is


read. As seen, for known Cp, td and R, the V1 is a function of
Cx and further of dx1 – which is a finger distance. V1 can
reach the level bellow or above the pin’s threshold VTR Fig. 3. Selection of external resistor R
depending on whether the pad is touched or not. Translated
B. FPGA Design Methodology
into digital domain it means logical ”1” or “0” of the
corresponding bit within the register IN. The Single-Pad Capacitive Interface (SPCI) presents a basic
Finding an optimal value for R is an additional issue. Fig 3 design core of the sensing interface, Fig. 4. It is a three
shows graphical illustration of (2) for td=200us, VDD=3.3V, terminal port with clock (CLK), sensor input (S) and sensor
Cp=4pF and R as parameter. As seen, for R=68K, VTR status (SS) signals. In essence, it is a counter with comparator.
corresponds to VTR≈(V1(touched)-V1(untouched))/2, and that is The generic constants CHARGE_TIME_NS,
an optimal case. Additional purpose of R is to protect the DISCHARGE_TIME_NS, START_READ_NS, correspond to
FPGA pin from the electrostatic discharges and with 68K it the tc, td and ts+tm respectively, while PERIOD_NS marks a
can go up to1000V. reading cycle. These constants are parameterized, but can
alternatively be stored in configuration registers. The VHDL
code of SPCI unit, Listing 1, presents the software
implementation of sensing protocol.

Fig. 4. SPCI) and MPCI FPGA architectures

In the case of Multi-Pad Capacitive Interface MPCI, SPCIs


are “copied” n times in parallel. The Si (i=1..n) signals are
sensor inputs. SSi (i=1..n) present internal outputs that are fed
to the PRIORITY ENCODER and DECODER producing
KEY CODE and KEY PRESSED outputs. KEY CODE is the
length of log2n, while KEY PRESSED is a binary signal
Fig. 2. The sensing algorithm which is active when one of pads is pressed and can be used
for producing interrupt. Both are carried out or forwarded to

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2013 IEEE XXXIII International Scientific Conference Electronics and Nanotechnology (ELNANO)
the CUSTOM DIGITAL SYSTEM unit. In our case CLK has The second criterion was checking of occupancy of silicon
frequency of 48 MHz. resources, Table I. SPCI occupies only 60 LEs, (Logical
Elements) which is mere 1% of total number of available LEs
for chip EP1C6Q240C8, which has 5980 LEs in total. MPCI
in 2, 4, 8, 16, 32 and 64 input configurations occupy 140, 151,
168, 213, 297 and 462 LEs. It can be noted that the design is
very silicon-effective and, as an example, 64 pads
configuration occupies only 7.7 % of the EP1C6Q240C8
resources and 72 pins out of 240. Practically, N inputs MPCI
may even be embedded in a low-capacity FPGA. The only
limitation is a number of available FPGA pins, usually several
hundreds.

Fig. 5. Oscilloscope probes introduce the additional capacitances Cop.

Listing 1. VHDL implementation of sensing algorithm

III. EXPERIMENTAL RESULTS


Fig. 6. Real waveforms for untouched (up) and touched (down) pad,
On-chip verification of the proposed approach was D=10mm and dx1=0.1mm, paper insulator.
performed on EP1C6Q240C8 FPGA chip from Altera Cyclone
Series [6]. After the code design, compilation and debugging, The third test criterion was noise immunity. Because of the
the chip is configured in SPCI configuration. The pad of parallelism, the sampling period does not increase with the
10mm diameter is isolated with 0.1mm paper layer. In real number of pads, and can be adjusted from 5us to 20us in a real
measurements, Fig. 5, the oscilloscope probes were connected situation. Additional benefit in terms of noise is that the input
to the ends of resistor R, introducing the additional impedance of pin Pn has a low value during phases
capacitances Cop of 15pF in parallel to Cx and Cp, Agilent “CHARGE” and “DISCHARGE” and high value (Z), which is
Tech. DSO3102A and Agilent Tech. probes N2862A. It noise sensitive, only during “SHARE” and “MEASURE”.
significantly reduces the sensing effects having in mind the This makes the sensor being very robust regarding to the low-
capacitance Cx1, about 7pF, see Fig.1. Thus, in order to frequency noise such is AC noise of 50Hz or 60Hz, because it
emphasize visual effects, the charging, discharanging and can affect very shortly, only during “SHARE” and
sharing times are increased to tc=24us, td=2.5us and t- “MEASURE” phases, whose total duration is about 1μs. For
s+tm=15us, respectively, Fig. 6. As can be seen, the traces example, AC noise with induced amplitude of 100V has an
match very well the theoretical prediction, Fig. 2, and the increment of ΔVACmax= 22mV, during 1μs on steepest interval.
presence of finger is detected. In real situation the distinction It is much less than the margin │V1(touched)-VTR│≈
effect is even more pronounced. │V1(untouched)-VTR│, see Fig. 3, for R=68K the margin is

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2013 IEEE XXXIII International Scientific Conference Electronics and Nanotechnology (ELNANO)
above 0.35V. Thus, mains voltage can be considered as DC testing results against set criteria are elaborated. The system is
signal which does not influence the sensing mechanism. The very versatile and can be used in low cost embedded human-
influence of radiated noise (high frequency) can be reduced by machine, bio-chemical and mechanical sensor interfacing.
implementing software filters in VHDL, while environmental ACKNOWLEDGMENT
noise has a slow increment over time.
This paper presents a part of the research performed in the
TABLE I. HARDWARE OCCUPATION IN LES projects: “Development and implementation of embedded
systems for medical applications”, MESI. The authors are
# of % of grateful for their support.
# of LEs # of occupied pins
pads available LEs
1 60 1 5 REFERENCES
2 140 2.4 5
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16 213 3.5 22 October 2002.
[3] Z. Albus, “PCB-Based Capacitive Touch Sensing With MSP430”, Texas
32 297 5.0 39 Instruments, Dallas, Application Report SLAA363A, 2007.
[4] N. Lekic, R. Stojanovic, Z. Mijanovic , ‘‘An approach of using
64 462 7.7 72 microcontroller port as capacitive keypad’’, Proceedings of the IEEE 20th
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2011, September 2011, Portoroz, Slovenija, pp. 43---46.
IV. CONCLUSIONS [5] Fujitsu Microelectronics America, “Interfacing the FMA1127 Touch
Sensor Controller with Fujitsu Microcontrollers”, Application Note,
A capacitive sensing technique is presented. It is fully 2009.
digital and as such very suitable for implementation in system- [6] Altera Corporation, Cyclone Device Handbook, Volume 1, 2008,
on-chip like FPGA. The sensing principle and design http://www.altera.com/literature/hb/cyc/cyc_c5v1.pdf .
architectures are presented together with the core code. The

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