so13/2018 ‘System Veniog: Packed and Unpacked Array : Memory Allocation ) Mowe Crate Blog $1 System Verilog Mer ob, 208 Packed and Unpacked Array : Memory Allocation ‘ystemVerog stores each element in ng word (32 bts). For example, folowing decaration wil use 32s Inthe memory, though only 8 bits ae realy used Ber} ‘is a sngleeloment wih 8 bits-The memory use wile as below, Rowing the above declaration ike flowing Bi 7:0) 2_unpackod (2 05 "Now's become an aay which contains 3 elemenis wih the size of 8 bis each. As ‘SystemVerlog stores ‘2ch element in a longword (82 bis’. n the above dectaration wi ook tke is ‘The memory is nat use efciently (not well packe), but sometimes it i nec called unpacked array. Les rewrite the above declaration into fllowing way B20) [7-0}2_packed ‘The word dimension [20] moved next obit cimension [7]. ais an element (noe iis single olomont) which has 3 sos of bt words. Since a single element stored ina long word, memory usage wil look ike this ‘The memory used oferty (wo packs). is callod packed aray Ped yn 2 No comments: Post a Comment Po Netty me am enon ntpifsystemveriog123.blogspot.comy2016/02ipacked-and-unpacked-array-memonghim! 1.sovs2018 ‘System Verilog: Packed and Unpacked Array ¥ bey 10) Sane Unsne vari: Aaa. Dose Sat rise apo Maha Ove + mse Singename Poway oso _ntplleystemverlog 128 blogspot conv2016/02Ipacked-and-unpacked-array-memory.hm! Memary Allocation 2