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Digital Simulation White Paper Comparison of VHDL, Verilog and SystemVerilog
Stephen Bailey Technical Marketing Engineer Model Technology www.model.com
Introduction A s the numb er of enhancements to various
Hardware Description Languages (HDLs) has
increased over the past year, so too has the com-
plex ity of determining which language is b est for
a particular design. Many designers and organi-
zations are contemplating whether they should
switch from one HDL to another.
This paper compares the technical characteristics of three, general-purpose
HDLs: ¥ VHDL (IE E E -Std 10 7 6 ): A general-pur- pose digital design language
supported b y multiple verification and synthesis (implementation) tools. ¥ V
erilog (IE E E -Std 136 4): A general-pur- pose digital design language
supported b y multiple verification and synthesis tools. ¥ SystemVerilog: A n
enhanced version of
Verilog. A s SystemVerilog is currently
b eing defined b y A ccellera, there is not
yet an IE E E standard. General Characteristics of the Languages E ach HDL has
its own style and heredity. The
following descriptions provide an overall ÒfeelÓ
for each language. A tab le at the end of the
paper provides a more detailed, feature-b y-fea-
ture comparison.
VHDL VHDL is a strongly and richly typed language.
Derived from the A da programming language, its
language requirements mak e it more verb ose
than Verilog. The additional verb osity is intend-
ed to mak e designs self-documenting. A lso, the
strong typing requires additional coding to
ex plicitly convert from one data type to another (integer to b it-vector, for
ex ample). The creators of VHDL emphasized semantics
that were unamb iguous and designs that were
easily portab le from one tool to the nex t. Hence,
race conditions, as an artifact of the language
and tool implementation, are not a concern for
VHDL users.
Several related standards have b een developed to
increase the utility of the language. A ny VHDL
design today depends on at least IE E E -Std 116 4
(std_ logic type), and many also depend on stan-
dard Numeric and Math pack ages as well. The
development of related standards is due to
another goal of VHDLÕ
s authors: namely, to pro-
duce a general language and allow development
of reusab le pack ages to cover functionality not
b uilt into the language.
VHDL does not define any simulation control
or monitoring capab ilities within the language.
These capab ilities are tool dependent. Due to
this lack of language-defined simulation control
commands and also b ecause of VHDLÕ
s user-
defined type capab ilities, the VHDL community
usually relies on interactive GU I environments
for deb ugging design prob lems.
Verilog Verilog is a weak ly and limited typed language.
Its heritage can b e traced to the C programming
language and an older HDL called Hilo.
A ll data types in Verilog are predefined in the
language. Verilog recognizes that all data types
have a b it-level representation. The supported
data representations (ex cluding strings) can b e
mix ed freely in Verilog.
Comparison of VHDL, Verilog, and SystemVerilog 1 Pros and Cons of Strong Typing
The b enefit of strong typing is finding b ugs in a
design as early in the verification process as pos-
sib le. Many prob lems that strong typing uncover
are identified during analysis/compilation of the
source code. A nd with run-time check s enab led,
more prob lems may b e found during simulation.
The downside of strong typing is performance
cost. Compilation tends to b e slower as tools
must perform check s on the source code.
Simulation, when run-time check s are enab led,
is also slower due to the check ing overhead.
Furthermore, designer productivity can b e lower
initially as the designer must write type conver-
sion functions and insert type casts or ex plicitly
declared conversion functions when writing code.
The $ 1,0 0 0 ,0 0 0 question is this: do the b enefits of strong typing
outweigh the costs? There isnÕ t one right answer to the question. In
general, the VHDL language designers wanted a
safe language that would catch as many errors as
possib le early in the process. The Verilog language
designers wanted a language that designers could -
use to write models quick ly. The designers of
SystemVerilog are attempting to provide the b est
of b oth worlds b y offering strong typing in areas
of enhancement while not significantly impacting
code writing and modeling productivity.
2 Comparison of VHDL, Verilog, and SystemVerilog Language Feature Comparison
The following tab le presents a feature-b y-feature comparison of the three
HDLs. Note that the purple font color differentiates Verilog 20 0 1 features
from Verilog 19 9 5 features. Comparison of VHDL, Verilog, and SystemVerilog 3
VHDL Verilog(20 0 1) SystemVerilog Strong typing Yes No • Bit
• bit-vector
• wire
• reg)
• unsigned
•signed • integer • real • String in certain contexts only Partial Not strongly
typed in areas back- ward compatible with Verilog Yes Enhanced type system is
strongly typed (but not as strong as VHDL) User-defined types Yes No Yes Dynamic
memory allocation (pointer types) Yes No Partial Class objects can be
dynamically
created/destroyed, but via handles
(“safe pointers”)
Physical types Yes No No Named events No Yes Yes Enumerated types (FSM modeling)
Yes No Yes Records/structs Yes No Yes Variant/unions No No Yes
Associative/sparse arrays Partial (But can be modeled using access types) No Yes
Class/inheritance No No Yes (single inheritance) Data packing No No Yes Bit
(vector) / integer equivalence Partial Not built-in but standard package
supports Yes Yes User defined signal/net resolution Yes No No Subprograms
(procedural) Yes Function & procedure always automatic Yes Static andautomatic
functions and tasks Yes Same as Verilog plus void functions (procedures)
Subprograms (concurrent) aka tasks Yes Concurrent procedure calls Yes Static
tasks Yes Static tasks Methods No No Yes (goes hand-in-hand with classes)
Separate packaging Yes Packages Yes Include files Yes Include files continues on
pg 4 4 Comparison of VHDL, Verilog, and SystemVerilog continues on pg 5
continued from pg 3 VHDL Verilog(20 0 1) SystemVerilog Other hierarchy Yes
Separate entity / architecture (Interface / implementation) No Yes Programs,
Clocking domains, Interfaces All-read sensitivity No Yes @ (*) Yes Same as
Verilog. Plus: always_comb Reactive region processes Yes Postponed processes No
Yes Programs, Clocking domains, Final blocks Dynamic process creation/deletion
No Yes Fork/join. Block/task disable. Yes Same as Verilog. Conditional
statements Yes • If-then-else/elsif (priority) • Case (mux) • Selected assign
(mux) • Conditional assign (priority) • No “don’t care” matching capability Yes
• if-else (priority)
• case (mux)
• casex (mux)
• ?: (conditional used in concurrent assignments) Yes Same as Verilog.
Adds priority and unique keywords
to infer priority encoding/mux
implementation Iteration Yes • Loop
• while-loop
• for-loop
• exit • next Can name the loop to exit or continue with next Yes • repeat • for
• while Yes Same as Verilog, Plus: • do-while
• break
• continue
Only closest enclosing loop can be break or continue Operators & expressions Yes
All expected: • arithmetic
• logical
• bit-wise
• shift
• concatenation
Overloadable (polymorphism).
No unary reduction.
No logical scalar/vector.
Yes All expected: • arithmetic
• logical
• bit-wise
• shift
• concatenation
• unary reduction
• logical scalar/vector
• case (in)equality.
• conditional (?:)
No rotate left/right Yes Same as Verilog. Plus: • wild (in)equality
• increment
• decrement
• assignment (+=, -=, |=, etc.) No rotate left/right Gate level modeling Yes
VITAL. Very good FPGA library support. Yes Builtin primitives. UDPs. Better
availability of ASIC library support Yes Same as Verilog.
Except, library support yet to be
qualified as vendors won’t assume
Verilog sign-off = SystemVerilog
sign-off Interface abstraction Partial Component abstracts interface
from specific module.
Two layer binding allows flexibility
in generic/port mapping.
No Yes Interfaces are a separate
construct in language.
Supports multiple abstraction
level and eases interface reuse.
Can reduce coding.
Comparison of VHDL Verilog and SystemVerilog
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