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CoolSET™-F2
ICE2A165/265/365
ICE2A180/280
P o w e r M a n a g em e n t & S u p p l y
N e v e r s t o p t h i n k i n g .
CoolSET™-F2
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www.infineon.com
Edition 2001-09-19
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München
© Infineon Technologies AG 1999.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted char-
acteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infin-
eon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
CoolSET™-F2
ICE2A165/265/365
ICE2A180/280
Features Description
• 650V/800V Avalanche Rugged CoolMOS™ The second generation COOLSET™-F2 provides several
• Only few external Components required special enhancements to satisfy the needs for low power
• Input Undervoltage Lockout standby and protection features. In standby mode
• 100kHz Switching Frequency frequency reduction is used to lower the power
• Max Duty Cycle 72% consumption and support a stable output voltage in this
• Low Power Standby Mode to meet European mode. The frequency reduction is limited to 21.5 kHz to
Commission Requirements avoid audible noise. In case of failure modes like open loop,
• Thermal Shut Down with Auto Restart overvoltage or overload due to short circuit the device
• Overload and Open Loop Protection switches in Auto Restart Mode which is controlled by the
• Overvoltage Protection during Auto Restart internal protection unit. By means of the internal precise
• Adjustable Peak Current Limitation via peak current limitation the dimension of the transformer and
External Resistor the secondary diode can be lower which leads to more cost
• Overall Tolerance of Current Limiting < ±5% efficiency.
• Internal Leading Edge Blanking
• User defined Soft Start
• Soft Switching for Low EMI
Typical Application
+
Snubber Converter
RStart-up DC Output
85 ... 270 VAC
-
CVCC
VCC Drain
Feedback
Low Power Power
StandBy Management CoolMOS™
RSense
FB
Protection Unit
GND
PWM-Controller
CoolSET™-F2
Feedback
Type Ordering Code Package UDS FOSC RDSon1) 230VAC ±15%2) 85-265 VAC2)
ICE2A165 Q67040-S4426 P-DIP-8-6 650V 100kHz 3.0Ω 31W 18W
ICE2A265 Q67040-S4414 P-DIP-8-6 650V 100kHz 0.9Ω 52W 32W
ICE2A365 Q67040-S4415 P-DIP-8-6 650V 100kHz 0.45Ω 67W 45W
ICE2A180 ES Samples available P-DIP-8-6 800V 100kHz 3.0Ω 31W 18W
ICE2A280 Q67040-S4416 P-DIP-8-6 800V 100kHz 0.8Ω 54W 34W
1)
typ @ T=25°C
2)
Maximum power rating at Ta=75°C, Tj=125°C and with copper area on PCB = 6cm²,
SoftS 1 8 GND
VCC (Power supply)
This pin is the positiv supply of the IC. The operating
range is between 8.5V and 21V.
FB 2 7 VCC
To provide overvoltage protection the driver gets
disabled when the voltage becomes higher than 16.5V
during Start Up Phase.
Isense 3 6 N.C
GND (Ground)
4 5 This pin is the ground of the primary side of the SMPS.
Drain Drain
Figure 2
Datasheet
+
Converter
Snubber DC Output
RStart-up CLine
85 ... 270 VAC VOUT
-
CVCC
VCC Drain
Power Management
Undervoltage Internal
Lockout Bias
13.5V
C1
8.5V
16.5V
Power-Down 6.5V 0.72
Reset 5.3V Oscillator
Representative Blockdiagram
Voltage Duty Cycle
6.5V 4.8V
4.0V Reference max
C2 Power-Up 4.0V
G1
Reset Clock
RSoft-Start 21.5-100kHz
6
R Q
4.8V PWM
C3 Comparator
RFB Error-Latch
0.3V
C5
FB Current-Limit RSense
fosc Leading Edge 10kΩ
Thermal Comparator
Blanking
Shutdown 100kHz Vcsth
200ns
Representative Blockdiagram
CoolSET™-F2
GND
September 2001
Representative Blockdiagram
ICE2A165/265/365
ICE2A180/280
CoolSET™-F2
CoolSET™-F2
ICE2A165/265/365
ICE2A180/280
Functional Description
3 Functional Description
3.1 Power Management 3.2 Improved Current Mode
M ain L in e (1 00 V -3 80 V )
S o ft-S ta rt C o m p a ra to r
R S tart-U p
P o w er-D ow n 6.5 V PW M OP
R e set 5.3 V
V o lta g e
R efe ren ce
4.8 V
x3 .6 5 Ise n se
4.0 V
P o w er-U p
R e se t Im proved
C urrent M ode
R Q
P W M -L atch
6 .5 V
Figure 4 Current Mode
S Q
R Soft-Sta rt Current Mode means that the duty cycle is controlled
S o ftS E rro r-L a tch
by the slope of the primary current. This is done by
S o ft-S ta rt C om p ara tor
comparison the FB signal with the amplified current
sense signal.
C S oft-Start T1 E rror-D ete ctio n
A m p lified C u rren t S ig n al
0.8V
1 0 kΩ
x3 .6 5
R1 t
T2
V1
PW M OP Figure 7 Light Load Conditions
C1 2 0p F
3.2.1 PWM-OP
V oltage Ram p The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
Figure 6 Improved Current Mode RSense connected to pin ISense. RSense converts the
source current into a sense voltage. The sense voltage
To improve the Current Mode during light load is amplified with a gain of 3.65 by PWM OP. The output
conditions the amplified current ramp of the PWM-OP of the PWM-OP is connected to the voltage source V1.
is superimposed on a voltage ramp, which is built by The voltage ramp with the superimposed amplified
the switch T2, the voltage source V1 and the 1st order current singal is fed into the positive inputs of the PWM-
low pass filter composed of R1 and C1(see Figure 6, Comparator, C5 and the Soft-Start-Comparator.
Figure 7). Every time the oscillator shuts down for max.
duty cycle limitation the switch T2 is closed by VOSC.
When the oscillator triggers the Gate Driver T2 is 3.2.2 PWM-Comparator
opened so that the voltage ramp can start. The PWM-Comparator compares the sensed current
In case of light load the amplified current ramp is to signal of the integrated CoolMOSTM with the feedback
small to ensure a stable regulation. In that case the signal VFB (see Figure 8). VFB is created by an external
Voltage Ramp is a well defined signal for the optocoupler or external transistor in combination with
comparison with the FB-signal. The duty cycle is then the internal pullup resistor RFB and provides the load
controlled by the slope of the Voltage Ramp. information of the feedback circuitry. When the
By means of the C5 Comparator the Gate Driver is amplified current signal of the integrated CoolMOS™
switched-off until the voltage ramp exceeds 0.3V. It exceeds the signal VFB the PWM-Comparator switches
allows the duty cycle to be reduced continously till 0% off the Gate Driver.
by decreasing VFB below that threshold.
6 .5 V C4
5 .3 V G2 S Q
T Soft − Start
C Soft − Start =
G a te D rive r t R Soft − Start × 1, 69
V S o ftS kHz
100
5 .3 V
65
f OSC
T S oft-S ta rt
21,5
0,9
V FB t 1,0 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2
V
V FB
4 .8 V Figure 12 Frequency Dependence
I O v e rs ho ot1 V
1,3
1,25
1,2
VSense
1,15
t 1,1
1
The overshoot of Signal2 is bigger than of Signal1 due 0,95
to the steeper rising waveform. 0,9
A propagation delay compensation is integrated to 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 V
bound the overshoot dependent on dI/dt of the rising dVSense µs
primary current. That means the propagation delay dt
time between exceeding the current sense threshold
Vcsth and the switch off of CoolMOS™ is compensated Figure 16 Overcurrent Shutdown
over temperature within a range of at least.
dI dV Sense 3.6 PWM-Latch
0 ≤ R Sense × peak
≤ 1
dt dt The oscillator clock output applies a set pulse to the
PWM-Latch when initiating CoolMOS™ conduction.
So current limiting is now capable in a very accurate After setting the PWM-Latch can be reset by the PWM-
way (see Figure 16). OP, the Soft-Start-Comparator, the Current-Limit-
Comparator, Comparator C3 or the Error-Latch of the
VOSC Protection Unit. In case of reseting the driver is shut
max. Duty Cycle down immediately.
3.7 Driver
off time The driver-stage drives the gate of the CoolMOS™
and is optimized to minimize EMI and to provide high
circuit efficiency. This is done by reducing the switch on
VSense Propagation Delay t slope when reaching the CoolMOS™ threshold. This is
achieved by a slope control of the rising edge at the
Vcsth driver’s output (see Figure 17).
Thus the leading switch on spike is minimized. When
CoolMOS™ is switched off, the falling shape of the
driver is slowed down when reaching 2V to prevent an
overshoot below ground. Furthermore the driver circuit
is designed to eliminate cross conduction of the output
Signal1 Signal2 stage. At voltages below the undervoltage lockout
t threshold VVCCoff the gate drive is active low.
Figure 15 Dynamic Voltage Threshold Vcsth
4 .8 V
F a ilu re
D e te ctio n
5V
t
S o ftS
t
5 .3 V
Figure 17 Gate Rising Slope S o ft-S ta rt P h a se
R FB
6 .5 V
Figure 19 FB-Detection
t
S o ftS S o ft-S ta rt P ha se C S o ft-S ta rt
5 .3V T1 P o w e r U p R e se t
4 .0V
O v erv olta g e
D e te ction P ha se
8.5 V
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 6
(VCC) is discharged before assembling the application circuit.
4.3 Characteristics
Note: The electrical characteristics involve the spread of values guaranteed within the specified supply voltage
and junction temperature range TJ from – 25 °C to 125 °C.Typical values represent the median values,
which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 15 V is assumed.
36
13,54
34
13,52
32
PI-004-190101
PI-001-190101
13,50
30
13,48
28
13,46
26
24 13,44
22 13,42
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]
Figure 22 Start Up Current IVCC1 vs. Tj Figure 25 VCC Turn-On Threshold VVCCon vs. Tj
6,0 8,67
VCC Turn-Off Threshold V VCCoff [V]
8,64
Supply Current IVCC2 [mA]
5,7
8,61
8,58
5,4
8,55
PI-003-190101
PI-005-190101
8,52
5,1
8,49
8,46
4,8
8,43
4,5 8,40
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]
Figure 23 Static Supply Current IVCC2 vs. Tj Figure 26 VCC Turn-Off Threshold VVCCoff vs. Tj
9,0 5,10
VCC Turn-On/Off Hysteresis V CCHY [V]
8,6 5,07
Supply Current I VCC3 [mA]
ICE2A365
8,2 5,04
7,8 5,01
ICE2A280
7,4 4,98
PI-002-190101
PI-006-190101
7,0 4,95
6,6 4,92
ICE2A265
5,8 4,86
5,4 4,83
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Figure 24 Supply Current IVCC3 vs. Tj Figure 27 VCC Turn-On/Off HysteresisVVCCHY vs. Tj
6,55 4,70
Trimmed Reference Voltage V REF [V]
6,54 4,68
6,52 4,64
6,51 4,62
PI-010-190101
PI-007-190101
6,50 4,60
6,49 4,58
6,48 4,56
6,47 4,54
6,46 4,52
6,45 4,50
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]
Figure 28 Trimmed Reference VREF vs. Tj Figure 31 Frequency Ratio fOSC1 / fOSC2 vs. Tj
102,0 0,730
101,5 0,728
Oscillator Frequency f OSC1 [kHz]
101,0 0,726
100,5 0,724
Max. Duty Cycle
100,0 0,722
PI-008-190101
PI-011-190101
99,5 0,720
99,0 0,718
98,5 0,716
98,0 0,714
97,5 0,712
97,0 0,710
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Figure 29 Oscillator Frequency fOSC1 vs. Tj Figure 32 Max. Duty Cycle vs. Tj
21,8 3,70
Reduced Osc. Frequency f OSC2 [kHz]
21,7 3,69
21,6 3,68
21,5 3,67
PWM-OP Gain AV
21,4 3,66
PI-009-190101
PI-012-190101
21,3 3,65
21,2 3,64
21,1 3,63
21,0 3,62
20,9 3,61
20,8 3,60
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]
Figure 30 Reduced Osc. Frequency fOSC2 vs. Tj Figure 33 PWM-OP Gain AV vs. Tj
4,00 5,35
Feedback Resistance R FB [kOhm]
3,95 5,34
3,85 5,32
3,80 5,31
PI-013-190101
PI-016-190101
3,75 5,30
3,70 5,29
3,65 5,28
3,60 5,27
3,55 5,26
3,50 5,25
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]
Figure 34 Feedback Resistance RFB vs. Tj Figure 37 Detection Limit VSoft-Start1 vs. Tj
58 4,05
Soft-Start Resistance R Soft-Start [kOhm]
56 4,04
Detection Limit V Soft-Start2 [V]
4,03
54
4,02
52
4,01
50
PI-014-190101
PI-017-190101
4,00
48
3,99
46
3,98
44
3,97
42 3,96
40 3,95
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]
Figure 35 Soft-Start Resistance RSoft-Start vs. Tj Figure 38 Detection Limit VSoft-Start2 vs. Tj
4,85 16,80
Overvoltage Detection Limit V VCC1 [V]
4,84 16,75
16,70
4,83
Detection Limit V FB2 [V]
16,65
4,82
16,60
4,81 16,55
PI-015-190101
PI-018-190101
4,80 16,50
4,79 16,45
16,40
4,78
16,35
4,77
16,30
4,76 16,25
4,75 16,20
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Figure 36 Detection Limit VFB2 vs. Tj Figure 39 Overvoltage Detection Limit VVCC1 vs. Tj
1,010 2,0
1,008 1,8
Peak Current Limitation V csth [V]
1,002 1,2
ICE2A280
PI-023-190101
PI-019-190101
1,000 1,0
0,998 0,8
0,996 0,6
0,994 0,4
0,992 0,2
0,990 0,0
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C] Junction Temperature [°C]
Figure 40 Peak Current Limitation Vcsth vs. Tj Figure 43 Drain Source On-Resistance RDSon vs. Tj
280 1,0
270 0,9
Leading Edge Blanking t LEB [ns]
260 0,8
250 0,7
PI-024-190101
230 0,5
220 0,4
210 0,3
200 0,2
190 0,1
180 0,0
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Figure 41 Leading Edge Blanking VVCC1 vs. Tj Figure 44 Drain Source On-Resistance RDSon vs. Tj
900
7,6
Breakdown Voltage V (BR)DSS [V]
850 ICE2A180
7,0 ICE2A280
On-Resistance R dson [Ohm]
6,4 800
5,8
750
5,2
PI-022-190101
PI-025-190101
4,6 700
ICE2A165
4,0 ICE2A180
650
3,4
1,0 500
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Figure 42 Drain Source On-Resistance RDSon vs. Tj Figure 45 Breakdown Voltage VBR(DSS) vs. Tj
6 Outline Dimension
P-DIP-8-6
(Plastic Dual In-line
Package)
Figure 46
Dimensions in mm
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