Engineering Science and Technology, an International Journal 21 (2018) 43–49

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Engineering Science and Technology,

an International Journal
journal homepage: www.elsevier.com/locate/jestch

Full Length Article

A new voltage mode quadrature oscillator using grounded capacitors: An

application of CDBA
Tajinder Singh Arora ⇑, Soumya Gupta
Maharaja Surajmal Institute of Technology, Janakpuri, New-Delhi, India

a r t i c l e i n f o a b s t r a c t

Article history: The paper realizes a single-resistance-controlled oscillator employing current differencing buffered
Received 29 October 2017 amplifiers as active devices, and virtually grounded resistors and grounded capacitors as passive compo-
Revised 10 January 2018 nents. Operating in voltage mode, the designed circuit is capable of generating quadrature outputs along
Accepted 13 January 2018
with an unambiguous control of oscillating frequency and condition of oscillation. Initially, practicality
Available online 13 February 2018
and feasibility of the design has been justified by the results obtained using PSPICE simulation software.
Simulation results include time response and frequency response outputs generated by using the com-
Keywords:
mercially available I.C. of CFOA, i.e. AD844, as well as by using the CMOS structure of active device
Single-resistance-controlled oscillator
Quadrature outputs
employed. Later, hardware experimentation of the design has been included, for which AD844 along with
Current differencing buffered amplifiers standard components have been employed. Validating results have been obtained in both the cases.
Voltage mode oscillators Ó 2018 Karabuk University. Publishing services by Elsevier B.V. This is an open access article under the CC
BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction as: (a) employment of minimum active and passive components,

Analog signal processing encounters a wide use of filters and
oscillators [1,2,3]. Use of various different active devices such as
Current Feedback Operational Amplifier (CFOA) [4,5], Current Con-
veyors (CC) [6,7], Differential Voltage Current Conveyor (DVCC)
[8,9], Voltage Differencing Current Conveyor (VDCC) [10,11], Oper-
ational Transconductance Amplifiers (OTA) [12,13] etc. in generat-
ing these filter or oscillator networks has been frequently
witnessed in literature. In 1999, a new active building block was
proposed by Acar and Ozoguz [14], which was named as Current
Differencing Buffered Amplifier (CDBA). This versatile device has
a wide frequency range and is suitable for both current and voltage
mode operations. These features encouraged a widespread use of
CDBA in realization of circuits like filters, oscillators, and convert-
ers, to name a few [15,16] and also references cited therein.
Single-resistance-controlled oscillator (SRCO) refers to a block
that generates a continuous periodic, oscillating electronic signal,
whose frequency of oscillation (F.O.) and condition of oscillation
(C.O.) are controllable by a separate individual resistive element.
Finding application in telecommunication and instrumentation,
quadrature sinusoidal oscillators are the ones which produce out-
puts with 90° phase shift. For evaluating the efficiency of SRCO
configurations several factors are taken into consideration such
⇑ Corresponding author.
E-mail address: tajarora@msit.in (T.S. Arora).
Peer review under responsibility of Karabuk University.
(b) efficient tunability of F.O. and C.O., (c) working frequency of
designed oscillator, (d) easier cascadibility, and (e) efficient inte-
grated circuit implementation and so on.
Exploring the versatility of device CDBA further, the authors
have devised a network acting as an oscillator and offering the fol-
lowing features: (a) two active components, (b) low passive com-
ponent count (c) easy tunablility of F.O. and C.O., (d) grounded
capacitors and hence easier IC implementation, (e) high oscillating
frequency and (f) generation of quadrature outputs. Entirely based
on above mentioned features, an elaborated comparison has been
provided in Table 1. As per the table, one of the work done on CDBA
[23] is similar to the presented work. However, other worthy fac-
tors which became the basis of comparison are frequency of oscil-
lation, number of IC employment and simulation results. The
frequency of oscillation achieved in designed SRCO is 500 kHz
whereas that achieved in previous work [23] is 15.91 kHz. Also,
the simulation results shown there were using AD844 only but
simulations shown in this work is using CMOS and AD844. In sim-
ulating the SRCO proposed [23], four AD844 were used but here
only three have been used. Hence, proposed configuration of this
manuscript has several other advantages when compared to SRCO
designed previously.
According to the literature survey conducted, there are many
circuits available in literature which provide some of the men-
tioned features, but no circuit has the capability of supporting all
the features and simulations presented in this work. Hence, there

https://doi.org/10.1016/j.jestch.2018.01.006
2215-0986/Ó 2018 Karabuk University. Publishing services by Elsevier B.V.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
44 T.S. Arora, S. Gupta / Engineering Science and Technology, an International Journal 21 (2018) 43–49

Table 1
Comparison between previous work and presented work.

Reference No. Number of CDBA Number of passive components All grounded Capacitors Independent C.O. and F.O.
[17] 2 5 No Yes
[18] 2 6 Yes Yes
[19] 2 6 Yes Yes
[20] 2 6 No Yes
[21] 1 5 No Yes
[22] 2 8 No No
[23] 2 5 Yes Yes
Circuits 1–4 [24] 2 6 Yes Yes
Circuits 5–12 [24] 2 6 No Yes
[25] 2 5 No Yes
[26] 2 5 No Yes
Proposed Circuit 2 5 Yes Yes

is a successful bridging of gap between the previous circuits and

designed circuit, through this manuscript.
Divided among various sections, the present section gives the
introduction of analog signal processing, quadrature oscillators
and comparison between previous work and presented work.
While the next section, i.e. Section 2, will introduce the active
building block of this manuscript (CDBA). Section 3 contains the
designed circuit with its ideal analysis. Non-ideal and sensitivity
analysis are stated in Section 4. Occupying Section 5 is the analysis
of the configuration with parasitic effects under consideration.
Tabulation of THD results is done in Section 6. Verifying the theo- Fig. 2. Ideal structure of CDBA obtained by voltage sources and current sources.
retical analysis, Section 7 contains all the simulation results
obtained through PSPICE. Experimental results, with circuit design
and related theoretical discussion, is presented in Section 8. At last,
conclusion is provided in Section 9. The nomenclature used in
complete manuscript is defined in Appendix (A-1), provided at
the end.

2. Current differencing buffered amplifier

CDBA is a two-input two-output terminal device, shown in

Fig. 1. Amongst the available ports, P and N are low impedance Fig. 3. CDBA implementation using AD844.
input ports whereas Z terminal is high impedance output port
and W is low impedance output port.
On ignoring the non-idealities of the device employed, the ideal
characteristic equations of CDBA are derived, as given in (1). These
are basically obtained by analyzing the ideal structure of the device
shown in Fig. 2.
Ideal analysis of circuits generated using CDBA as active device
is done using these equations given below.

VP ¼ VN ¼ 0
VW ¼ VZ ð1Þ
I Z ¼ I P  IN
As defined in literature, CDBA can be generated by employing
the commercially available I.C. of CFOA, i.e. AD844 [1], or by using
MOSFETs with a suitable technology [27]. Both these realizations of Fig. 4. CMOS arrangement of employed CDBA [27].
CDBA are shown in Figs. 3 and 4 respectively.

Practically CDBA is characterized by equations given in (2)

which are also used during non-ideal analysis of circuits generated
using CDBA as active building block.

VP ¼ VN ¼ 0
V W ¼ dV Z ð2Þ
IZ ¼ aIP  bIN

wherea, b and d are port transfer ratios of P, N and Z terminals

Fig. 1. Symbol of CDBA. respectively.
 T.S. Arora, S. Gupta / Engineering Science and Technology, an International Journal 21 (2018) 43–49 45

3. Proposed circuit 1
Sx 0 x0 x0 x0
R1 ¼ SR2 ¼ SC 1 ¼ SC 2 ¼  ð9Þ
2
The circuit for SRCO has been designed keeping in mind easier
and efficient integrated circuit implementation and hence the cir- 1
S- 0 -0 -0 -0
R1 ¼ SR2 ¼ SC 1 ¼ SC 2 ¼  ð10Þ
cuit contains only two capacitors, both grounded in nature, and 2
three resistors among which two are virtually grounded. Using
1
only two CDBA, by keeping F.O. and C.O. independent of each other, S- -0 -0
d1 ¼ Sd2 ¼ Sb2 ¼
0
ð11Þ
the configuration has been designed, which is given in Fig. 5. 2
Analyzing the circuit shown in Fig. 5 using characteristic equa-
tions given in (1), the ideal characteristic equation for oscillator is
5. Parasitic effect
obtained as stated in (3). For initiating and sustaining the oscilla-
tions of constant amplitude in any oscillator network, a condition
Fig. 6 depicts the symbol of a non-ideal CDBA when the para-
has to be fulfilled which is termed as condition of oscillation. The
sitic impedances of all the terminals are involved. Including these
frequency at which these oscillations are obtained is termed as fre-
parasitic impedances and considering non-idealities of all ports to
quency of oscillation.
be unity, the circuit shown in Fig. 5 is redrawn and provided in
Frequency and condition of oscillation are derived as shown in
Fig. 7. The characteristic equation, of the voltage mode oscillator
(4) and (5) respectively.
circuit, is given in (12).


s 1 1 1 


s2   þ ¼0 ð3Þ 1 1 1 1 1 1
C 1 R3 R2 R1 R2 C 1 C 2 s2 þ s þ  þ
C A RB RZ1 RA C B RZ2
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

1 1 1 1 1
1 þ þ  þ
FO : x0 ¼ ð4Þ C A C B RZ1 RZ2 RB RZ2 RA RZ2 RC RB
R1 R2 C 1 C 2
¼0 ð12Þ
CO : R3 6 R2 ð5Þ The expression for F.O., under parasitic impedances considera-
The above derived equations indicate that F.O. can be controlled tion, is given in (13) while C.O. was obtained as given in (14).
from virtually grounded resistor R1 whereas C.O. can be varied by sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

ffi
 1 1 1 1 1
another virtually grounded resistor i.e. R3 . Hence, the designed cir- FO : x ¼ 0 þ  þ ð13Þ
cuit is capable of acting as a single-resistance-controlled oscillator. C A C B RZ1 RZ2 RB RZ2 RA RZ2 RC RB



4. Non-Ideal and sensitivity consideration 1 1 1 1 1 1
CO þ  þ 60 ð14Þ
C A RB RZ1 RA C B RZ2
Analysis of the design of Fig. 5, upon consideration of non- Wherein assumptions have been made that C A ¼ C 1 þ C Z1 ,
idealities of CDBA, resulted in oscillator’s characteristic equation C B ¼ C 2 þ C Z2 , RA ¼ R3 þ RP1 , RB ¼ R2 þ RO2 and RC ¼ R1 þ RN2 .
to be as shown in (6). Similarly, the effect has been shown on oscil- From above derived equations it is evident that presence of par-
lating frequency and condition of oscillation through (7) and (8) asitic elements affects the condition and frequency of oscillations.
respectively However, error due to these can be avoided if the value of external


a1 d1 1 d1 d2 b2 passive components are kept higher than these, when present in
s2  s  þ ¼0 ð6Þ series, and lower than these when present in parallel. In accor-
R3 C 1 R2 C 1 R1 R2 C 1 C 2
dance with Fig. 7, the value of C 1  C Z1 and similarly the value
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi of C 2  C Z2 . Also, the value of parasitic resistances at P, N and W
d1 d2 b2 terminals, i.e., RP1 , RN2 and RW2 should be very less when compared
FO : -0 ¼ ð7Þ
R1 R2 C 1 C 2 to R3 , R1 and R2 respectively. Hence, all these parasitic resistances
and capacitances will get absorbed and there will be no influence
CO : R3 6 d1 a1 R2 ð8Þ of the same on frequency and condition of oscillation.
where a1 , b1 , and d1 represent the non-ideal port transfer ratios of
CDBA1 while a2 , b2 , and d2 represent the non-idealities of CDBA2. 6. Total Harmonic Distortion (THD) analysis
The sensitivity of the network towards different passive compo-
nent values, in ideal and non-ideal case, as well as towards the Presence of harmonics at frequencies other than the oscillating
non-ideal transfer ratios are included in (9)-(11) respectively. Evi- frequency has been evaluated through THD analysis, which is per-
dently, very low sensitivity value, i.e. 0.5, has been obtained which formed in Cadence PSPICE software. Summarizing the THD results,
indicates the efficient performance of the designed configuration. when CMOS structure of CDBA is employed, Table 2 has been
prepared.

Fig. 5. Proposed SRCO circuit. Fig. 6. Non-ideal CDBA with parasitics at each terminal [16].
46 T.S. Arora, S. Gupta / Engineering Science and Technology, an International Journal 21 (2018) 43–49

Table 4
Aspect ratios of transistors shown in Figure. 4.

Transistors W (mm)/L (mm)

M1 –M 10 150/1
M11 , M 12 4/2
M13 , M 14 , M17 , M 18 5/1
M15 , M 16 100/1
M19 20/1
M20 200/1

Fig. 7. Proposed SRCO circuit with parasitic elements involved.

The THD results obtained when AD844 were employed for sim-
ulations, as per Fig. 2, are tabulated in Table 3.
It is evident from the above tables that the value of THD in both
the cases, i.e. CMOS and AD844, is 3.7% and 0.72% respectively.
These low values support the efficient functionality of the designed
SRCO.

7. Simulation results
Fig. 8. Transient response using CMOS structure of CDBA as active device.
Using the Cadence PSPICE simulation software, all the regular
simulation graphs have been obtained for the purpose of justifying
the practical workability of the design. Like mentioned before,
commercially available I.C. of CFOA, i.e. AD844, as well as CMOS
arrangement of CDBA, both have been employed for verifying the
practicality of the devised oscillator network, through simulations.
Fig. 4 shows the CMOS structure of CDBA wherein current with
an amplitude of 30mA has been used for IB1 , IB2 and IB3 and a supply
voltage (V DD and V SS ) of amplitude ±2.5 V has been applied. The
aspect ratios of all the utilized MOSFETs are provided in Table 4
[27], and 0.5 mm MIETEC technology real transistor process param-
eters have been used [28].
Analysis performed using the CMOS structure of CDBA, as active
device, resulted in F.O. being 500 kHz with the component values
being adjusted to R1 ¼ R2 = 25 KO, R3 = 22 KO and C 1 ¼ C 2 = 12.7 Fig. 9. Steady state response attained using CMOS structure of CDBA.
pF. The percentage error for this frequency reported to be 4.02.
Supporting the theoretical data provided for the novel SRCO circuit, outputs generated by the design are shown in Fig. 10. The FFT
the transient response as well as the steady state response of it has response of the output voltage, which indicates the presence of
been included in Figs. 8 and 9 respectively. The two quadrature oscillations at desired frequency, is given in Fig. 11. At last, the

Table 2
THD results for CMOS structure of CDBA.

Harmonic No. Frequency Fourier Component Normalized Component Phase (°) Normalized Phase
1 5.000E+05 6.931E01 1.000E+00 9.441E+01 0.000E+00
2 1.000E+06 2.427E02 3.502E02 9.507E+01 9.375E+01
3 1.500E+06 7.626E03 1.100E02 1.515E+02 1.317E+02
4 2.000E+06 4.469E03 6.448E03 1.166E+02 2.610E+02
5 2.500E+06 2.692E03 3.885E03 1.085E+02 3.636E+02
DC component = 3.228251E02
Total harmonic distortion = 3.747226E + 00 percent

Table 3
THD results for AD844 implementation of CDBA.

Harmonic No. Frequency Fourier Component Normalized Component Phase (°) Normalized Phase
1 1.446E+05 8.371E+00 1.000E+00 1.536E+02 0.000E+00
2 2.892E+05 1.776E02 2.122E03 2.039E+01 2.868E+02
3 4.338E+05 3.426E02 4.093E03 1.759E+02 2.850E+02
4 5.784E+05 1.914E02 2.286E03 3.806E+01 5.764E+02
5 7.230E+05 4.298E02 5.134E03 5.901E+01 8.271E+02
DC component = 9.599857E03
Total harmonic distortion = 7.269179E01 percent
 T.S. Arora, S. Gupta / Engineering Science and Technology, an International Journal 21 (2018) 43–49 47

Fig. 10. Quadrature waveforms of designed oscillator using CMOS structure of

CDBA.
Fig. 13. Transient response obtained through simulation using AD844.

Fig. 11. FFT response of steady state output using CMOS arrangement of CDBA. Fig. 14. Steady state response obtained through simulation using AD844.

variations in frequency of oscillation with respect to resistor R1 is

provided in Fig. 12, which also depict the deviations between ideal
and simulated frequencies.
Commercially available AD844s, with ±12 V supply, have been
employed for generating simulation as well as hardware experi-
mentation results. The central frequency in this case was 144.62
kHz, which was obtained by adjusting the component values to
R1 ¼ R2 = 10 KO, R3 = 9.7 KO, C 1 = 103 pF and C 2 = 104 pF. The per-
centage error, between the simulated and the experimental fre-
quency, reported to be 0.25. The transient analysis obtained
through simulation is given in Fig. 13, from which the steady state
response has been taken and displayed in Fig. 14. The two output
voltages i.e. VB and VA, marked in Fig. 5, results in quadrature
waveforms which has been depicted in Fig. 15. The Fast Fourier
Transform (FFT) response is provided in Fig. 16. Fig. 15. Quadrature waveforms obtained through simulation using AD844.

8. Experimental results

Practical implementation of single CDBA requires the use of two

AD844 ICs, as shown in Fig. 3. The designed SRCO, despite of

Fig. 16. FFT response obtained through simulation using AD844.

employing two CDBA, requires the use of only three AD844 ICs,
in total, as P terminal of CDBA2 is open. A schematic diagram of
Fig. 12. Variations in frequency of oscillation with respect to R1 . the realization of proposed configuration using discrete compo-
48 T.S. Arora, S. Gupta / Engineering Science and Technology, an International Journal 21 (2018) 43–49
Fig. 17a. Schematic diagram of hardware realization.
Fig. 17b. Experimental arrangement for designed SRCO.
Fig. 18. Steady state response obtained through experimentation using AD844.
nents is shown in Fig. 17a and the actual hardware arrangement is
shown in Fig. 17b. The figure depicts the utilization of AD844 in
designing a network with CDBA as active device.
For generating the hardware results, the circuit is operated with
dual power supply (Agilent E3631A) at ±12 V level. The passive
component values used in experimentation are same as that used
during simulations through AD844. The similarity has been kept
so that comparison between both the results, i.e. simulation and
hardware, can be appreciated. For observing the oscillations, and
obtaining phase and gain information, Agilent Technologies Digital
Oscilloscope MSO6014A has been used.
Fig. 19. Quadrature waveform obtained through experimentation using AD844.
Fig. 20. Variations in frequency of oscillation with respect to R1 .
The following graphs are the results of hardware experimenta-
tion, carried out at a frequency of 145 kHz. The steady state anal-
ysis of the oscillator has been shown in Fig. 18. As claimed earlier,
the configuration is capable of producing quadrature waveforms
which has been justified in Fig. 19. Also, the figure shows the phase
and frequency obtained, which clearly states that the two wave-
forms are out of phase by 91°.
In order to focus on comparative study between simulation,
theoretical and experimental values, a curve between varying val-
ues of virtually grounded resistor R1 and frequency of oscillation
has been drawn and presented in Fig. 20. This graph shows the
deviation between frequency values obtained in all three cases
for a fixed value of resistor R1 .
9. Conclusion
The paper introduced a single-resistance-controlled oscillator,
capable of generating quadrature outputs and supported by the
features of easy tunability, voltage mode and high frequency oper-
ation. Minimum active and passive components were employed,
with all the capacitors being grounded, resulting in easier I.C.
implementation. Out of three resistors used, two were virtually
grounded. All necessary theoretical results and corresponding
practical results were presented. Testing of the devised oscillator,
through simulations, was done using two different implementa-
tions, a commercially available I.C. (AD844) as well as CMOS struc-
ture of CDBA. Validation of design was also confirmed through
hardware experimentation, wherein three AD844s were employed
in performing the experiment.
 T.S. Arora, S. Gupta / Engineering Science and Technology, an International Journal 21 (2018) 43–49 49

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