1.1.

BACKGROUND

The explosive growth of mobile phone in our pocket, television at

home,desktopcomputer to the space shuttle, cloud computing etc. have changed

the life styleof the people. It envisions a world of ubiquitous electronic devices and

sensors of newexciting applications termed as “Internet of Things (IoT)”. The

development of theelectronics industry is rapid above the substratum

semiconductor device since mid-20thcentury. To meet the growing demands of this

industry, there evolved the expansionand diversification in the field of research. The

fabrication of various functionalities on asingle semiconductor surface known as

integrated circuits (ICs) or “chips” is so to say thebeginning of the electronics era.

Everywhere chips perform their operations satisfactorily.Each of these chips are

quite diverse, designed to different specifications to performvarious operations

under several operating conditions. The fundamental technology used in chips is the

CMOS (complementary metal-oxide semiconductor) technology. Ever since the first

semiconductor transistor by Bardeen, Brattain and Shockley in 1947 and the first IC

by Kilby in 1958 were invented, the semiconductor industry went through an

evaluation at a disproportionate speed for more than five decades. Presently, the

semiconductor technology set the stage for many modern civilizations.

Semiconductor technology lays the basis for rapid growth of global electronic

industry. At present, the electronic industry is the world’s largest industry. It is

anticipated that the semiconductor and electronics industry will continue to grow

and increase its share in the Gross World Product (GWP).The semiconductor
industry might be able to reach about 1.6 trillion dollars, while the complete

electronic industry may reach about 10 trillion dollars and constitute about 10% of

the GWP by 2030. All the IC chips internally consist of large number of small

electron device. The number of electron devices per chip has increased

exponentially over past few decades due to decrease in size of the devices, and has

now entered the ULSI (Ultra Large Scale Integration) era because of which a billon

transistors can now be integrated into a single IC chip. One of the key electron

devices in the IC is the MOSFET. Currently, MOSFET is the most accepted device for

VLSI (Very Large Scale Integration) and ULSI applications. Due to the advancement

in MOSFET technology, the cutting edge VLSI and ULSI design provides a number of

benefits like, ultrafast computational abilities, multiple functionalities, less standby

and operating power and a lot more. From supercomputers such as the IBM Blue

Gene to consumer products like the iPod and the world’s second largest industry in

automobiles, MEMS gyro circuitry, human civilization has been highly benefitted

because of the advancement in the IC and MOSFET technology.

1.2. Motivation for Present Research:

The explosive growth of communication technology has created mass consumer

market for Radio-Frequency (RF) electronics. Mobile communications as an example

is one of the fastest growing areas over the past decade and semiconductor devices

for RF applications are the backbone of advanced communication systems. In

addition to digital circuits, emerging nanoscale MOSFETs remain a strong contender

for analog and RF applications in the wireless communications market. In addition

1
to the digital circuits, CMOS technology has gained extensive importance in analog

and RF circuits due to its low cost, high integration capability and low noise

performance. Today the challenges CMOS technology is facing in terms of severe

Short-channel effects (SCEs) arising from the extremely scaled dimensions has

resulted in the need to explore new device architectures and design. Recent studies

reveals that there are several novel device structures such as Tunnel FET,

heterostructure MOSFETs, nanowires(nw) Tunnel FET, FinFETs, junctionless

transistors, CNTs, etc. are emerging as strong contender to replace conventional

planar bulk transistors. In the deep sub micron regime, these novel device structures

exhibit promises to replace the conventional bulk MOSFETs due to their higher

immunity against the SCEs, low leakage current, CMOS compatible technology, high

Ion/Ioff ratio, sub 60mV/dec and improved subthreshold slope with the requirement of

lower power supply.(synopsis).

1.3. Plan of work:

A deep understanding of the theoretical and computational aspects of emerging

nanoscale devices is a prime requirement for the development and growth of

nanotechnology. In recent years, rapid development in the area of electronics and

micro computing is fueled by the significant innovations and applications of

nanotechnology. Recently it has been noticed that rapid progress in nanoscale

engineering and science leads to the relentless development of emerging devices

with sophisticated materials. Therefore, in order to achieve a more quantitative and

2
qualitative understanding of the nanoscale science, improved modeling and

simulation study of emerging nanoscale devices and materials has become highly

important.

Today, innovations in RF devices, circuits and architectures makes wireless

communication to become an un-detachable part of everyday's life due to the

continued scaling potential of CMOS technology augmented with recent

development in fabrication process. Therefore, the explosive growth of

communication technology has created mass consumer market for Radio-Frequency

(RF) electronics. Mobile communications as an example is one of the fastest

growing areas over the past decade and semiconductor devices for RF applications

are the backbone of advanced communication systems. In addition to digital

circuits, emerging nanoscale MOSFETs remain a strong contender for analog and RF

applications in the wireless communications market. In addition to the digital

circuits, CMOS technology has gained extensive importance in analog and RF circuits

due to its low cost, high integration capability and low noise performance.

Today the challenges CMOS technology is facing in terms of severe Short-

channel effects (SCEs) arising from the extremely scaled dimensions has resulted in

the need to explore new device architectures and design. Recent studies reveals

that there are several novel device structures such as Tunnel FET, heterostructure

MOSFETs, nanowires, FinFETs, junctionless transistors, CNTs, etc. are emerging as

strong contender to replace conventional planar bulk transistors. In the deep sub

micron regime, these novel device structures exhibit promises to replace the

3
conventional bulk MOSFETs due to their higher immunity against the SCEs, low

leakage current, CMOS compatible technology, high Ion/Ioff ratio, sub 60mV/dec and

improved subthreshold slope with the requirement of lower power supply.

Therefore, the analytical modeling of nano-dimensional MOSFET is a prime

requirement to investigate its down-scaling ability and to judge their Short-channel

effects performance parameter figure-of-merits. Till now, researchers has been

focused mainly on the digital applications of the emerging nanoscale devices.

However, the analog and linearity performance is still an unexplored area, has not

been received enough attention and needs to be investigated also. The modern day

communication requires low distortion and linear systems as a building block for

their design and implementation. Because, increased traffic in the neighboring

frequency ranges forces more constraints on the linearity matrices of RF systems,

and intensify the need for more effective linearization techniques.

Linearity is considered as one of the most important requirements in all

RF communication systems. Good linearity ensures minimum contributions of

higher order harmonics and inter-modulation terms and results in less distortion

at the output of RF front-end stages. Traditional ways to achieve linearity

involve complex circuit design methods, and/or requires operation of the device in

the velocity saturation regime which implies high supply voltages and large power

consumption–a scenario that is not ideal for portable and low power applications.

In nanoscale MOSFETs, transconductance, and output conductance are

considered as major sources of nonlinearity. The focus of this work is to provide the

4
impact of various device physics and device scaling on the RF performance analysis

and investigation of various linearity matrices due to their dominant role for

today’s RF systems and circuits using analytical model and simulation. Therefore,

in this work, we are dealing with theory, modeling, design and simulations of

nanostructured materials and devices with nano dimensions to find their suitability

in linear RF circuits/systems. In this study, our focus is to study the linearity and

analog performance of nanoscale deviecs with sub-100nm channel length to

determine their suitability for analog/ RF applications. Therefore, this work is

concerned about different linearity, distortion and analog performance metrics like

2nd order/third order variable intercept point, 2nd order/ 3rd order Inter

modulation distortion, 1-dB compression, 2nd order/3rd order intercept points,

transconductance generation, drain-to-source output resistance Rout, cut-off

frequency, maximum frequency of oscillation, gain bandwidth product in a

comparative manner .(synopsis) 1.4. Introduction

The aggressive scaling of MOSFETs started and the semiconductor industryhas

showcased a spectacular exponential growth in the number of transistors per

integrated circuit for several decades, as predicted by Moore‟s law [1].The doubling

of transistor density was first observed by Gordon Moore,the co-founder of Intel in

1965 and is commonly referred to as Moore's law.This prediction has been the case

for many years and remarkably followed bythe semiconductor industry for more

than the last 50 years as presented in the Fig. 1.1. The figure shows the exponential

increase in number of transistors in the computer processors with the time. The

5
main driving forces behind the gatelength scaling are the higher switching speed

and increase of packing density.Industry has been following the graph as predicted

by Moore 1965. The 2010 update to the International Technology Roadmap for

Semiconductors (ITRS)predicted that growth will slow at the end of 2013. The

processor speed almostfixed between 1.3GHz and 2.8GHz, after 2010 which is

YEAR

barely double but what needs to be kept in mind is that the 2.8GHz is a QUAD CORE

[2],[3] while the1.3GHz is a single CORE. This means that the actual power of the

2.8GHz would be found if you multiply by four though the individual processor

speed is fixed.To continue to improve the performance of the circuits to integrate

morefunctions into each chip, feature size has to shrink. As the number of

transistors has increased, the amount of power per unit area is growing and heat

6
removal has become a concern. Though the supply voltage has scale down to 5V

to2.5V, power dissipation has not reduced[atanu kundu reference]. Aggressive and

continuous scaling of device features into the nano regime according to Moore’s

law to achieve highchip density and speed, and low power consumption has a

significant impact in terms of leakage current and powerdissipation effects. Leading

companies such as TSMC, GlobalFoundries,Intel, etc. are presently searching for

emergingdevices to replace conventional devices in consumer productsfor

suppression of short-channel effects (SCEs). In particular,there is a focus on devices

which act as FETs but use band-to-band tunneling (BTBT) in their ON-state as

well(ankur behoer). as in the transition between the OFF- and ON-states [1,2].BTBT

relies on the flow of minority charge carriers from the valence band of the source to

the conduction band of the channel region. This.BTBT mechanism can occur at both

the source–channel and drain–channel junction. The TFET is one such device, having

the ability to reach sub thresholdswing (SS) below 60 mV/dec as well as being

robust to SCEs [3,4]. The IOFF value of a TFET is only that of a reverse biased diode.

However, lowON-current (ION) and ambipolar behavior (conduction in both

directions) remain as two hurdles for TFETs based on silicon (Si), due to its large

indirect energy bandgap. To overcome this limitation, researchersfrom across the

world have tried and presented many associated structures and materials to

achieve improved device performance, including the double-gate (DG) TFET

withhigh-k dielectric presented by Kathy Boucart et al. [5]. Furthermore,Zhao et al.

proposed Si–GeTFETs for use in analog applications [6]. However, achievement of

7
good analog/RFperformance is limited by their planar structure. In this regard,

three-dimensional (3D) gate-all-around (GAA) structures with small, nanowire

dimension and underlap structureare expected to have a beneficial impact on the

tunnelling behavior, because of their short screening length (λ), volume inversion,

and enhanced gate controllability over the channel(ankurbehor). [7]. Note that, in a

GAA TFET, the gate is wrapped around all the sides over the channel, resulting in

the maximum BTBT due to volume inversion across the source–channel junction.In

particular, we reported [8] detailed investigations on cylindrical (Cyl) GAA-TFETs

with three structures based on spacer engineering. Spacers are insulators required

for isolation,to prevent carrier leakage over the gate edge. Based on literature on

fabricated devices [9,10], use of such spacer scan prevent source/drain dopants

from being implanted through any thinner faceted regions. Jhan et al. proposed

ananowire TFET with an asymmetric gate to achieve high ION[11].Note that TFETs

have a high electric field in the channel,mainly in the tunneling region at the source

end dueto enhanced electric fields from the source compared withconventional

metal–oxide–semiconductor field-effect transistors(MOSFETs). A few researchers

have also worked on TFET devices with optimized source/drain underlap, to

suppressthe ambipolar characteristic. Moreover, [12] proposed underlap in the gate

and drain to suppress the ambipolar characteristic,while Chattopadhyaya et al.

reported the impactof gate overlap/underlap on the performance of a Si-

TFETdevice [13], and Lee et al. [14] predicted that drain underlap in a GAA-TFET

could improve the OFF-state currentIOFF. However, they also found that scaling of

8
the channellength (Lch) to below 40nm caused a gradual decrease in the driving

current and significantly degraded the ION/IOFF ratio and SS, representing a major

performance hurdle in terms ofthe DC and analog/RF characteristics of such

devices.Moreover,other approaches actually increase the drain-to-source channel

length, significantly reducing chip density [14]. Inaddition, the hetero-gate dielectric

approach has also beenemployed to improve device performance [15], albeit

limitedto analysis of the impact of a hetero-spacer on the GAA TFET. Moreover,

analysis by Anghel and Chattopadhyayet al. revealed that the high-k gate dielectric

is responsiblefor the enhanced ON-current [13,16], although their analysis did not

include further detailed investigations on spacer engineering.As stated above,

spacers are insulators required for isolation to prevent carrier leakage over the gate

edge, thus designing a structure with a tuned spacer plays a vital rolein achieving

high BTBT across the source–channel junctionwithout depletion of the source/drain

fringing field towardsthe edge of the gate. Furthermore, most previous such

workhas been based on planar technology, which limits deviceperformance for

circuit applications. In addition, Kao et al.proposed the concept of direct and

indirect BTBT in germanium(Ge) TFETs [17] and also analyzed a modelingapproach

for tensile-strained Ge-TFETs [18]. Besides, Kimet al. [19] proposed aGe-source

TFET. The Ge-source designachieves much higher ON-state drive current ION due to

thenarrow bandgap and high BTBT rate compared with Si, for. use in low-power

applications. However, at low gate biases,lateral tunneling at the drain–channel

junction was found tobe a dominant factor, effectively increasing the

9
subthresholdor OFF-state leakage current (IOFF). Thus, it is difficult tosatisfy the

performance requirements of low-power applications

using only small-bandgap heterojunctions. This limitsfurther device scaling, as

decrease of the BTBT causes SCEsand degrades device performance. In this regard,

identificationof an optimized 3D structure that can improve thedriving current as

well as the analog/RF characteristics withoutincreasing IOFF is of great importance

for low-powermodules for use in Internet of Things (IoT) applications.Therefore, in

this work, we optimized the performance of adesign using a Ge source based on a

hetero-spacer dielectricwith a drain-underlap structure to improve the analog/RF

performanceof the 3D cylindrical (Cyl) gate-all-around (GAA)TFET. Here, use of a Ge

source increases the tunnelingconduction of charge carriers, which helps to

decrease thedepletion barrier width at the tunneling junction and increase the

tunneling rate; thus, high ON-current characteristics areobtained. Here, IOFF was

effectively suppressed by using a DU structure with fringing-field engineering. The

fringingfield was effectively implemented using the concept ofa hetero-spacer

dielectric placed over the source and drainregions.Furthermore, in the design of the

proposed structure, weachieve a DU by varying the gate length while keeping other

values, i.e., drain, source, and channel length, constant,whichis significant for high

chip density and reduces the complexityof fabrication using complementary metal–

oxide–semiconductor (CMOS)-compatible processes. In addition,asymmetry in the

spacer dielectric introduced between thesource and drain reduces the ambipolar

characteristic of theTFET. In addition, this approach has merits in terms of

10
highmobility and flexibility over a wide range of bandgap, reducingthe ambipolar

behavior of such devices. In addition tohigh performance, device reliability is always

a major concern.Previously, most simulation work has been carried out assuming

ideal direct tunneling for the semiconductor bodywithout any defects, which cannot

adequately explain thenonideal behavior within the semiconductor body. Note that

processes applied during device fabrication induce radiationthat can cause damage

resulting in interface defect-assistedtunneling, which can reduce device reliability

and lifetime[20,21].In this regard, we reported [22] the effects of trap-

assistedtunneling (TAT) in a GAA-TFET with the aim of improvingreliability. In this

work, we also considered experimentalnonidealities such as interface defects and

phonons whileincluding the effects of traps in the 3D simulations.Althoughwe do

not claim to have proved device reliability, we haveanalyzed the device under real

fabrication conditions toimprove reliability.(ankur behor)

Motivation for Present Research:

The explosive growth of communication technology has created mass consumer

market for Radio-Frequency (RF) electronics. Mobile communications as an example

is one of the fastest growing areas over the past decade and semiconductor devices

for RF applications are the backbone of advanced communication systems. In

addition to digital circuits, emerging nanoscale MOSFETs remain a strong contender

for analog and RF applications in the wireless communications market. In addition

to the digital circuits, CMOS technology has gained extensive importance in analog

11
and RF circuits due to its low cost, high integration capability and low noise

performance. Today the challenges CMOS technology is facing in terms of severe

Short-channel effects (SCEs) arising from the extremely scaled dimensions has

resulted in the need to explore new device architectures and design. Recent studies

reveals that there are several novel device structures such as Tunnel FET,

heterostructure MOSFETs, nanowires(nw) Tunnel FET, FinFETs, junctionless

transistors, CNTs, etc. are emerging as strong contender to replace conventional

planar bulk transistors. In the deep sub micron regime, these novel device structures

exhibit promises to replace the conventional bulk MOSFETs due to their higher

immunity against the SCEs, low leakage current, CMOS compatible technology, high

Ion/Ioff ratio, sub 60mV/dec and improved subthreshold slope with the requirement of

lower power supply.(synopsis).

As the downscale of CMOS technology tends to approaches physical limitations,

there is a requirement of new alternatives and modified device structures to meet

the challenges of scaling. In view of this many novel structures have been proposed

in the recent years in the nanoscale regime to replace the conventional devices so

to maintain the pace of the technology. One such structure is the double-gate

transistor, proposed in the year 1980s [3,4] which has the ability to improve short

channel effects by deploying a double-gate architecture instead of the traditional

single-gate architecture. Recent studies reveals that there are several novel device

structures such as Tunnel FET, heterostructure MOSFETs, nanowires(nw) Tunnel FET,

FinFETs, junctionless transistors, CNTs, etc. are emerging as strong contender to

12
replace conventional planar bulk transistors. In the deep sub micron regime, these

novel device structures exhibit promises to replace the conventional bulk MOSFETs

due to their higher immunity against the SCEs, low leakage current, CMOS compatible

technology, high Ion/Ioff ratio, sub 60mV/dec and improved subthreshold slope with

the requirement of lower power supply.(synopsis).

. As the downscale of CMOS technology tends to approaches physical limitations,

there is a requirement of new alternatives and modified device structures to meet

the challenges of scaling. In view of this many novel structures have been proposed

in the recent years in the nanoscale regime to replace the conventional devices so

to maintain the pace of the technology. One such structure is the double-gate

transistor, proposed in the year 1980s [3,4] which has the ability to improve short

channel effects by deploying a double-gate architecture instead of the traditional

single-gate architecture.Other possible solutions include SOI devices, strained-

silicon FETs, carbon nanotube FETs. Finfield-effect transistors (FinFETs), triple-gate

(tri-gate) MOSFETs, surrounding gate MOSFETs, tunnel FET, Π- gate/ Ω-gate

structures proposed subsequently to improve the device performance and the

reliabity [5-8].. In order to achieve high-speed and high packing density of the logic

circuits and memories, the MOSFET dimensions in CMOS technology, have been

reduced continuously for quite some time now. With the shrinkage of its

dimensions, the devices have achieved cutoff frequencies in the giga-hertz range

making this technology also very attractive for analog and mixed signal system on-

chip applications. However, scaling of devices leads to short channel effects such as

13
degradation of device reliability due to gate leakage current (hot-electron effects)

and drain- induced barrier lowering (DIBL). These SCEs need to be eliminated or

minimized for proper device operation [1]. The main reason for short channel

effects is the drain control and the technique is to make the step-function like

shaping of the surface potential since it screens the effect of drain on the source-

channel barrier of the device [2]. The step rise of the surface potential profile can be

generated by using more than one material with the different work functions for

forming the gate contact of a MOSFET. This technique has been implemented in the

conventional silicon-on-insulator MOSFETs and multigate(Cylindrical

surrounding-gate MOSFETs with electrically induced source/drain

extension)(cong li).

According to [1-3], Junctionless MOSFET is an essential promising structure than

conventional bulk MOSFET because.Conventional transistors requires different

types of doping. Scaling of conventional MOSFET becomes difficult to meet the

thermal budget of the fabrication of abrupt junction. Junctionless devices facilitates

a simpler fabricationThe source-channel-drain having the same doping Provide

Higher Scalability Capability to Reduced SCEs. Theoretical and practical

investigations of junctioness devices have already been addressed the double-gate

(DG) [4], Trigate [5] and cylindrical nanowire FET [2]. Among them, cylindrical

surrounding gate JL FET is most promising due to its superior gate-controllability. On

the other hand, the gate-material engineering [6] results in higher carrier transport

14
efficiency, higher transconductance and SCEs suppression due to the modified the

gate transport efficiency by modifying the electric field pattern and the surface

potential along the channel. In order to combine the advantage of JLFET,

surrounding gate structure (SRG) and gate-material engineering, dual-material

junctionless surrounding gate (DMJLSRG) transistor is proposed. In order to

introduce their advantages over single material juncionless surrounding gate

(SMJLSRG) MOSFET, there is a need to develop simple model. To analyze

subthershold operation, instead of using central-channel conduction, depth of

effective conducting path (deff) presents the location, where the punch through

current mainly occurs at subthershold conduction with ECPE conduction mode [7-

8]. Therefore, in our developed analytical model ECPE mode of conduction is also

considered.(1st paper).

The main work of this paper is to explore the SCEs and HCEs features of JLSRG and

compare its performance with that of conventional SG. Numerical simulation results

demonstrate that. DMJLSRG structure exhibits significantly improved performance

in terms of threshold voltage roll-off, drain induced barrier lowering, subthreshold

swing, electrical field and Surface potential . As the minimum feature size of the

MOSFET device reach submicron field, Drain Induced BarrierLowering(DIBL) effect is

increasingly prominent[1],[2],[3], which is due to a significant field penetrationfrom

the drain to the source. Because channel length(L) is reduced and the voltage across

drain tosource(Vds) is increased, the drain depletion region moves closer to the

source depletion, resulting in fieldpenetration. Due to this field penetration, the

15
potential barrier at the source is lowered, leading toincreased injection of electrons

by the source over the reduced channel barrier, giving rise to shiftedthreshold

voltage.The influence of DIBL to Small-scaled MOS device could be analyzed by the

shifted threshold voltageobtained by solving a 2-D Poisson’s equation

numerically[4],[5] or experimentally[6],[7]. DIBL effect in either bulk Si MOS or SOI

MOS have been reported[8][9], however, there are literatures rarely reportedfor

the DIBL effect in strained Si MOS, which is a hotspot to improve performance of

the MOS device inrecent years[10][11]. In this paper, an analytical threshold voltage

model of strained Si nMOSFET isdeveloped to analyze the DIBL effect, which is

based on solving 2-D Poisson equation. By simulation, therelationship between DIBL

and channel length, gate oxide thickness, Ge content, and channel

dopingconcentration has been analyzed and the way to restrain the DIBL effect has

been acquired. This modelwhich has been proved by ISETCAD simulator is

significant for the design of high performance strained Si nMOSFET to restrain the

DIBL effect.( Study of Drain Induced Barrier Lowering(DIBL) Effect

forStrained Si nMOSFET (JiangTao Qu∗

Some of the greatest challenges of modern society are related to energy

consumption, dissipation andwaste. Among these, present and future technologies

based on nanoscale materials and devices hold great potentialfor improved energy

consumption, conversion, or harvesting. A prominent example is that of integrated

electronics, where power dissipation issues have recently become one of its

16
greatest challenges. Power dissipation limits the performance of electronics from

mobile devices (~10-3 W) to massive data centers (~109 W), allprimarily based on

silicon micro/nanotechnology. Put together, the energy use of the United States

information technology (IT) infrastructure is currently in excess of 20 GW, or 5-10%

of our national electricity budget, withan approximate breakdown as shown in Figs.

1c and 1d [1]. Importantly, the figures for data center energy consumption have

doubled in the past five years, with waste heat requiring drastic cooling solutions

(Fig. 1c). Such challenges are also evident at the individual microprocessor (CPU)

level, where the race to increase operating frequency beyond a few GHz recently

stopped when typical dissipated power reached 100 W/cm2 (Fig. 1b), anorder of

magnitude higher than a typical hot plate [2]. Such electronic power and thermal

challenges have negative impacts from massive database servers to new

applications like wearable devices, medical instrumentation,or portable electronics.

In the latter situations, a basic trade-off is one between the available functionality

and the need to carry heavy batteries to power it.Despite tremendous progress

over the past three decades, modern silicon transistors are still over three orders of

magnitude (>1000×) more energy inefficient than fundamental physical limits, as

shown in Fig. 1a.These limits have been estimated as approximately 3kBT ≈ 10-20 J

at room temperature for a binary switch with asingle electron and energy level

separation kBT, where kB is the Boltzmann constant and T is the absolute

temperature[3]. In the average modern microprocessor the dissipated power is due,

in approximately equal parts, to both leakage (or “sleep”) power and active

17
(dynamic) switching power [4], as detailed in Section 2. Power dissipationis

compounded at the system level, where each CPU Watt demands approximately

1.5x more for thesupply, PC board, and case cooling [1]. Such power (mis)use is

even more evident in systems built on otherwisepower-efficient processors, e.g. in

the case of the Intel Atom N270 (2.5 W power use) which is typically pairedup with

the Intel 945GSE chipset (11.8 W power use) [5]. At the other extreme, data centers

require 50-100%additional energy for cooling (Fig. 1c), which is now the most

important factor limiting their performance, notthe hardware itself.If present

growth trends are maintained, data center and overall electro nics power use could

reach one third of total US consumption by 2025 [1]. Worldwide, the growth trends

could be even steeper, given that technoloE.Pop Nano Research 3, 147 2gically

developed regions suchas the US, Western Europe andJapan currently account for

58percent of the world’s computers,but only 15 percent of theworld population.

[6]. Such energy challenges for the electronicsinfrastructure stem notonly from the

power supply sidewhich call for new energysources, efficient batteries,

orthermoelectrics, but also fromthe demand side, i.e. the need formore energy-

efficient computingdevices. To put it in financialterms, data centers consumedmore

than 7 GW or $4.5 billionin 2006 (Fig. 1c) [1]. The estimated108 million PCs in

officesacross the US had an annualenergy cost of $4.2 billion in2008 [6]. More

troubling, theamount of equivalent CO2 emissionsgenerated is

approximatelyequivalent to that of 5 millioncars, comparable to the entirestate of

Maryland.In fact, such estimates arelikely to be conservative, missingthe power

18
consumed byhome PCs, routers, networks,and the Internet backbone

wheredetailed studies are not available (however, a thought-provoking study of

energy consumption by e-mail SPAMhas recently been made [8]). Nevertheless, the

overall negative impact of these trends (to predicted 2025 levels)on energy

supplies, budgets, and the environment in terms of equivalent CO2 emissions is

staggering. Thus,breakthroughs in our understanding and improvement of energy

efficiency in nanoelectronics will also have aglobal effect, impacting the entire

structure of modern society.On a broader scale, just over half the man-made energy

in the world is wasted as heat (1013 W), from powerplants and factories, to car

engines and the power bricks on our laptops. Efficiently reclaiming even a small

percentageof such wasted heat would itself nearly satisfy the electricity needs of

our planet [7]. The fundamentalissues at hand are, in fact, a two-sided problem: On

one side, there is a significant need for low-energy computingdevices, which is

perhaps the biggest challenge in micro/nanoelectronics today. On the other side lies

thechallenge of waste heat dissipation, guiding, or conversion into useful

electricity.( Energy Dissipation and Transport in Nanoscale

Devices)

(TFET) The design of most ICs is nowadays constrained by the budget of dissipated

power. The energy efficient ICs expected to be working with a VDD less than 0.5V

[1], need a steep subthreshold swing. For a conventional bulk MOSFET, the best

19
possible Subthreshold swing (SS) is limited (60mv/dec). This fixed slope means, if we

want to shift VT by 60 mV, then the price to pay is an increase of one decade of off-

current and in turn of static power. In this respect, International Technology

Roadmap for Semiconductors (ITRS) [2] has specified Tunnel FET (TFET) as most

promising solution for obtaining Steep Subthreshold swing [3]. In contrast to a

MOSFET where voltage-controlled modulation of charge is important, TFET relies on

the modulation of the potential in the device enabling or disabling tunneling from

the valence band to the conduction band. When a Tunnel FET is OFF, only p-i-n

diode leakage current flows between the source and drain, and this current can be

extremely low (less than a fA/μm). But, when a positive voltage is applied to the

gate, on the other hand, the energy bands in the intrinsic region are pushed down

and tunneling takes place between the valence band of the p+-region and the

conduction band of the intrinsic region. The energy barrier width for band-to-band

tunneling is the single most important factor that determines the amount of drain

current through a Tunnel FET [4]. There have been experimental demonstration of

TFET offering SS less than 60mv/dec. A double-gate (DG) TFET offers the additional

advantage of better electrostatic control [5-6] to improve the ON-current and

subthreshold swing. Recently, MOS technology has become a serious contender for

RF and analog applications which was previously dominated by the bipolar

technologies with the recent trend to reuse the mainstream digital CMOS

technologies for analog/RF applications [7]. Therefore, it is important to study the

RF/analog performance of devices optimized for digital circuits for possible use in

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analog/mixed-mode circuits within a SoC. As a result, a deeper understanding of

scaling effects on RF/analog performance parameter is crucial. Therefore, for a

scaled TFET, RF device modeling and parameter extraction is not only important for

proper understanding of the characteristics of the device but also a prerequisite to

design the ICs for RF/analog application [8-9]. The RF/analog performance

investigation of TFETs is still largely unexplored except a few reported [10-11]. (TFET

FROM NANOCON CONF PUNE)

ITRS have identified tunnel FETs as an alternative to conventional devices[1] in order

to obtain steep subthreshold swing (<60mV/dec.) and less static power dissipation

[2]. TFET relies on the principle of tunneling for injection of carriers from the source

to the channel. Therefore, the width of the energy barrier is the single most

important factor that determines the rate of tunneling and in turn the drain current

of the TFET [3,4]. III–V semiconductor based TFETs exhibits significant improvement

in terms of ON-current and subthreshold swing as compared to Si-based TFETsDue to

its lower effective mass, smaller effective tunneling barrier width and low

bandgap[1-3].InAs-based NW TFETs are promising for high performance digital

application. However, the analog and RF performance of a InAs based Nanowire

Tunnel FET for mixed signal SOC application is crucial [1-2] which has been mostly

unexplored except few [3-4].Moreover, linearity study of NW InAs-based TFET has

not been yet reported.

This necessitates the RF/analog and linearity performance investigation of InAs-

based TFET. According to [1-3], Staggered hetero junction TFET is an essential

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promising structure than conventional TFET because Enhancement in ION and

decrease in IOFF due to the smaller effective mass, narrow band gap and lower

effective tunneling width.Staggered bandgap alignment provides a doping

modulated steeper band structure profile at source channel junction leading to

increase in BTBT tunneling probability[1]Among various III-V based staggered

heterostrure the band gap and band alignment of mixed As/Sb based heterostrucre

can be used .Thus mixed As/Sb InxGa1-x As/GaAsy Sb1-y staggered gap heterostructre

appears to be most promising material system to boost the TFET performance. (TFET

from prethesis )

JUSTIFICATION OF WORK: Therefore, the analytical modeling of nano-dimensional

MOSFET is a prime requirement to investigate its down-scaling ability and to judge

their Short-channel effects performance parameter figure-of-merits. Till now

researchers has been focused mainly on the digital applications of the emerging

nanoscale devices. However, the analog and linearity performance is still an

unexplored area, has not been received enough attention and needs to be

investigated also. The modern day communication requires low distortion and linear

systems as a building block for their design and implementation. Because, increased

traffic in the neighboring frequency ranges forces more constraints on the linearity

matrices of RF systems, and intensify the need for more effective linearization

techniques. Linearity is considered as one of the most important requirements in

all RF communication systems.Recently TFETs have involved a broad research

interest because of its direct BTBT and easy integration on Si substrate. It shows a

22
good output current saturation, because it indicate reduced short-channel effects,

such as drain-induced barrier lowering (DIBL), in the device and makes it also

attractive for analog/mixed-signal applications. This work TFET keeps most

promising candidate than MOSFET because of its steep sub-threshold swing which is

less than 60mv/dec. In contrast to a MOSFET where voltage-controlled modulation

of charge is important, TFET relies on the modulation of the potential in the device

enabling or disabling tunneling from the valence band to the conduction band. TFET

offers significant power dissipations having (supply voltage below 5v) low off

current. Scaling of conventional MOSFET becomes difficult to meet the budget of

abrupt junction. A multi-gate TFET offers an additional advantage of better

electrostatic control in order to improve the ON-state current and sub threshold

swing. In addition to this TFET reduces the short channel effect, thermal stability is

more in comparison to MOSFET. However, the early reported Silicon based TFET

suffer with low ON –state current Ion due to the high effective carrier mass and

limited transmission through the large tunneling barrier. This can be done by

modifying the structure of TFET such as heterojunction TFET, staggered hetero

junction TFET. For this purpose, III-V based staggered hetero junction which exhibit

an enhancement in ION and decrease in IOFF, because of smaller effective mass, lower

effective tunneling width and narrow band gap. A recent work for the structural

properties of mixed As/Sb staggered TFET has been carried out for improving the

TFET performance for low power applications. Thus a mixed As/Sb In xGa1-x

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As/GaAsy Sb1-y staggered gap heterostructure material are used to increase the

Tunnel FET performance because of its better device parameters.

Distinct asymmetric channel-engineering, gate-material engineering improve the

gate transport efficiency by changing the electric field pattern and the surface

potential along the channel, resulting in increasing carrier transport efficiency,

advanced trans conductance and SCE suppression. Because of gate engineering, it

increases the gate contrability. In surrounding double or triple gate effect of drain

potential variation is less, DIBL (Drain Induced Barrier Lowering) is less, which

suppress the short channel effect. On the other hand, the gate-material engineering

results in higher carrier transport efficiency, higher transconductance and SCEs

suppression due to the modified the gate transport efficiency by modifying the

electric field pattern and the surface potential along the channel. Considering a dual

material gate (DMG) MOSFET, where two metals M1 and M2 of different

workfunction are combined together laterally. The workfunction of M1 is greater

than M2. For which it introduce a step function in the potential along the channel

such that sharing of electric field is improved at the source side to increase the

carrier velocity, which efficiently minimise the hot carrier effects, and more control

of gate over the conductance of the channel to increase the carrier transport

efficiency. This so-called gate material engineering.

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Analytical model development of nanoscale MOSFET for evaluation of basic

quantities like

(i) Surface Potential

(ii) Electric field

(iii) Threshold voltage

(iv) DIBL

OBJECTIVE OF THE PROPOSED WORK:

Therefore, in this work, we are dealing with theory, modeling, design and

simulations of nanostructured materials and devices with nano dimensions to find

their suitability in linear RF circuits/systems. The objective of the proposed work is:

1. To study the effect of gate engineering and to find drain-induced

barrierlowering (DIBL), subthreshold slope, threshold voltage roll-off, in a

comparative manner.

2. To study the linearity and analog performance of nanoscale devices with sub-

100nm channel length to determine their suitability for analog/ RF applications.

Therefore, this work is concerned about different linearity, distortion and analog

performance metrics like 2nd order/third order variable intercept point, 2nd

order/ 3rd order Inter modulation distortion, 1-dB compression, 2nd order/3rd

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 order intercept points, transconductance generation factor, drain-to-source

output resistance Rout.

2. To study the RF performance such as cut-off frequency, maximum frequency of

oscillation, gain bandwidth product.

RESEARCH PROBLEM STATEMENT:

In this work, the remedies of major short-channel and non linearity effects

exhibited by deca-nanometer MOSFETs are studied by means of analytical

modelling and the wide numerical simulation studies. this work is to provide the

impact of various device physics and device scaling on the RF performance analysis

and investigation of various linearity matrices due to their dominant role for

today’s RF systems and circuits using analytical model and simulation.Unique

features offered by different novel device structures such as InAs-based nanowire

TFETs, junctionless surrounding gate MOSFETs and staggered herojunction TFETs

structure have been studied to address the challenge of increasing short-channel

effects and to show the efficacy to obtain improved analog/RF and linearity

performance for deep-submicron VLSI integration. This is accomplished in terms of

the following transitional stages.

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  Literature survey of potential promising building nanoscale devices for usage

in highly linear RF electronics and circuit applications

 Modeling and simulation of silicon based and other emerging nanoscale

transistors to mitigate short-channel effects in order to continue

downscaling.

 Modeling of complex nanoscale devices for usage in RF circuits.

 RF/ linearity performance assesment of nanoscale devices under

consideration.

SCOPE AND ORGANISATION OF THESIS : The prime objective of this

thesis is to study the performance analysis of NANO-MOS structures. The thesis comprises

of six chapters. Chapter one introduces the topic of research and its historical background.

It begins with a brief discussion on MOS transistor scaling scenario and its current

limitations. It also gives a high light for motivation of Present Research along with the plan

of work. A brief introduction towards the research area is also provided. The chapter briefly

explains the analytical model of triple-material double-gate MOSFET. Motivation to

suppress SCEs by developing an analytical model of TM-DG MOSFET. Motivation to study

the outcome of gate-length downscaling on RF/analog and linearity testing of a InAs-based

NW TFET. Motivation to study RF/analog and linearity performance of DG junctionless

MOSFET. The chapter concludes the organization of author work and presents the outline

of the thesis.

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 Chapter two describes the over view of various types of conventional MOSFETs and

the issues related to scaling. A brief discussion on different types of advanced MOSFET

devices with gate engineering and gate material Engineering is discussed in detail. The

fundamental models used in the simulation work and the calibration of simulation model

for the proposed devices are also explained.

The third chapter contains an introduction to the novel device Triple Material

Double Gate MOSFET. In this chapter, a logical version of surface potential and threshold

voltage of gate-engineered double-gate MOSFETs has been developed. On the basis of

developed analytical model, a comparative study between different gate-engineered

MOSFET structures of the same dimensions has been carried out in order to investigate

their immunity against SCEs. The outcome of various length ratios of three channel regions

related to three different gate materials of TM-DG structure on the SCEs characteristics

parameters have also been discussed. The DC performance and key device metrics such as

DIBL, SS, Ion/Ioff, VT rolls-off, variation of surface potential are evaluated using simulation.

The study helps to have a enhanced understanding of the device performance parameters

which lead to have a improved device design principle for analog and radio frequency

applications. The proposed device models used in the simulation work is calibrated by

comparing with previously published mathematical model results for proper validation.

The fourth chapter systematically analyzes different performance parameters of

analog, radio frequency and linearity with downscaling of gate-length of a InAs-based NW-

TFET. The analog/radio frequency (RF) and linearity performance of an InAs-based

nanowire (NW) tunnel field-effect transistor (TFET) is studied and compared with InAs-

based NW MOSFET of identical dimension. Different analog/RF and linearity key figure-of-

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merits like transconductance generation factor, output resistance, intrinsic gain, cut-off

frequency (fT) and 1-dB compression point are extracted and the effect of gate length down

scaling on those parameters has been studied. Moreover, an in-depth comparison between

InAs based NW TFET and conventional MOSFET has also been provided in order to

demonstrate the superiority of InAs based NW TFET to become a competitive contender by

replacing conventional MOSFET for Analog/Mixed signal System-on-Chip (SOC) applications.

The trend of the key RF/analog performance parameters as a function of gate-length

downscaling has also been provided.

The chapter five explains the analysis of RF/Analog and Linearity

performance of a Junctionless Double Gate MOSFET. The analog/RF and linearity

performance of a Junctionless Double Gate MOSFET (JL DGMOS) is investigated

using the numerical TCAD device simulator. In analog and RF circuit application,

linearity testing and RF performance is a major issue that is encountered due to

non-linear behavior of the devices. Therefore, in this paper, different RF/analog

and linearity performance figure of merits like Transconductance (gm), Intrinsic Gain

(gmRout), Transconductance Generation Factor (gm/ID), Cut off frequency(fT ),

Maximum frequency of oscillation (fmax), Gain Bandwidth Product(GBW), Variable

Intercept Point of Second order(VIP2), Variable Intercept Point of third order(VIP3),

Inter Modulation Distortion(IMD3), Third Order Intercept Point(IIP3), 1-dB

compression has been presented. Moreover, the effect of gate length down scaling

on these performance parameters has been carried out. The results indicates that

the down scaled JL DGMOS shows great promise to become a competitive

29
contender for Analog or Mixed signal System-On-Chip(SOC) application by

demonstrating a significant improvement in its RF performance with the

downscaling of its gate length.

Finally in the last chapter the major conclusions and outcomes of the present

work are discussed. The chapter ends with some suggestion and directions for future

work.

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