EEE F244

Microelectronic
Ci it
Circuits
BITS Pilani
Pilani Campus
p
 BITS Pilani
Pilani Campus

Common source amplifier

Single stage MOS amplifier
with
ith drain-to
d i t gate
t ffeedback
db k bias
bi

Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.

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CSA with current mirror bias

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CSA with potential divider bias
Ac model with dc bias

• No change in ac model with different

biasing schemes
• So, for ac analysis, biasing circuit is not
considered
T model

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Common Source

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Why
y do we need a capacitor
p Cs?

• Without Cs. Vgs ≠ vin,

• As
A a resultlt a.c currentt becomes
b smallll
[gm (vgs-vx)]

• Hence drop across Rd reduces

• Gain reduces
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 Bits, pilani
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Pmos CSA
Common Source

• Bias point
• Given--Kn’= 80uA/v2, Vt=1v, Vdd= 5v

• Suppose, we
e want
a t Id= 100uA,
00u , Vds= 2.5v,
5 ,

• This gives ----

• Rd= 25k
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Design
g of common source for gain
g
• To set gain
• Av= 30 = - gm [ RD || ro ]

• ro=1/
1/ λId = 1M ohm;
h λ=λ .01V
01V-11

• gm= 1.2
1 2 mA / V = 2 Id / Vov

• Hence, Vov= 0.166V [designers choice depends on

VDD, Small value
al e for small ssupply
ppl ]
gm= 1.2 mA / V = Kn’ (w/L) Vov

• W/L= 90.3, Vgs= 1.166V

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Practical design
• Sketch VTC
• Choose bias current, choose a w/L
• Find corresponding Vgs
Vgs, Vds
Vds, re calculate Rd
Rd,
w/L
• Draw the schematic in eda tool
• Set voltages by applying sources
• Do .dc
dc analysis
• Check all dc current and voltages
• Apply ac , check ac output
output. Do .ac
ac analysis
Phase relationship

Leading Phase Difference Lagging Phase Difference

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

gm/ Id—
transconductance generation efficiency
• It is strongly related to the performances of analog
circuits

• 2) It gives an indication of the device operating region

region.

• 3) It provides a tool for calculating the transistors

dimensions

• The g
gm/ID ratio is a measure of the efficiency
y to
translate current (hence power) into transconductance;
i e the greater the gm / ID value,
i.e., value the greater the
transconductance we obtain at a constant current value.
Intrinsic gain
How to maximize gain in active
region?

• Av increases with W/L, VRD, or by dec ID

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Trade offs
• W/L increased keeping ID and VRD
constant
---greater device capacitance at output , time
constant increases, speed of response is
affected
---less overdrive voltage reqd. ( as Id constt.)
so vomin reduces
output swing range increases, bias point will
shift
----gain increases
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Bias point for increased (w/L)--- ID and V RD constant

(w/L) 2 large

(w/L) 1 small

vgs 2 vgs 1
small large

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 (w/L) 2 > (w/L) 1
Id =
Vdd/Rd
ID and VRD constant

Q1, Q2 vgs1

(w/L)2 large vgs2

Vov2 less

Less lower
swing
(w/L)1 small
Vov1 more
More lower swing

Vdd
vov2 vov1
VdS
less more
VRD increased keeping Id and W/L
constant

• Gain
G i increases
i
• Vdd - VRd inc., or Vout max reduces,
output swing range decreases,
MOS shifts towards triode region,
V lt
Voltage swing
i iis lilimited
it d

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Bias point for increased VRD ------ID and w/L constant

vgs 1,2
12

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 (VRD)2 > (VRD)1
Id=
Vdd/Rd Id and W/L constant

(VRD)2 large
Q2
Q
vgs
Q1
Less lower swing

(VRD)1small

More lower swing

vds2 vds1 Vdd

less more VdS
ID dec. keeping VRD and W/L const.
• ID reduces---to keep VRd constant Rd
must increase,
So, Rout shd. be increased
time constant increases,
So speed of response is affected
So,
 Vgs must dec.

• Gain increases
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Bias point for decreased (ID)--- (w/L) and VRD constant

vgs 2 vgs 1
small large
g

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 VRD and W/L constt. (Id)2 < (Id)1
Id=
Vdd/Rd

Q1
vgs1
(Id) 2 small
vgs2
Vov2 less
Q2
Less swing
((Id)1 large
Vov1 more
More swing

Vdd
vov2 vov1
VdS
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Voltage
g amplifier
p model of CSA

Ro

+ + +
vi Ri vo
Avvi
- -
-
Maximum gain possible (intrinsic gain)

• Av= - gm ro
• Make Rd infinite

• But this will make

VRd=Vdd, MOS goes
to cutoff

• How?---Rd replaced
by current source
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GAIN and SWING COMPATIBILITY

• What if gain is high but not sufficient

voltage swing ?

• Output will be distorted as MOSFET slips

i LINEAR/ CUTOFF region
in i

• Hence, output voltage swing calculation is

important
p
Output voltage swing under dynamic
state
t t
• Constraint---MOS must
remain in saturation
• Vo max≈Vdd
• Vomin Vgs-Vt
• Output DC level[Vdd-IIdRd]
Vdd= 3V
Reduced upper swing

Dc level

Reduced lower swing

Vgs-Vt = 0.2
For symm. signal—dc level shd. be in the middle for max swing
 How to configure
g an Active
current source ?

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Current source load
Pmos current mirror

Rout= ro1 || ro2

-Swing [ Vdd- Vov2] to Vov1

-MOS
OS Cap
Cap. at output increases
c eases
due to M2 RoutCout product inc.
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Output Voltage swing
• Vomax---- Vdd - Vov2
• Vomin---- Vov1

• For Vdd=3v, Vgsp = Vgsn =0.9v, Vt=0.7v

• Vomax---- 0.2v
0 2v
} 2.6v
• Vomin---- 2.8v

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Penalty paid
• Fixed Vgs required to support current bias
• No roll back flexibility for Q point

• Remedy---
• Place a current mirror at source also.
• Prob.
Prob ---Then
Then we have to use Cs to provide
bypass path
• Can
Can’tt we remove Cs??
Effect of technology scaling on
intrinsic gain (C E SCALING)

• MOS scaled down by constant electric

field scaling strategy

• All dimensions scale down by a factor α:

(α > 1: usually α =1.33)

• All voltages scale down by a factor α

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Effect of technology scaling on intrinsic gain (C E SCALING)

• Keeping W/L constt----- Vdd decreases by α

L scaled down by α, W also decreases to
keep ratio constant,
Cox, increases by α-----Id decreases by α---
gm remains constt.
λ increases by α, Id decreases by α---ro
constt
constt.
Hence intrinsic gain does not change
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Guideline--To increase intrinsic gain
by design

• Keep L large
• Keep Id small
• Example---
Keeping
eep g (w/L)
( / ) constant
co sta t
• L’= 4L, W’=4W, I’ = I/4 Vgs ↓
• Intrinsic gain= ½ × 16 8 times increase
½ × 16= 8
• Intrinsic gain’ ≈ [8] original intrinsic gain by
properlyl choosing
h i values
l
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Effect of increasing only L

• Keeping I constt-----
L scaled up by α,α ro increases
L scaled up, W also increases to keep
ratio constant,
constant so gm remains same
Hence, intrinsic gain increases by α
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Effect of increasing
g L on CSA gain
g

• Keeping I constt
constt.-----
L1, L2 scaled up by α, (ro1, ro2) increase
W1 W2 also
W1, l iincrease tto kkeep ratio
ti
constant, so gm remains same
Hence CSA gain increases by ≈ α

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 Active load CS amplifier –
other types of load
• Diode connected load---
b d lloadsmall
bad d ll ↓ I
impedance, leads to
small gain V
I

desirable

V
Vgs
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Equivalent Resistance calc.

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Active load amplifier

p
pmos

Small value
Gain depends on device dim
for same I.

Also on µp if load is pmos

Gain improvement technique for diode
connected load—inc. I1

I1/4

But Vgs of M1 will increase

to carry 4I current. Swing reduces Double gain
Gain depends only on device dim. ---so,
linear amplification,
amplification less distortion

For lin
lin. Amp.
Amp ----Gain
Gain shd
shd. be independent
of bias voltages and current

Reason---
|Av|= gm Rd changes as gm changes with
the input signal swing (though close to Q
point)
Non linearity due to bias dependence
V

vi

Vo—each input point is amplified by a

slightly different gain value

Bad drawing
Triode load

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CSA
CSA----

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ADV. / DISADV.
• No bypass capacitor---------good
• High gain, high swing--------good

• Large capacitance at the output--------bad

• A fixed Vgs
g is reqd
q .----worst --- bias p
point shift with
input signal variation, temp. , process variation

• We need to keep Vgs constant

constant. (or make gain a
weaker function of gm)

• So, allow source node to swing.

• ---Again place a current source at source node or
put a resistor Rs
p

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 Circuit trans-conductance ‘Gm’, ‘Av’
CSA

=gm of MOS

R t  ro1 || ro 2
Rout
 Vout  Vout  Iout
A 
Av  
 Vin  Iout  Vin
Av  R out  G m  g m R out
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Common source
amplifier

with Source Degeneration

Motivation- remove Cs
Motivation
• Aim
Aim----How
How to remove Cs ?
• To allow source node to swing
Put a current mirror sink at source but it has high ro

So, replace
S l currentt mirror
i b
by llow Rs in
i place
l off currentt
mirror sink and remove Cs. Ibias is decided by current
mirror load

--Can we get minimum (ideally NO) reduction in gain??

CSA with Source Degeneration

vout

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Performance variation

• Vgs < vin, gain reduces

• Output impedance will change
• Non linearity decreases as Id varies
smoothly w.r.t vin variations
Without Rs With Rs

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Nonlinearity Error
 Circuit trans-conductance ‘Gm’

ID

ID
gm of MOS

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Circuit trans-conductance
trans conductance

Voltage Gain

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 Trans-conductance variation-
comparison

Gm=

Without Rs With Rs

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Gm, Rout from approximate small signal
model

= gm (Vin-V
(Vi Vx)
Vx= Iout Rs
Gm, Rout from small signal model with ro
and gmb

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 gm

• For Rs=00, Gm = gm
• For Rs ≠ 0, Gm < gm

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Rout

Rout= Rd || Rout’

Rout’ Rout
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Rout
Rout’

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 Why Routt increases due to Rs?

• A high impedance at a node means

if voltage at that node is changed
slightly current through that node
slightly,
does no change much.

• Here we achieve this at Vout node

through negative feedback in vgsvgs.---
• If Vout ↑---Id ↑ (effect comes through
ro)
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• If Vout ↑
↑---Id ↑ ((effect comes
through ro)
• At the same time, due to Vout ↑ , a vs
voltage vs appears at source
• Vs causes reduction in Vgs Vgs, due to
which Id falls more due to square
dependence on Vgs
• Hence Id changes little in
comparison
i tto change
h iin voutt

• So Rout increases
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Voltage gain (from ac model)

If ro >> Rs, Rd
Using GmRout

Gm
Rout
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Gain rewritten (simplified form)

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High / low impedance node
• Look at R= ∆V/ ∆I

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Resistance looking into the source

• C
Considering
id i ro
to be large
• Vx / ix ≈

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Rout by inspection

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Bits, pilani
Gain by inspection

Replace by nmos

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Ideal Current source load
load---problem???
problem???

• Av
Can not change
• Effect of Rs is
negated as I0
(ideal) can not
sustain current
variations
• We want non ideal
active load
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Push-pull
Push pull amplifier

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Power efficiency
• Class A amplifier—conducts
amplifier conducts for full cycle

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Power Efficiency η---power delivered to load
For equal swing in both directions
directions, Vo shd.
shd be biased at Vdd/2
and then current through RL= Vdd/2RL

PL
  100 %
PS
Vdd Vdd
Now _ when _ up  transition ; Vo max  , IL 
2 2 RL
V o  Vdd ; for max Vo
 
Ps  V dd  I
Vdd I
PL  
2 2
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 rms peak vout

-----for max. swing Vdc= vdd/2,

IL=I/2
In up (or down) Transition
Vomax=vdd (or 0), extreme value
Peak vo amplitude
amplitude= vdd/2
Peak current supplied by vdd = I/2
η = 25%

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