Microelectronic

Circuits
BITS Pilani
Pilani Campus
p Anu Gupta
p
 BITS Pilani
Pil i
Pilani Campus

Frequency response of amplifier

Tasks

• Learn estimation of p
poles and zeroes of an
amplifier

• Learn shifting of poles and zeroes to

achieve desired response

BITS Pilani, Pilani Campus

T k
Tasks
 Learn estimation of poles and zeroes of an
amplifier
 L
Learn shifting
hifti off poles
l andd zeroes to
t achieve
hi
desired response
K questions
Key ti

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Why high frequency
operation?
ti ?

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M ti ti
Motivation

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Intrinsic frequency response of
MOSFET

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Why ft is chosen as figure of
merit?
it?

 Why current gain of common source---

Because it is related to transit time from
source to drain which determines max speed
of mosfet

 Why short circuit-

circuit  because current gain is
maximum for short circuited output port
Intrinsic frequency response of
MOSFET

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Ph i l iinterpretation
Physical t t ti off fT :

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Bits, pilani
 MOS unity gain frequency wT
 Limits for MOSFETs:
 Metric –C.S short-circuit current gain unit gain freq.:
 wT = (gm-SCgd)/[s(Cgs+Cgd)]
 wT is approximately = gm/Cgs
 = 3 un(VGS -VT)/2L2
Where gm = (W/L) unCox(VGS -VT) and
Cgs = (2/3)WLCox

 so wT≈ 3 μn(VGS -VT)/2L2

 Design lessons – to increase wT

 bias at large,
g overdrive voltage g ID –swing
g reduces
 minimize L (w in as L2) , λ (= 1/L)increases, ROUT dec.
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 use n-channel over p-channel , NOISE increases
D i
Design guidelines
id li

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I
Impact
t off bias
bi point
i t on fT :

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Frequency response--
transfer function
 A transmission zero is a frequency at which the
transfer function of a linear two-port network
has zero transmission of signal, i.e. Vout=0.

 T
Transmission
i i zeroes att zero frequency
f and
d infinite
i fi it
frequency may be found in high-pass filters and low-
pass filters respectively

 Zero transmission of signal occur in an amplifier if

the input impedance is either zero or infinity.
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Low pass ; transmission zero
att iinfinity
fi it
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High pass; transmission zero
att origin
i i
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Magnitude vs frequency—
both linear scale

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Magnitude
g vs frequency—
q y
mag. linear scale, freq in log scale

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Bode plot—both values in log

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Frequency response-
b d idth
bandwidth
 Ideal frequency response
response---gain
gain does not
change with frequency

 Practical frequency response

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 Bode Plots --Poles, Zeros
Characterization:

K ( s  z1 )( s  z 2 ) ... ( s  z m )
G (s) 
s  ( s  p1 )( s  p 2 ) ... ( s  pn )
s s s
(  1)(  1) ... (  1)
K  z1 z 2 z m  z1 z2 zm
G (s) 
 p1 p2 pn  s  ( s  1)( s  1) ... ( s  1)
p1 p2 pn
K  z1 z 2 z m 
KB 
 p1 p2 pn 
( z1s  1)( z 2 s  1) ... ( zm s  1)
G (s)  K B
s  ( p1 s  1)( p 2 s  1) ... ( pn s  1)
(Time Constant Form.)
Characterization:
Considering the transfer function in the time constant form.
we have 4 different types of terms in the time constant form, these are:

1 1
KB, , , (s / z  1)
s (s / p  1)
Expressing the transfer function dB:
j
 1)
KB (
G ( jw)  z
 j
(j )(  1)
0 p
20 log | G ( j ) |
j  j
 20 log K B  20 log | (  1) | 20 log | j | 20 log | 1|
z o p
 Mechanics: We have 4 distinct terms to consider:

20logKB ----- ( constant gain in time constant format)

- 20log|j /ω0 | ----- (Pole at origin if wo=1)

- 20log|(j
g|(j  /1 + |p|) ------ ((Pole at 0 = p )

20log|(j/1 ±z)| ----- (zero at 0 = z )

wlg
 1 1 1 1 1 1

This is a sheet of 5 cycle

cycle, semi
semi-log
log paper.
paper
This is the type of paper usually used for
preparing Bode plots.

dB Mag
Phase
(deg)

wlg

 (rad/sec)
F
Frequency response plots
l t
 Different types of transfer functions---
functions
 K

w 1 jw 1
j w 1 jw
wo j wo 1
wo wo

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K constant
t t
G i iin dB
Gain

Log w
Ө
Ө= 0

Log w
j / o
jw/w
G i iin dB
Gain

20 dB/ dec

wo Log w
Ө
Ө= 90

Log w
-j w/wo = 1/ [jw/wo]–
, pole at the origin, jw/w
w0=1 o

G i iin dB
Gain

20 dB/ dec

Log w
wo
rad./ sec

For a pole at the origin draw a line with a slope of -20

Ө dB/decade that goes through 0 dB at 1 rad/sec

Log w
Ө= -90
1+ j (w/w
( / o)
G i iin dB
Gain
Corner plot
20 dB/ dec

wo Log w
Ө Corner frequency

90 1
-1
45 Ө= tan (w/wo)

0.1 wo Log w
~10 wo
M
Magnitude
it d and
d phase
h
jw
1
wo

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1 / [1+ j (w/w
( / o)]
G i iin dB
Gain

wo
Log w

20 dB/ dec
Ө -1
Ө= -tan
tan (w/wo)
~0.1 wo

Log w
-45
-90
~10 wo
 Using Matlab For Frequency Response

Instruction: We can use Matlab

W M tl b to
t run the
th frequency
f response for
f the
th previous
i example.
l WeW place
l
the transfer function in the form:

5000 ( s  10) [ 5000s  50000 ]


( s  1) ( s  500) [ s 2  501s  500]

The Matlab Program

num = [5000 50000];

den = [1 501 500];
Bode (num,den)
Using Matlab For Freq.
Response
Instruction: W
We can use Matlab
M tl b to
t run the
th frequency
f response for
f theth
previous example. We place the transfer function in the
form:
5000 ( s  10) [ 5000s  50000 ]

( s  1) ( s  500) [ s 2  501s  500]

The Matlab Program

num = [5000 50000];

den = [1 501 500];
B d (num,den)
Bode ( d )
 Bode Diagrams

From: U(1)
40

30

20

10

0
Phase (deg); Magnitude (dB)

-10
1 10 100 500
0

-20

-40
P

To: Y(1)

-60
100 (1  jw / 10 )
Bode for: G ( jw ) 
-80
(1  jw )(1  jw / 500 )
-100
-1 0 1 2 3 4
10 10 10 10 10 10

Frequency (rad/sec)

G( j)  tan1 ( / 10)  tan1 ( / 1)  tan1 ( / 500)

0 0
Initial angle=0 and final angle -90
Evaluating the frequency
response
 Single time constant circuits

Vo (s) = 1/ [1+sCR] vi (s) Vo (s) = sCR/ [1+sCR] vi (s)

[vo./ vi]= K / [1+{s/wo}] [vo./ vi]= K s / [1+{s/wo}]

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Freq. Response of Common
source amplifier
lifi

CLL= Cdb+Cnext stage

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Two closely spaced pole frequencies (s) and one zero transmission freq

Rs Rd Rd CL

Rs Rd CL CL
Exact Expressions
Roots—1+as+bs
R t 1+ +b 2
s=jw
s jw

 a  a  4b 2
s1, s 2 
2b

Rs Rd Rd CL

Rs Rd CL CL
High frequency behavior understanding —
including one capacitor at a time in circuit

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Exact method & approx. method----
Reason for difference in expressions of
two poles in both methods
 Exact methods analyses y including
g all
capacitances from the beginning. Thus
first p
pole has effect coming g from Cgd
g and
CL also
 For example , in approx. method,
V1(s)= vin (s) / [ Rs Cgs]
 Which is wrong
rong as Cgd is present,
present so
loading effect of output port comes
through Cgd which should be included in
V1(s) calculations Bits, pilani
 BITS Pilani
Pil i
Pilani Campus

Intuitive estimation of Poles and

Zeroes
Pole estimation Intuitively
t
transfer
f ffunction
ti T(s)
T( )

Zero has to be found out through observing circuit

Physical significance of pole
f
frequencies
i
 Gain degradation
degradation---Cgs
Cgs impedance
reduces vin splits between Rs and 1/sCgs
vgs ↓ gm vgs ↓ vout ↓

 Phase shift---due
Ph hift d tto time
ti constant
t t off
intermediate node----charging/discharging
takes time-
time  output waveform shifts on time
axis
D gain---
Dc i graphical
hi l view
i off input
i t
High freq
Low freq
Gain reduction/time shift —
graphical view of output High freq---gain
degradation, phase shift

Low freq
E
Example
l
 gm= 0.1mA/v
 Rd= 100k
GBW=wT = 4 x 109 rad/sec
 Rs= 1k
 Cgd= 5fF
 Cgs= 20fF
 Cdb= 0.1fF
 s= - 28.5
28 5 x 109 ± 26.6
26 6 x 109 Lower
 s= -55 x 109, -2 x 109 Hence, Critical wp1

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Frequency response (without
transmission zero frequency)

Two poles

Multiple poles

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If poles are close to each other
Easy way to find poles—
dominant pole approx.

= w-3dB

= 1.75 x 109----------------
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approx. estimate
S
Second
d pole
l magnitude
it d

= 56 x 109

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Drawback of dominant pole
approx method
th d
 Need to derive entire transfer function

 Need to know that system has dominant pole

response

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Open circuit time constant
method
th d

 Need to know that system has

dominant pole response

 No need to derive entire transfer

function

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Open circuit time constant

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Approx.

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Application of OCTC to evaluate bandwidth of
common source amplifier

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 = 1.7 x 109

= 2 x 109

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A other
Any th fast
f t method???
th d???

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Why does gain fall with pole
f
frequency?
?

 Because of fall in impedance

 Zin Zout
Zin,

 Signal gets reduced

 Time constant of these nodes shd. be

evaluated without finding transfer function

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M th d using
Method i Miller
Mill ththeorem

 No need to know that system has

dominant pole response

 No need to derive entire transfer function

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Miller’s theorem---split bridge component Z

Vy - Vx Vy

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Z2
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Why bridge capacitor, Cgd gets
multiplied
lti li d by
b (1+A)
(1 A) att input
i t port??
t??

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Bits, pilani
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 MILLER THEOREM---applications
 Miller theorem, help in circuit analysis process,

 the dual version is a powerful tool for designing

and understanding circuits based on modifying
impedance by additional current.

 Useful in design of typical circuits with negative

impedance as load cancellers, capacitance
eut a e s
neutralizers
 Negative impedance obtained by current
inversion is implemented by a non-inverting
amplifier
lifi with
i h Av > 1.
1 The
Th current changes
h i
its
direction as the output
p voltage
g is higher
g than the
input voltage.

 If the input voltage source has some internal

impedance Zint or if it is connected through another
impedance element, a positive feedback appears
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 Miller theorem not valid when-

R1 is the only path from x to yy. Another dominant

path (possibly through amplifier) should be
present

We canot apply miller thth. in backward manner ii.e

e
o/p to i/p as vo=A vin not valid.
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Typical application of miller
theorem
th

Z in parallel to main signal path

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Miller theorem applied
pp to CSA

= 13.3 x 109

This is Wp1 if RsCgs >> RoutCL

= 1.96 x 109

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Previous result

wp1= 2 x 109
wp2= 55 x 109

= 1.96 x 109

win = 13.3 x 109

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Zin

 Zin=>∞ at s= small
 When s large
 Zin1/ s[Cgs + (1 +A ) Cgd] ; A = gm (Rd ||ro || 1/sCdb)
 When s very large Rd and Cdb comes into effect
 Zin (1 /gm) ||ro || Rd || 1/sCdb
 BITS Pilani
Pil i
Pilani Campus

CSA—pole
CSA pole frequency behaviour
cases
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CSA----2 poles—2 different cases for
hi h frequency
high f behaviour
b h i

 Case1--- win is small, then wp1= w-3db= win

 Case2----wout is small, then wp1= w-3db= wout

D
Dominant
i t pole
l

 Case1-----first pole due to Cgs

 Case 2-------- first pole due to CL

Bits, pilani
Cgs dominates
dominates– simplified expression

1
wp2 
Rd C L
Then

1
wp 1 
R sC gs  ( 1  A ) Cgd
Cgs dominates— DOMINANT POLE

At s= UGB , |A(s)| = 1 (=0 dB)

dB)------ UGB = A0 w-3dB
1
wp1 
Rs C gs

W-3dB =wH = 1/ Rs Cgs

Why

Bits, pilani
 UGB=UGB csa≈ Ao / [Rs Cgs]
≈ wtmos [Rd / Rs]

W-3dB
3dB =wH = 1/ Rs Cgs

When Cgs (win) dominates---UGB csa may not

increase with increase in Ao
Ao.
As UGB = Ao / (Cgs +Ao Cgd) Rs
Rather it ma
may dec
dec. d
due
e to inc
inc. in W
hence Cgs, Cgd.
Impact of increasing AO on freq.
response when
h C Cgs d
dominates
i t
under various pole frequency
conditions

Using Bode plots

H
How tto iincrease A?
A can be increased by
 increasing gm,

 increasing Rout,

 increasing both

We are changing the design of amplifier

6 cases

Single pole response before UGB

 ----A is increased by increasing gm,

 ----A
A is increased by increasing Rout,
 ----- A is increased by increasing both

Two pole response before UGB

 ----A is increased by increasing gm,

 ----A
A is
i iincreased
dbby iincreasing
i Rout
 ----- A is increased by increasing both
Cgs dominates,
Case 1
C 1---Dominant
D i t pole
l response ---1
1 pole
l
as A is increased by increasing gm, keeping Rout same

Dominant pole response

|A|
wp2

UGB
W
Log scale
Wp1
= 1/ [Rs Cgs+ ACgd]
Si l Pole
Single P l Response
R
 When Cgs (win) dominates---UGB
dominates UGB csa may
not increase with increase in Ao.
 A UGB = A
As Ao / (C
(Cgs +A
+Ao CCgd)
d) R
Rs

Rather
R th it may dec.
d due
d tot inc.
i in
i W hence
h
Cgs, Cgd.
Cgs dominates,
Case 2--- win=wp1 ; wp2 pole > UGB
as A is increased by increasing Rout only

1
wp2 
|A| Rd C L

UGB wp2

W
Wp1 Log scale
= 1/ [[Rs Cgs+ ACgd]
g ] wp2
Cgs dominates,
Case 3--- win=wp1 ; wp2 pole > UGB
as A is increased by increasing gm, and Rout both

|A|

UGB wp2

W
Wp1 Log scale
= 1/ [[Rs Cgs+ ACgd]
g ] wp2
Cgs dominates,
Case 11--- 2 pole response—
response
as A is increased, keeping Rout same: (wp2 remains same),
UGB decreases

2 pole response
|A|
Dominant pole response

Wp1 wp2
2 w
= 1/ [Rs Cgs+ ACgd] Log scale
UGB
Cgs dominates,
Case 22--- 2 pole response—
response
as A is increased, increasing Rout only: (wp2 reduces ), UGB
decreases
1
wp2  2 pole response
|A| Rd C L

Dominant pole response

Wp1 wp2 w
= 1/ [Rs Cgs+ ACgd] Log scale
UGB
Cgs dominates,
Case 33--- 2 pole response—
response
as A is increased, increasing both: (wp2 reduces ), UGB
decreases
1
wp2  2 pole response
|A| Rd C L

Dominant pole response

Wp1 wp2 w
= 1/ [Rs Cgs+ ACgd] Log scale
UGB
CL = Cdb (here) dominates

1 Critical
wp11  Wp1= 2x 109
Rd C L

1
wp 2  Wp2 = 50 x 109
Rs C gs
 I this
In thi example
l
gm= 0.1mA/v
0 1mA/v
Rd= 100k
Rs= 1k
Cgd= 5fF Small, but Rd Cdb+CL is large
Cgs= 20fF
Cdb+ CL= 0.1fF
= 50 pf
Cgs= 20 ff
ff, does not dominate
 Unity
yggain bandwidth UGB (f
( t)
 A(s) = Ao wH here wH= w-3db
 For dominant pole, we can neglect second
pole
-
wz

 s= UGB at |A(s)| = 1 (=0 dB)------

dB) wt = A0 w-3dB

UGB =Wt = gm Rd / Rd CL = gm / CL
Bits, pilani

Here output pole is dominant

 Comparing
p g fH with fT of MOS

1
wH  wp1  = wH /2π
Rd C L
wH = w-3dB

UGB=Wt csa≈ gm / CL
nmos W-3dB
3dB =w
wH = 1/ Rout
Ro t CL

High fT means high UGB and high w-3dB bandwidth

Hence scaling is beneficial as small mos, so Cgs↓ gm
Bits, pilani
If CL dominates---UGB csa increases with increase
in A
As UGB = A / CL Rout
We can increase A in 2 ways
ways------
1--But as A increases (redoing the design keeping
Rout constt.,
constt power dissipation and output swing
also constt. ) gm UGB increases

But gm ↑Cgs ↑Rs Cgs ↑ second pole freq. reduces

may
y become dominant UGB may y reduce

2--A increases due to Rout ↑ first pole freq.

reducesUGB reduces
If CL dominates, Dominant pole response
case1-as A is increased
increased, keeping Rout same,
same UGB increases

|A| Dominant pole response

Wp2

UGB’

Wp1 UGB w
Log scale
= 1/ Rout CL
CL dominates, Dominant pole response

case 2--
2 as A iis increased
i d by
b Rout
R t ,
 wp1
1 reduces
d so UGB
remains same, wp2 nearly same

|A| Dominant pole response

Wp1 UGB’=UGB w
Log scale
= 1/ Rout CL
CL dominates, Dominant pole response

case 3--
3 as A iis increased
i d by
b inc.
i both
b th ,
 wp1
1 reduces
d
so UGB reduces

|A| Dominant pole response

w
Log
scale

Wp1 UGB’=UGB
UGB’=UGB
= 1/ Rout CL
If CL dominates, 2 pole response
CASE1--as
CASE1 A is increased, keeping Rout same (wp1 same),
UGB increases
Non Dominant pole response
|A|
Dominant pole response

wp2 w
Wp1
Log scale
= 1/ Rout CL
UGB
To keep power, output swing constt. , gm is to increase to increase A, or
w/L ↑  Cgs ↑  wp2 ↓
NOTE-----As
As W ↑ , parasitic capacitance Cdb at output ↑ , hence C L

↑ , so wp1 ↓ slightly
 If CL dominates, 2 pole response
CASE2----as
CASE2 A is increased, increasing Rout ,(wp1 inc.), UGB
increases

N D
Non Dominant
i t pole
l response
|A|
Dominant pole response

wp2
Wp1 w
Log scale
= 1/ Rout CL
UGB
Cgd A Cgd

If Cgs dominates---UGB csa may not

increase
As UGB = A / (Cgs +A Cgd) Rs

Bits, pilani
Caution

 For same design [gain x bandwidth ] always

remains constant

 When we redo the design and increase gain

gain,
increase in A may cause increase in
bandwidth.

 D ’ confuse
Don’t f iit with
i h above
b concept!!
!!
Zin, (graphical)

Low freq. value= ∞

Drops to low value quickly  because Cgs is large value

 Zout
Zout

Zout= Rd||r0 ; s small

When s large
Zin Rd ||r
|| o || 1/
1/sC
Cdb || 1/ sC
Cgd ; A=
A gm (Rd ||r
|| o|| 1/
1/sC
Cdb)

When s very large

Same as Zin
Zin (1 /gm) ||ro || Rd || 1/sCdb
Zout---graphical

Low freq. value

Low value at high freq

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Bits, pilani
Zero transmission frequency

Bits, pilani
Z
Zero transmission
t i i freq.
f
-
wz

Zero increases gain magnitude

Why?

 20 log
g ||A|| = 20 log
g [ (gm Rd)
 +√(1+ w2/wz2)
 -√(1+
√(1+ w2/wp12)
 -√(1+ w2/wp22)]
Physical
y explanation
p
i
iout

 When Cgd path becomes effective , i starts flowing

through
g Cgd,g , thus adding
g to (gm vgs ) current
 So iout increases, so Gm increases beyond gm, so gain
increases
 Gm =iout/vgs = (gm - sCgd );
 Gm =√ gm2 + (wCgd )2 ; > gm
Phase shift

output

input

-zero

+zero

Bits, pilani
Feed-forward path----origin of zero
Estimation of zero---easy way
i
iout

-
wz

vgs
Estimation of zero---easy
y way
y
 From transfer function, at s wz; A(s)0
vout(s)0
 So to estimate wz magnitude------
 Short output to ground
 Write KCL at output
p node
S Cgd (vgs-0) = gm vgs  wz = gm/ Cgd
 positive or RHS zero
zero,
 + zero when currents meet in anti phase at a node
 - zero when currents meet in same phase at a node
 For CSA wz = +2 x 1010 rad/sec
-ve zero example
l
Bode magnitude plot (with
t
transmission
i i zero

wz

Bits, pilani
 Bode plots— corner plots
Θ= - tan -1 (w/wp1) - tan -1 (w/wp2) - tan -1 (w/wz)
|A|
- 20dB p
per decade

- 40dB per decade

UGB
WP1 WP2 WZ

-20dB per dec

θ 0.1 WP1 10 WP1

-90

-180
~ -195

-270
Observations
 Gain starts falling at wp, Phase starts falling
at 0.1
0 1 wp
 At UGB total extra phase > 180o
 Already 180 phase from low freq
 So total phase ≈ 360o  output in phase
with
ith iinputt
 If feedback is used, output will add to input
 output amplitude will keep on growing till it
is limited by Vdd
 Bode plots— corner plots of our example
W 1 wz< wp2---increase
Wp1< 2 i ugb
b but
b severe phase
h degradation
d d i leads
l d to instability
i bili
|A|
- 20dB p
per decade

- 20dB per decade

UGB
WP1 WZ WP2
-20dB per dec

θ 0.1 WP1 10 WP1

-90

-180

-270
>-270
END

Bits, pilani
UGB=Wt csa≈ [gm Rd ] / [Rs Cgs]
= wt [Rd / Rs]

W-3dB =wH = 1/ Rs Cgs

Current through Cgd vs freq.

wp2

wz

wp1

Wp1 region

Wp2
p region
g

wz

Bits, pilani
BITS Pilani, Pilani Campus