FULL-CHIP ELECTRICAL RELIABILITY

VERIFICATION: A NEW APPROACH FOR

ADVANCED NODES

FRANK FENG
MENTOR, A SIEMENS BUSINESS

W H I T E P A P E R

D E S I G N T O S I L I C O N

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Full-Chip Electrical Reliability Verification: A New Approach for Advanced Nodes

INTRODUCTION
Chip designs using advanced technology take advantage of shrinkage in both gate size and
interconnect width/spacing to achieve greater functionality in a smaller device. Advanced
processes enable many more devices to be packed into a die with equal or lesser dimensions
than those of a previous node. For a 10 nm system-on-chip (SOC) design, it is not surprising to
see multi-billions of devices contained in an area under 1 cm2.

During the technology development stage, a gate library is developed that takes into account
reliability issues like electrostatic discharge (ESD), latch up (LUP), and time-dependent dielectric
breakdown (TDDB) under as-designed operation voltage ranges. For interconnect technology,
the co-planar interconnect spacing requirements across dielectrics is determined primarily by
optical and etching effects, with some consideration given to electrical parasitic impacts. Once
the gate library and technology design parameters are developed and packaged into a process
design kit (PDK), the place and route (P&R) tool uses them as input to P&R process, which is
tuned against the customary cost functions to achieve design rule checking (DRC) compliance,
timing, die size, IR drop, and electromigration (EM) design goals.

However, based on the experience of the foundries and integrated device manufacturers (IDMs),
the resulting layout still requires full-chip reliability verification (and possible layout
modifications) to prevent ESD along interconnect paths across multiple function blocks, LUP
across gates in the vicinity of IO circuits, and TDDB between interconnects of different nets
operated on different potentials. Such full-chip design verification practices are becoming
critical for technology at and below 28 nm. Without it, chip reliability failures become far more
likely during burn-in stage or in silicon.

DYNAMIC SIMULATION: WHY IT ISN’T PRACTICAL AT THE

FULL-CHIP LEVEL
Dynamic simulation is a technique used by various reliability verification approaches, mostly at
the cell/transistor level, to detect and prevent reliability issues. During full-chip design, cells and
transistors are connected through interconnect metal. Because the physical circuitry is
extremely condensed in advanced designs, and it often operates in multiple power domains,
new reliability concerns have emerged for the interconnect at both the chip and block levels.
Using dynamic simulation approaches to analyze ESD, LUP, TDDB, and electrical overstress (EOS)
problems is not feasible for block or whole chip designs, primarily because the large scale of the
circuits produces too much data to be processed to provide reliable simulation results in a
practical runtime.

STATIC DESIGN RULE EVOLUTION

From a strict technology perspective, the foundry or IDM always provides a reliability design kit
to circuit designers. However, in advanced node foundry/IDM technology kits, some critical
reliability design rules are often defined simply as guidelines, with little consideration given to
the feasibility of implementing them in an EDA tool. Some designers may choose the familiar
dynamic simulation approach, only to find the task is impractical.

For example, to prevent weak interconnect spots being burned by high ESD current surges, the
typical foundry/IDM rule defines the required wire width of the ESD path to be larger than some
criteria to survive an ESD event. Based on this guideline, fabless layout designers usually try to
use a traditional DRC tool to check the wire “width” against the rule criteria. However, a
traditional DRC tool can’t identify the direction of the electrical current path along polygon
shape (which is needed to determine the “width” of the path) and it doesn’t know how to

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Full-Chip Electrical Reliability Verification: A New Approach for Advanced Nodes

process the individual weighted widths of a parallel wires network to check against rule criteria.
In an attempt to facilitate automation and still meet rule requirements, foundries/IDMs have
begun more clearly defining a static current density check along ESD paths to enable designers
to find weak interconnect spots.

To prevent LUP issues, the foundry/IDM historically provided a DRC approach that performs
both a spacing check and a check for the presence of a guard ring between aggressor and
victim circuits at the chip assembly design stage. However, to enable a DRC tool to recognize
the polygons that are a part of these checks, designers often manually place markers on
designated polygons. In an iterative design process, it is difficult for designers to find a reliable
and consistent way to place markers at the appropriate locations on the layout. The marker
methodology requires designers to identify the circuits behind ESD resistors (connected to IO
Pads) that are involved in a LUP check. At the same time, the LUP sensitivity of these circuits
depends on the effective resistance of the ESD resistors. If the effective resistance (a value the
DRC tool doesn’t and can’t know) is bigger than the rule criteria, then circuits behind the ESD
resistors are considered to be isolated from LUP. Some markers also require the identification of
delta-operation voltage on polygons of different nets. However, depending on the delta-
operation voltage range, the spacing check criteria will differ. Foundries and IDMs are now
defining non-physical marker methodology that allows logic-driven layout (LDL) checking
functionality to find LUP circuits/nets that can be further transformed to physical shapes for a
property-annotated DRC check.

When verifying interconnect TDDB, the foundry/IDM provides a DRC approach to check the
spacing of polygons on different nets at the chip assembly design stage, where the spacing
criteria is dependent on delta-operation voltage. However, this methodology also uses multiple
physical markers representing different voltage values. Designers struggle to place markers of
the appropriate voltage values on polygons in nets of concern across the whole layout. Not only
do the physical markers not work well with delta-operation voltage dependent spacing criteria,
but assigning voltage from IO/power/ground pads to nets associated with inner circuits is
difficult. Foundries and IDMs are now defining voltage text/annotation methodology that
allows LDL checking functionality to propagate the voltage values into the entire circuit design,
and export nets of TDDB concern, for which the logical nets can be further transformed to
physical shapes for property-annotated DRC checks.

Employing static design rules is becoming a realistic and effective approach to manage
reliability issues in the chip/block-level design stage. Applying them to earlier design stages for
block or intellectual property (IP) reliability verification can also help reduce design iterations.
While the static approach may yield a small amount of over-pessimistic values (especially for
TDDB), its ability to detect complex reliability issues early in the design flow outweighs the
reasonable amount of manual work needed to evaluate these values prior to tapeout.

AUTOMATED RELIABILITY VERIFICATION WITH THE CALIBRE

PERC RELIABILITY PLATFORM
The Calibre® PERC™ reliability platform is specifically designed to perform a wide range of
complex reliability verification tasks using both standard rules from the foundry and custom
rules created by a design team. The Calibre PERC platform employs topological constraints to
verify that the correct circuit structures are in place wherever circuit design rules require them.
In addition, it also has the unique ability to use both netlist and layout (GDS) information
simultaneously to perform electrical checks that incorporate both layout-related parameters
and circuitry-dependent checks, enabling designers to address these complex verification
requirements.

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Full-Chip Electrical Reliability Verification: A New Approach for Advanced Nodes

Using Calibre PERC static simulation

and static voltage propagation in
conjunction with the Calibre PERC LDL
flow, foundries/IDMs can now clearly
define ESD and LUP rules with
assurance of 100% coverage based on
their rule requirements, and design
companies can implement automated
full-chip ESD, LUP, and TDDB rule
checking. The LDL flow for both SPEF
and SPICE networks is shown in Figure
1. This flow replaces the manual
marker flow and provides automated
reliability verification.

For ESD prevention, diode/MOS/

resistor as ESD or power-clamping
device clusters with enough strength
must be connected to IO, power,
ground, and cross-power domain
Figure 1: Steps in an LDL flow for both SPEF and SPICE
paths. The Calibre PERC platform networks.
provides the functionality to traverse
connectivity inside a SPICE netlist to
verify that the required (foundry or user-defined) ESD/power-clamping/back-to-back diodes
circuits exist or not. Device parameters of all corresponding circuits are also examined to ensure
the devices (individual/clustered) have sufficient strength for adequate ESD protection.

For advanced technology, the influence of interconnect parasitics is becoming significant. Of

concern is their impact on ESD across the whole chip, not just whether or not the ESD
protection circuits exist. To ensure ESD paths (connected by interconnect metals) function as
designed, it is critical to examine not only the placement of an ESD circuit, but also the effective
resistance along the ESD path. ESD paths are defined by either the foundry or the designer, and
typically contain multiple P-2-P segments. The “P” can be either a device pin or a cell port. Each
P-2-P segment is formed by pin pairs on same net, and pin pairs can be exported with an
annotation index for grouping purposes during simulation. The pin pairs will be transformed
into probe points in SPEF network. The Calibre PERC platform provides functionalities to search
ESD paths inside a SPICE netlist (Figure 2), extract non-redundant and reduced SPEF networks
for corresponding ESD paths, then run static simulation (in a user-defined grouping mechanism)
to calculate effective resistance of ESD paths meeting criteria (foundry or user-defined) or not.

Figure 2: Searching ESD

paths in a SPICE netlist.

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Full-Chip Electrical Reliability Verification: A New Approach for Advanced Nodes

Even when the electrical effective resistance meets criteria (usually an amount less than some
value in ohm), a huge ESD surge current (with different dynamic natures for different ESD
modes) can easily burn a weak interconnect spot. To prevent this, the current density along ESD
paths through all wire segments and via arrays should be examined to ensure current density is
less than some tolerant value. Designers can use Calibre PERC functionality to calculate DC
current densities along ESD paths. The flow is similar to determining the effective resistance of
ESD paths described above, but the SPEF network is un-reduced to preserve physical polygon
data for each wire segment and via area to enable calculation of the current density flowing
through them.

In addition to inserting guard-rings/guard-straps, LUP

prevention requires that spacing among polygons of
active diffusion, P+ active, and N-well device layers
operated at different potentials should be equal or
larger than a criteria for which the value increases
with increases of potential difference (delta-
operation voltage). This delta-voltage-dependent
spacing requirement for LUP checks is considered to
increase the reliability of a design. The circuits/
polygons scheme for LUP checking is shown in
Figure 3. The spacing criteria and delta-voltages are
usually grouped in a few bins, with one spacing
criteria assigned to one delta-voltage range. A user
input file is needed to assign the operational voltage
value to corresponding IO/power/ground ports.
Figure 3: Inside a LUP sensitive zone, safe spacing between
active diffusion, P+ active, and N-well polygons is
dependent on delta-voltage (Va-Vb and Va-Vc) range.

The Calibre PERC automated LUP checking flow performs the following steps:

1. Extract the layout netlist (standard circuit verification step provided by foundry/IDM).
2. Traverse connectivity graph, propagate voltage values from IO/power/ground ports into
internal nets based on user-defined constraints, and locate and export potential aggressor/
victim devices annotated with a propagated voltage value. Voltage propagation is executed
without alternating the voltage value. This voltage propagation behavior is reasonable for a
LUP check, since the potential LUP issue occurs close to an IO circuits region.
3. Generate unique physical layers that correspond to exported aggressor/victim devices.
These layers are usually a collection of polygons overlapped with device formation seed
shapes. This procedure also annotates the voltage value as a polygon property.
4. Process polygon data with annotated properties, and perform spacing DRC checks to find
any edges or polygon pairs that violate spacing criteria according to the delta-voltage
range.

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Full-Chip Electrical Reliability Verification: A New Approach for Advanced Nodes

For interconnect TDDB checks on block or full-chip designs, spacing checks among polygons of
the same interconnect layer on different nets are executed against criteria dependent on delta-
voltage range. The challenge is to propagate voltage value from IO/power/ground ports to
internal nets, such that all targeted nets for potential TDDB concerns have the appropriate
voltage value to annotate to their corresponding polygons. Unlike voltage propagation for LUP
checks, the voltage values starting propagation from IO/power/ground ports shift magnitude
when going out from some level-shifter-related circuits. Unless these voltage shifts are handled
appropriately, users will eventually see huge quantities of overly-pessimistic values. The static
voltage propagation engine doesn’t usually recognize this level of circuit function automatically.
It requires the user to design a static voltage propagation scheme that includes additional
information—like voltage values on some cell ports related to level-shifter circuits, or sub-circuit
pattern definitions—to enable the voltage propagation engine to manipulate voltage shifts.

The Calibre PERC platform contains functionality to perform static voltage propagation under a
user-constrained propagation scheme, assign appropriate voltage values to each concerned net,
annotate static voltage values to physical polygons of corresponding nets, and run spacing
checks that account for different spacing criteria versus different delta-voltage ranges. An
example of a static voltage propagation scheme is shown in Figure 4. The top port has a 3.3
voltage. Using static voltage propagation, 2.5, 1.8 or 1.2 V can be assigned to other nets inside
this circuit, depending on the design of the voltage propagation scheme. Voltage shift is
executed by user-defined sub-circuit patterns, or by acquiring the voltage value on the output
cell port of a level-shifter circuit by means of simulation. After completing static voltage
propagation, the LDL flow is used to annotate the voltage values to polygons in nets of concern
for DRC checking.

Figure 4: Automated static

voltage propagation with
the Calibre PERC platform.

There are multiple means by which designers can acquire cell port voltage data. For example, a
simplified level of dynamic simulation can be executed to acquire such data. The static voltage
propagation engine can be instructed to propagate voltage, break out when encountering the
above cell ports or sub-circuit patterns, and then continue propagation based on acquired
voltage data on cell port or voltage constraints defined with the sub-circuit patterns.

In a real-world application, if the voltage shift scheme/function is well-defined, designers will

see relatively clean run results. There may be some small quantity of overly-pessimistic voltage
annotation values, due to the nature of static propagation. However, the number of these values
is typically in a human-manageable range, so they can be manually processed toward final
tape-out without any significant effect on schedules.

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Full-Chip Electrical Reliability Verification: A New Approach for Advanced Nodes

SUMMARY
Advanced nodes are introducing new and complex reliability conditions that can’t be easily or
accurately checked using dynamic simulation or traditional physical and circuit verification
technology at the full-chip level. A new approach that employs static simulation and static
voltage propagation in conjunction with logic-driven layout analysis supports the development
of accurate, fast, automated reliability design verification for ESD, LUP, and TDDB issues. With
new methodologies and tools like the Calibre PERC reliability platform, designers can now verify
that their designs are protected against a wide range of reliability issues, ensuring that the final
product provides the performance and product life the market demands.

For more info:

visit http://mentor.com/PERC
or
contact a Calibre representative

For the latest product information, call us or visit: w w w . m e n t o r . c o m

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