J.

PRATHAPA REDDY
Phone No. : +918501874897
E-Mail: prathap492@gmail.com

OBJECTIVE
Seeking a full time position and looking to utilize my experience in the field of Digital RTL level Design and FPGA
Design.
PROFESSIONAL SNAPSHOT
 Acquired good understanding of various subjects such as Digital Electronics, VLSI Design.

 Good understanding of the FPGA design flow.
 Experience in RTL models in VHDL,Verilog on FPGA Design Using Chipscope.
 Hands on experience on FPGA & SOC hardware platform – Xilinx 7 series FPGA’s such as ARTIX7,VIRTEX7
FPGA boards.and ZYNQ(processor and FPGA)boards.

 Working knowledge of front end digital design tools such as XILINX ISE 14.7 Version Design Suite and VIVADO
Design Suite and ModelSim.
 Verification using FPGA platforms (prototyping on FPGA).

 Experience in using industry standard EDA tools for the front-end design and verification
 Exceptionally organised with a track record that demonstrates creativity and initiatives to achieve the set
goals.

VLSI DOMAIN SKILLS

HDLs VHDL ,Verilog
Xilinx ISE, VIVADO,EDK, SDK,
EDA TOOL Matlab/Simulink,Modelsim
and chipscope pro

DOMAIN FPGA Design flow,

RTL Coding, Simulation, Hardware
KNOWLEDGE Debugging,CDC,Timing closure,TCL scripting
chipscope pro analyzer, Uart, Ethernet, GTX Optical
fiber links(Aurora Protocol,)

QUALIFICATION HIGHLIGHTS

2015 M.Tech. (Digital Systems and Computer Electronics) from JNTU Hyderabad and secured 80%
marks

2012 B.Tech. (Electronics and Communication) from hitech college of engineering and
technology(Hyderabad) under JNTUH and secured 78% marks
2008 Secondary education from Narayana junior College (kurnool) and secured 93% marks
2006 Matriculation from Sri Bhagyodhaya High school(Bethamcherla), and secured 86% marks
PROFESSIONAL QUALIFICATION

1. Design Engineer in ASTRA MICROWAVE PRODUCTS LTD, Hyderabad, A.P. Aug-2015 to July 2018
2. Design Engineer in WIPRO Technologies,Hyderabad July 2018 to till date

EXPERIENCE(2y.10 m.): PROJECTS

Developed the embedded software for various subsystems such as RF BITE Contol Unit, ESM Processor Unit(ESMP) of
ESM system.
Hardware implementation and performance evaluation of various subsystems of ESM system with RADAR
applications on FPGA
FPGA implementation of configuring MGT(multi gigabit transceivers) for communication applications.
Working on Aurora protocol to send data from one board to another board(artix7 and virtex7)
HDL: Vhdl,Verilog
EDA Tools: Modelsim, VIVADO, sdk and ISE,MATLAB/SIMULINK
Operating system:Vxworks(RTOS)

ACADEMIC PROJECT

TITLE: DESIGN OF EFFICIENT BINARY COMPARATOR IN QUANTUM-DOT CELLULAR

AUTOMATA(QCA).
QCA is an attractive technology suitable for the development of ultra dense low-Power high performance
digital circuits.The project deals with the details that new design approach oriented to the implementation of
binary comparators in QCA. The new strategy has been exploited in the design of two different comparator
architectures and for several operands word lengths.

PERSONAL DETAILS

Date of Birth : 06th Jan 1991

Language Known : Telugu,Hindi & English.
Permanent Address : j. Prathapa reddy,
S/o J. Maddilety Swamy reddy,
H.No:3-61, Muddavaram(post),
Bethamcherla(Mandal),
Kurnool(District),518599(pin ocde).
DECLARATION:
I hereby declare that the above furnished details are true and correct to the best of my knowledge.

Place: Hyderabad
Date: (J.PRATHAPA REDDY)